/*
 * $Id: clock.c,v 1.2 2008/07/22 14:40:52 nbrk Exp $
 */
/*-
 * Copyright (c) 2005-2007, Kohsuke Ohtani
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the author nor the names of any co-contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

/*
 * clock.c - SA-110 Operatin System Timer driver.
 */

#include <kernel.h>
#include <timer.h>
#include <irq.h>

/*
 * This OST is an incrementing counter running at 3.6864 MHz.
 * It contains four 32-bit Match Registers which can be programmed
 * to cause periodic interrupts in SAIC.
 * For our main clock service we use channel 0.
 */
#define SAOST_INTRNO	26	/* channel 0 match */
#define SAOST_FREQ	3686400	/* ticks per second */

#define SAOST_BASE	0x90000000
#define  SAOST_OSMR(x)	(x * 4)	/* Match Register x */
#define  SAOST_OSCR	0x10
#define  SAOST_OSSR	0x14
#define  SAOST_OIER	0x1c

/*
 * Clock interrupt service routine.
 * No H/W reprogram is required.
 */
static int
clock_isr(int irq)
{
	irq_lock();

	timer_tick();

	irq_unlock();

	return INT_DONE;
}

/*
 * Initialize clock H/W chip.
 * Setup clock tick rate and install clock ISR.
 */
void
clock_init(void)
{
	int clock_irq;


	/* disable interrupts on matching all channels */
	*(volatile uint32_t *)(SAOST_BASE + SAOST_OIER) = 0;

	/* set channel 0 to 1/100 / sec */
	*(volatile uint32_t *)(SAOST_BASE + SAOST_OSMR(0)) = SAOST_FREQ / CONFIG_HZ;

	clock_irq = irq_attach(SAOST_INTRNO, IPL_CLOCK, 0, clock_isr, NULL);
	ASSERT(clock_irq != -1);

	/* enable interrupts on channel 0 compare */
	*(volatile uint32_t *)(SAOST_BASE + SAOST_OIER) = 1;
}