Annotation of sys/lib/libkern/arch/sh/sdivsi3.S, Revision 1.1.1.1
1.1 nbrk 1: /* $NetBSD: sdivsi3.S,v 1.8 2006/05/22 20:56:44 uwe Exp $ */
2:
3: /*-
4: * Copyright (c) 1990 The Regents of the University of California.
5: * All rights reserved.
6: *
7: * This code is derived from software contributed to Berkeley by
8: * William Jolitz.
9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: * 3. Neither the name of the University nor the names of its contributors
19: * may be used to endorse or promote products derived from this software
20: * without specific prior written permission.
21: *
22: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32: * SUCH DAMAGE.
33: *
34: * from: @(#)udivsi3.s 5.1 (Berkeley) 5/15/90
35: */
36:
37: #include <machine/asm.h>
38:
39: /* r0 <= r4 / r5 */
40: NENTRY(__sdivsi3)
41: mov r4, r0
42: mov r5, r1
43:
44: tst r1, r1
45: bt div_by_zero
46:
47: mov #0, r2
48: div0s r2, r0
49: subc r3, r3
50: subc r2, r0
51: div0s r1, r3
52: #define DIVSTEP rotcl r0; div1 r1, r3
53: /* repeat 32 times */
54: DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP;
55: DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP;
56: DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP;
57: DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP;
58: #undef DIVSTEP
59: rotcl r0
60:
61: rts
62: addc r2, r0
63:
64: div_by_zero:
65: #ifdef _KERNEL
66: rts
67: mov #0, r0
68: #else
69: mov.l r14, @-r15
70: sts.l pr, @-r15
71: mov r15, r14
72:
73: mov.l L_raise, r1
74: #ifdef PIC
75: 1: bsrf r1
76: #else
77: jsr @r1
78: #endif
79: mov #8, r4 /* delay slot. 8 <- SIGFPE. */
80: mov #0, r0
81:
82: lds.l @r15+, pr
83: rts
84: mov.l @r15+, r14
85:
86: .align 2
87: L_raise:
88: #ifdef PIC
89: .long _C_LABEL(raise)-(1b+4)
90: #else
91: .long _C_LABEL(raise)
92: #endif
93: #endif
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