Annotation of sys/dev/usb/uhcireg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: uhcireg.h,v 1.13 2003/07/08 13:19:09 nate Exp $ */
2: /* $NetBSD: uhcireg.h,v 1.16 2002/07/11 21:14:29 augustss Exp $ */
3: /* $FreeBSD: src/sys/dev/usb/uhcireg.h,v 1.12 1999/11/17 22:33:42 n_hibma Exp $ */
4:
5: /*
6: * Copyright (c) 1998 The NetBSD Foundation, Inc.
7: * All rights reserved.
8: *
9: * This code is derived from software contributed to The NetBSD Foundation
10: * by Lennart Augustsson (lennart@augustsson.net) at
11: * Carlstedt Research & Technology.
12: *
13: * Redistribution and use in source and binary forms, with or without
14: * modification, are permitted provided that the following conditions
15: * are met:
16: * 1. Redistributions of source code must retain the above copyright
17: * notice, this list of conditions and the following disclaimer.
18: * 2. Redistributions in binary form must reproduce the above copyright
19: * notice, this list of conditions and the following disclaimer in the
20: * documentation and/or other materials provided with the distribution.
21: * 3. All advertising materials mentioning features or use of this software
22: * must display the following acknowledgement:
23: * This product includes software developed by the NetBSD
24: * Foundation, Inc. and its contributors.
25: * 4. Neither the name of The NetBSD Foundation nor the names of its
26: * contributors may be used to endorse or promote products derived
27: * from this software without specific prior written permission.
28: *
29: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
30: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
31: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
32: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
33: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
34: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
37: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39: * POSSIBILITY OF SUCH DAMAGE.
40: */
41:
42: #ifndef _DEV_PCI_UHCIREG_H_
43: #define _DEV_PCI_UHCIREG_H_
44:
45: /*** PCI config registers ***/
46:
47: #define PCI_USBREV 0x60 /* USB protocol revision */
48: #define PCI_USBREV_MASK 0xff
49: #define PCI_USBREV_PRE_1_0 0x00
50: #define PCI_USBREV_1_0 0x10
51: #define PCI_USBREV_1_1 0x11
52:
53: #define PCI_LEGSUP 0xc0 /* Legacy Support register */
54: #define PCI_LEGSUP_USBPIRQDEN 0x2000 /* USB PIRQ D Enable */
55:
56: #define PCI_CBIO 0x20 /* configuration base IO */
57:
58: #define PCI_INTERFACE_UHCI 0x00
59:
60: /*** UHCI registers ***/
61:
62: #define UHCI_CMD 0x00
63: #define UHCI_CMD_RS 0x0001
64: #define UHCI_CMD_HCRESET 0x0002
65: #define UHCI_CMD_GRESET 0x0004
66: #define UHCI_CMD_EGSM 0x0008
67: #define UHCI_CMD_FGR 0x0010
68: #define UHCI_CMD_SWDBG 0x0020
69: #define UHCI_CMD_CF 0x0040
70: #define UHCI_CMD_MAXP 0x0080
71:
72: #define UHCI_STS 0x02
73: #define UHCI_STS_USBINT 0x0001
74: #define UHCI_STS_USBEI 0x0002
75: #define UHCI_STS_RD 0x0004
76: #define UHCI_STS_HSE 0x0008
77: #define UHCI_STS_HCPE 0x0010
78: #define UHCI_STS_HCH 0x0020
79: #define UHCI_STS_ALLINTRS 0x003f
80:
81: #define UHCI_INTR 0x04
82: #define UHCI_INTR_TOCRCIE 0x0001
83: #define UHCI_INTR_RIE 0x0002
84: #define UHCI_INTR_IOCE 0x0004
85: #define UHCI_INTR_SPIE 0x0008
86:
87: #define UHCI_FRNUM 0x06
88: #define UHCI_FRNUM_MASK 0x03ff
89:
90:
91: #define UHCI_FLBASEADDR 0x08
92:
93: #define UHCI_SOF 0x0c
94: #define UHCI_SOF_MASK 0x7f
95:
96: #define UHCI_PORTSC1 0x010
97: #define UHCI_PORTSC2 0x012
98: #define UHCI_PORTSC_CCS 0x0001
99: #define UHCI_PORTSC_CSC 0x0002
100: #define UHCI_PORTSC_PE 0x0004
101: #define UHCI_PORTSC_POEDC 0x0008
102: #define UHCI_PORTSC_LS 0x0030
103: #define UHCI_PORTSC_LS_SHIFT 4
104: #define UHCI_PORTSC_RD 0x0040
105: #define UHCI_PORTSC_LSDA 0x0100
106: #define UHCI_PORTSC_PR 0x0200
107: #define UHCI_PORTSC_OCI 0x0400
108: #define UHCI_PORTSC_OCIC 0x0800
109: #define UHCI_PORTSC_SUSP 0x1000
110:
111: #define URWMASK(x) \
112: ((x) & (UHCI_PORTSC_SUSP | UHCI_PORTSC_PR | UHCI_PORTSC_RD | UHCI_PORTSC_PE))
113:
114: #define UHCI_FRAMELIST_COUNT 1024
115: #define UHCI_FRAMELIST_ALIGN 4096
116:
117: #define UHCI_TD_ALIGN 16
118: #define UHCI_QH_ALIGN 16
119:
120: typedef u_int32_t uhci_physaddr_t;
121: #define UHCI_PTR_T 0x00000001
122: #define UHCI_PTR_TD 0x00000000
123: #define UHCI_PTR_QH 0x00000002
124: #define UHCI_PTR_VF 0x00000004
125:
126: /*
127: * Wait this long after a QH has been removed. This gives that HC a
128: * chance to stop looking at it before it's recycled.
129: */
130: #define UHCI_QH_REMOVE_DELAY 5
131:
132: /*
133: * The Queue Heads and Transfer Descriptors are accessed
134: * by both the CPU and the USB controller which run
135: * concurrently. This means that they have to be accessed
136: * with great care. As long as the data structures are
137: * not linked into the controller's frame list they cannot
138: * be accessed by it and anything goes. As soon as a
139: * TD is accessible by the controller it "owns" the td_status
140: * field; it will not be written by the CPU. Similarly
141: * the controller "owns" the qh_elink field.
142: */
143:
144: typedef struct {
145: uhci_physaddr_t td_link;
146: u_int32_t td_status;
147: #define UHCI_TD_GET_ACTLEN(s) (((s) + 1) & 0x3ff)
148: #define UHCI_TD_ZERO_ACTLEN(t) ((t) | 0x3ff)
149: #define UHCI_TD_BITSTUFF 0x00020000
150: #define UHCI_TD_CRCTO 0x00040000
151: #define UHCI_TD_NAK 0x00080000
152: #define UHCI_TD_BABBLE 0x00100000
153: #define UHCI_TD_DBUFFER 0x00200000
154: #define UHCI_TD_STALLED 0x00400000
155: #define UHCI_TD_ACTIVE 0x00800000
156: #define UHCI_TD_IOC 0x01000000
157: #define UHCI_TD_IOS 0x02000000
158: #define UHCI_TD_LS 0x04000000
159: #define UHCI_TD_GET_ERRCNT(s) (((s) >> 27) & 3)
160: #define UHCI_TD_SET_ERRCNT(n) ((n) << 27)
161: #define UHCI_TD_SPD 0x20000000
162: u_int32_t td_token;
163: #define UHCI_TD_PID_IN 0x00000069
164: #define UHCI_TD_PID_OUT 0x000000e1
165: #define UHCI_TD_PID_SETUP 0x0000002d
166: #define UHCI_TD_GET_PID(s) ((s) & 0xff)
167: #define UHCI_TD_SET_DEVADDR(a) ((a) << 8)
168: #define UHCI_TD_GET_DEVADDR(s) (((s) >> 8) & 0x7f)
169: #define UHCI_TD_SET_ENDPT(e) (((e)&0xf) << 15)
170: #define UHCI_TD_GET_ENDPT(s) (((s) >> 15) & 0xf)
171: #define UHCI_TD_SET_DT(t) ((t) << 19)
172: #define UHCI_TD_GET_DT(s) (((s) >> 19) & 1)
173: #define UHCI_TD_SET_MAXLEN(l) (((l)-1) << 21)
174: #define UHCI_TD_GET_MAXLEN(s) ((((s) >> 21) + 1) & 0x7ff)
175: #define UHCI_TD_MAXLEN_MASK 0xffe00000
176: u_int32_t td_buffer;
177: } uhci_td_t;
178:
179: #define UHCI_TD_ERROR (UHCI_TD_BITSTUFF|UHCI_TD_CRCTO|UHCI_TD_BABBLE|UHCI_TD_DBUFFER|UHCI_TD_STALLED)
180:
181: #define UHCI_TD_SETUP(len, endp, dev) (UHCI_TD_SET_MAXLEN(len) | \
182: UHCI_TD_SET_ENDPT(endp) | UHCI_TD_SET_DEVADDR(dev) | UHCI_TD_PID_SETUP)
183: #define UHCI_TD_OUT(len, endp, dev, dt) (UHCI_TD_SET_MAXLEN(len) | \
184: UHCI_TD_SET_ENDPT(endp) | UHCI_TD_SET_DEVADDR(dev) | \
185: UHCI_TD_PID_OUT | UHCI_TD_SET_DT(dt))
186: #define UHCI_TD_IN(len, endp, dev, dt) (UHCI_TD_SET_MAXLEN(len) | \
187: UHCI_TD_SET_ENDPT(endp) | UHCI_TD_SET_DEVADDR(dev) | UHCI_TD_PID_IN | \
188: UHCI_TD_SET_DT(dt))
189:
190: typedef struct {
191: uhci_physaddr_t qh_hlink;
192: uhci_physaddr_t qh_elink;
193: } uhci_qh_t;
194:
195: #endif /* _DEV_PCI_UHCIREG_H_ */
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