Annotation of sys/dev/usb/ehcireg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: ehcireg.h,v 1.13 2005/10/28 04:36:42 fgsch Exp $ */
! 2: /* $NetBSD: ehcireg.h,v 1.17 2004/06/23 06:45:56 mycroft Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 2001 The NetBSD Foundation, Inc.
! 6: * All rights reserved.
! 7: *
! 8: * This code is derived from software contributed to The NetBSD Foundation
! 9: * by Lennart Augustsson (lennart@augustsson.net).
! 10: *
! 11: * Redistribution and use in source and binary forms, with or without
! 12: * modification, are permitted provided that the following conditions
! 13: * are met:
! 14: * 1. Redistributions of source code must retain the above copyright
! 15: * notice, this list of conditions and the following disclaimer.
! 16: * 2. Redistributions in binary form must reproduce the above copyright
! 17: * notice, this list of conditions and the following disclaimer in the
! 18: * documentation and/or other materials provided with the distribution.
! 19: * 3. All advertising materials mentioning features or use of this software
! 20: * must display the following acknowledgement:
! 21: * This product includes software developed by the NetBSD
! 22: * Foundation, Inc. and its contributors.
! 23: * 4. Neither the name of The NetBSD Foundation nor the names of its
! 24: * contributors may be used to endorse or promote products derived
! 25: * from this software without specific prior written permission.
! 26: *
! 27: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
! 28: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
! 29: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
! 30: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
! 31: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
! 32: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
! 33: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
! 34: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
! 35: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
! 36: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 37: * POSSIBILITY OF SUCH DAMAGE.
! 38: */
! 39:
! 40: /*
! 41: * The EHCI 1.0 spec can be found at
! 42: * http://developer.intel.com/technology/usb/download/ehci-r10.pdf
! 43: * and the USB 2.0 spec at
! 44: * http://www.usb.org/developers/data/usb_20.zip
! 45: */
! 46:
! 47: #ifndef _DEV_PCI_EHCIREG_H_
! 48: #define _DEV_PCI_EHCIREG_H_
! 49:
! 50: /*** PCI config registers ***/
! 51:
! 52: #define PCI_CBMEM 0x10 /* configuration base MEM */
! 53:
! 54: #define PCI_INTERFACE_EHCI 0x20
! 55:
! 56: #define PCI_USBREV 0x60 /* RO USB protocol revision */
! 57: #define PCI_USBREV_MASK 0xff
! 58: #define PCI_USBREV_PRE_1_0 0x00
! 59: #define PCI_USBREV_1_0 0x10
! 60: #define PCI_USBREV_1_1 0x11
! 61: #define PCI_USBREV_2_0 0x20
! 62:
! 63: #define PCI_EHCI_FLADJ 0x61 /*RW Frame len adj, SOF=59488+6*fladj */
! 64:
! 65: #define PCI_EHCI_PORTWAKECAP 0x62 /* RW Port wake caps (opt) */
! 66:
! 67: /* EHCI Extended Capabilities */
! 68: #define EHCI_EC_LEGSUP 0x01
! 69:
! 70: #define EHCI_EECP_NEXT(x) (((x) >> 8) & 0xff)
! 71: #define EHCI_EECP_ID(x) ((x) & 0xff)
! 72:
! 73: #define EHCI_LEGSUP_LEGSUP 0x00
! 74: #define EHCI_LEGSUP_OSOWNED 0x01000000 /* OS owned semaphore */
! 75: #define EHCI_LEGSUP_BIOSOWNED 0x00010000 /* BIOS owned semaphore */
! 76: #define PCI_LEGSUP_USBLEGCTLSTS 0x04
! 77:
! 78: /*** EHCI capability registers ***/
! 79:
! 80: #define EHCI_CAPLENGTH 0x00 /*RO Capability register length field */
! 81: /* reserved 0x01 */
! 82: #define EHCI_HCIVERSION 0x02 /* RO Interface version number */
! 83:
! 84: #define EHCI_HCSPARAMS 0x04 /* RO Structural parameters */
! 85: #define EHCI_HCS_DEBUGPORT(x) (((x) >> 20) & 0xf)
! 86: #define EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000)
! 87: #define EHCI_HCS_N_CC(x) (((x) >> 12) & 0xf) /* # of companion ctlrs */
! 88: #define EHCI_HCS_N_PCC(x) (((x) >> 8) & 0xf) /* # of ports per comp. */
! 89: #define EHCI_HCS_PRR(x) ((x) & 0x80) /* port routing rules */
! 90: #define EHCI_HCS_PPC(x) ((x) & 0x10) /* port power control */
! 91: #define EHCI_HCS_N_PORTS(x) ((x) & 0xf) /* # of ports */
! 92:
! 93: #define EHCI_HCCPARAMS 0x08 /* RO Capability parameters */
! 94: #define EHCI_HCC_EECP(x) (((x) >> 8) & 0xff) /* extended ports caps */
! 95: #define EHCI_HCC_IST(x) (((x) >> 4) & 0xf) /* isoc sched threshold */
! 96: #define EHCI_HCC_ASPC(x) ((x) & 0x4) /* async sched park cap */
! 97: #define EHCI_HCC_PFLF(x) ((x) & 0x2) /* prog frame list flag */
! 98: #define EHCI_HCC_64BIT(x) ((x) & 0x1) /* 64 bit address cap */
! 99:
! 100: #define EHCI_HCSP_PORTROUTE 0x0c /*RO Companion port route description */
! 101:
! 102: /* EHCI operational registers. Offset given by EHCI_CAPLENGTH register */
! 103: #define EHCI_USBCMD 0x00 /* RO, RW, WO Command register */
! 104: #define EHCI_CMD_ITC_M 0x00ff0000 /* RW interrupt threshold ctrl */
! 105: #define EHCI_CMD_ITC_1 0x00010000
! 106: #define EHCI_CMD_ITC_2 0x00020000
! 107: #define EHCI_CMD_ITC_4 0x00040000
! 108: #define EHCI_CMD_ITC_8 0x00080000
! 109: #define EHCI_CMD_ITC_16 0x00100000
! 110: #define EHCI_CMD_ITC_32 0x00200000
! 111: #define EHCI_CMD_ITC_64 0x00400000
! 112: #define EHCI_CMD_ASPME 0x00000800 /* RW/RO async park enable */
! 113: #define EHCI_CMD_ASPMC 0x00000300 /* RW/RO async park count */
! 114: #define EHCI_CMD_LHCR 0x00000080 /* RW light host ctrl reset */
! 115: #define EHCI_CMD_IAAD 0x00000040 /* RW intr on async adv door bell */
! 116: #define EHCI_CMD_ASE 0x00000020 /* RW async sched enable */
! 117: #define EHCI_CMD_PSE 0x00000010 /* RW periodic sched enable */
! 118: #define EHCI_CMD_FLS_M 0x0000000c /* RW/RO frame list size */
! 119: #define EHCI_CMD_FLS(x) (((x) >> 2) & 3) /* RW/RO frame list size */
! 120: #define EHCI_CMD_HCRESET 0x00000002 /* RW reset */
! 121: #define EHCI_CMD_RS 0x00000001 /* RW run/stop */
! 122:
! 123: #define EHCI_USBSTS 0x04 /* RO, RW, RWC Status register */
! 124: #define EHCI_STS_ASS 0x00008000 /* RO async sched status */
! 125: #define EHCI_STS_PSS 0x00004000 /* RO periodic sched status */
! 126: #define EHCI_STS_REC 0x00002000 /* RO reclamation */
! 127: #define EHCI_STS_HCH 0x00001000 /* RO host controller halted */
! 128: #define EHCI_STS_IAA 0x00000020 /* RWC interrupt on async adv */
! 129: #define EHCI_STS_HSE 0x00000010 /* RWC host system error */
! 130: #define EHCI_STS_FLR 0x00000008 /* RWC frame list rollover */
! 131: #define EHCI_STS_PCD 0x00000004 /* RWC port change detect */
! 132: #define EHCI_STS_ERRINT 0x00000002 /* RWC error interrupt */
! 133: #define EHCI_STS_INT 0x00000001 /* RWC interrupt */
! 134: #define EHCI_STS_INTRS(x) ((x) & 0x3f)
! 135:
! 136: #define EHCI_NORMAL_INTRS (EHCI_STS_IAA | EHCI_STS_HSE | EHCI_STS_PCD | EHCI_STS_ERRINT | EHCI_STS_INT)
! 137:
! 138: #define EHCI_USBINTR 0x08 /* RW Interrupt register */
! 139: #define EHCI_INTR_IAAE 0x00000020 /* interrupt on async advance ena */
! 140: #define EHCI_INTR_HSEE 0x00000010 /* host system error ena */
! 141: #define EHCI_INTR_FLRE 0x00000008 /* frame list rollover ena */
! 142: #define EHCI_INTR_PCIE 0x00000004 /* port change ena */
! 143: #define EHCI_INTR_UEIE 0x00000002 /* USB error intr ena */
! 144: #define EHCI_INTR_UIE 0x00000001 /* USB intr ena */
! 145:
! 146: #define EHCI_FRINDEX 0x0c /* RW Frame Index register */
! 147:
! 148: #define EHCI_CTRLDSSEGMENT 0x10 /* RW Control Data Structure Segment */
! 149:
! 150: #define EHCI_PERIODICLISTBASE 0x14 /* RW Periodic List Base */
! 151: #define EHCI_ASYNCLISTADDR 0x18 /* RW Async List Base */
! 152:
! 153: #define EHCI_CONFIGFLAG 0x40 /* RW Configure Flag register */
! 154: #define EHCI_CONF_CF 0x00000001 /* RW configure flag */
! 155:
! 156: #define EHCI_PORTSC(n) (0x40+4*(n)) /* RO, RW, RWC Port Status reg */
! 157: #define EHCI_PS_WKOC_E 0x00400000 /* RW wake on over current ena */
! 158: #define EHCI_PS_WKDSCNNT_E 0x00200000 /* RW wake on disconnect ena */
! 159: #define EHCI_PS_WKCNNT_E 0x00100000 /* RW wake on connect ena */
! 160: #define EHCI_PS_PTC 0x000f0000 /* RW port test control */
! 161: #define EHCI_PS_PIC 0x0000c000 /* RW port indicator control */
! 162: #define EHCI_PS_PO 0x00002000 /* RW port owner */
! 163: #define EHCI_PS_PP 0x00001000 /* RW,RO port power */
! 164: #define EHCI_PS_LS 0x00000c00 /* RO line status */
! 165: #define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == 0x00000400)
! 166: #define EHCI_PS_PR 0x00000100 /* RW port reset */
! 167: #define EHCI_PS_SUSP 0x00000080 /* RW suspend */
! 168: #define EHCI_PS_FPR 0x00000040 /* RW force port resume */
! 169: #define EHCI_PS_OCC 0x00000020 /* RWC over current change */
! 170: #define EHCI_PS_OCA 0x00000010 /* RO over current active */
! 171: #define EHCI_PS_PEC 0x00000008 /* RWC port enable change */
! 172: #define EHCI_PS_PE 0x00000004 /* RW port enable */
! 173: #define EHCI_PS_CSC 0x00000002 /* RWC connect status change */
! 174: #define EHCI_PS_CS 0x00000001 /* RO connect status */
! 175: #define EHCI_PS_CLEAR (EHCI_PS_OCC|EHCI_PS_PEC|EHCI_PS_CSC)
! 176:
! 177: #define EHCI_PORT_RESET_COMPLETE 2 /* ms */
! 178:
! 179: #define EHCI_FLALIGN_ALIGN 0x1000
! 180:
! 181: /* No data structure may cross a page boundary. */
! 182: #define EHCI_PAGE_SIZE 0x1000
! 183: #define EHCI_PAGE(x) ((x) &~ 0xfff)
! 184: #define EHCI_PAGE_OFFSET(x) ((x) & 0xfff)
! 185:
! 186: typedef u_int32_t ehci_link_t;
! 187: #define EHCI_LINK_TERMINATE 0x00000001
! 188: #define EHCI_LINK_TYPE(x) ((x) & 0x00000006)
! 189: #define EHCI_LINK_ITD 0x0
! 190: #define EHCI_LINK_QH 0x2
! 191: #define EHCI_LINK_SITD 0x4
! 192: #define EHCI_LINK_FSTN 0x6
! 193: #define EHCI_LINK_ADDR(x) ((x) &~ 0x1f)
! 194:
! 195: typedef u_int32_t ehci_physaddr_t;
! 196: #define EHCI_BUFPTR_MASK 0xfffff000
! 197:
! 198: /* Isochronous Transfer Descriptor */
! 199: #define EHCI_ITD_NTRANS 8
! 200: #define EHCI_ITD_NBUFFERS 7
! 201: typedef struct {
! 202: ehci_link_t itd_next;
! 203: u_int32_t itd_trans[EHCI_ITD_NTRANS];
! 204: #define EHCI_ITD_GET_OFFSET(x) (((x) >> 0) & 0xfff) /* offset from buf ptr */
! 205: #define EHCI_ITD_SET_OFFSET(x) (x)
! 206: #define EHCI_ITD_GET_PG(x) (((x) >> 12) & 0x7) /* buffer page */
! 207: #define EHCI_ITD_SET_PG(x) ((x) << 12)
! 208: #define EHCI_ITD_GET_IOC(x) (((x) >> 15) & 0x1) /* interrupt on complete */
! 209: #define EHCI_ITD_IOC 0x00008000
! 210: #define EHCI_ITD_GET_XLEN(x) (((x) >> 16) & 0xfff) /* transaction length */
! 211: #define EHCI_ITD_SET_XLEN(x) ((x) << 12)
! 212: #define EHCI_ITD_GET_STATUS(x) (((x) >> 28) & 0xf) /* duh */
! 213: #define EHCI_ITD_SET_STATUS(x) ((x) << 28)
! 214: #define EHCI_ITD_ACTIVE 0x8
! 215: #define EHCI_ITD_BUFERR 0x4
! 216: #define EHCI_ITD_BABBLE 0x2
! 217: #define EHCI_ITD_XACTERR 0x1
! 218: ehci_physaddr_t itd_buffer[EHCI_ITD_NBUFFERS];
! 219: /* page (buffer) 0 */
! 220: #define EHCI_ITD_GET_ADDR(x) (((x) >> 0) & 0x7f) /* endpoint addr */
! 221: #define EHCI_ITD_SET_ADDR(x) (x)
! 222: #define EHCI_ITD_GET_ENDPT(x) (((x) >> 8) & 0xf) /* endpoint no */
! 223: #define EHCI_ITD_SET_ENDPT(x) ((x) << 8)
! 224: /* page (buffer) 2 */
! 225: #define EHCI_ITD_GET_MPS(x) (((x) >> 0) & 0x7ff) /* max packet size */
! 226: #define EHCI_ITD_SET_MPS(x) (x)
! 227: #define EHCI_ITD_DIRECTION 0x00000800
! 228: /* page (buffer) 3 */
! 229: #define EHCI_ITD_GET_MULTI(x) (((x) >> 0) & 0x3) /* trans per microframe */
! 230: #define EHCI_ITD_SET_MULTI(x) (x)
! 231: ehci_physaddr_t itd_buffer_hi[EHCI_ITD_NBUFFERS]; /* 64bit */
! 232: } ehci_itd_t;
! 233: #define EHCI_ITD_ALIGN 32
! 234:
! 235: /* Split Transaction Isochronous Transfer Descriptor */
! 236: #define EHCI_SITD_NBUFFERS 2
! 237: typedef struct {
! 238: ehci_link_t sitd_next;
! 239: u_int32_t sitd_endp;
! 240: #define EHCI_SITD_GET_ADDR(x) (((x) >> 0) & 0x7f) /* endpoint addr */
! 241: #define EHCI_SITD_SET_ADDR(x) (x)
! 242: #define EHCI_SITD_GET_ENDPT(x) (((x) >> 8) & 0xf) /* endpoint no */
! 243: #define EHCI_SITD_SET_ENDPT(x) ((x) << 8)
! 244: #define EHCI_SITD_GET_HUBA(x) (((x) >> 16) & 0x7f) /* hub address */
! 245: #define EHCI_SITD_SET_HUBA(x) ((x) << 16)
! 246: #define EHCI_SITD_GET_PORT(x) (((x) >> 23) & 0x7f) /* hub port */
! 247: #define EHCI_SITD_SET_PORT(x) ((x) << 23)
! 248: u_int32_t sitd_sched;
! 249: #define EHCI_QH_GET_SMASK(x) (((x) >> 0) & 0xff) /* intr sched mask */
! 250: #define EHCI_QH_SET_SMASK(x) ((x) << 0)
! 251: #define EHCI_QH_GET_CMASK(x) (((x) >> 8) & 0xff) /* split completion mask */
! 252: #define EHCI_QH_SET_CMASK(x) ((x) << 8)
! 253: u_int32_t sitd_trans;
! 254: #define EHCI_SITD_GET_STATUS(x) (((x) >> 0) & 0xff) /* status */
! 255: #define EHCI_SITD_ACTIVE 0x80
! 256: #define EHCI_SITD_ERR 0x40
! 257: #define EHCI_SITD_BUFERR 0x20
! 258: #define EHCI_SITD_BABBLE 0x10
! 259: #define EHCI_SITD_XACTERR 0x08
! 260: #define EHCI_SITD_MISSEDMICRO 0x04
! 261: #define EHCI_SITD_SPLITXSTATE 0x02
! 262: #define EHCI_SITD_GET_CPROG(x) (((x) >> 8) & 0xff) /* c-mask progress */
! 263: #define EHCI_SITD_SET_CPROG(x) (((x) >> 8) & 0xff)
! 264: #define EHCI_SITD_GET_BYTES(x) (((x) >> 16) & 0x7ff) /* bytes to transfer */
! 265: #define EHCI_SITD_SET_BYTES(x) ((x) << 16)
! 266: #define EHCI_SITD_GET_PG(x) (((x) >> 30) & 0x1) /* buffer page */
! 267: #define EHCI_SITD_SET_PG(x) ((x) << 30)
! 268: #define EHCI_SITD_IOC 0x80000000 /* interrupt on complete */
! 269: ehci_physaddr_t sitd_buffer[EHCI_SITD_NBUFFERS];
! 270: /* page (buffer) 0 */
! 271: #define EHCI_SITD_GET_OFFSET(x) (((x) >> 0) & 0xfff) /* current offset */
! 272: /* page (buffer) 1 */
! 273: #define EHCI_SITD_GET_TCOUNT(x) (((x) >> 0) & 0x3) /* transaction count */
! 274: #define EHCI_SITD_GET_TP(x) (((x) >> 3) & 0x3) /* transaction position */
! 275: #define EHCI_SITD_SET_TP(x) ((x) << 3)
! 276: #define EHCI_SITD_TP_ALL 0x0
! 277: #define EHCI_SITD_TP_BEGIN 0x1
! 278: #define EHCI_SITD_TP_MIDDLE 0x2
! 279: #define EHCI_SITD_TP_END 0x3
! 280: ehci_link_t sitd_back;
! 281: ehci_physaddr_t sitd_buffer_hi[EHCI_SITD_NBUFFERS]; /* 64bit */
! 282: } ehci_sitd_t;
! 283: #define EHCI_SITD_ALIGN 32
! 284:
! 285: /* Queue Element Transfer Descriptor */
! 286: #define EHCI_QTD_NBUFFERS 5
! 287: typedef struct {
! 288: ehci_link_t qtd_next;
! 289: ehci_link_t qtd_altnext;
! 290: u_int32_t qtd_status;
! 291: #define EHCI_QTD_GET_STATUS(x) (((x) >> 0) & 0xff)
! 292: #define EHCI_QTD_SET_STATUS(x) ((x) << 0)
! 293: #define EHCI_QTD_ACTIVE 0x80
! 294: #define EHCI_QTD_HALTED 0x40
! 295: #define EHCI_QTD_BUFERR 0x20
! 296: #define EHCI_QTD_BABBLE 0x10
! 297: #define EHCI_QTD_XACTERR 0x08
! 298: #define EHCI_QTD_MISSEDMICRO 0x04
! 299: #define EHCI_QTD_SPLITXSTATE 0x02
! 300: #define EHCI_QTD_PINGSTATE 0x01
! 301: #define EHCI_QTD_STATERRS 0x7c
! 302: #define EHCI_QTD_GET_PID(x) (((x) >> 8) & 0x3)
! 303: #define EHCI_QTD_SET_PID(x) ((x) << 8)
! 304: #define EHCI_QTD_PID_OUT 0x0
! 305: #define EHCI_QTD_PID_IN 0x1
! 306: #define EHCI_QTD_PID_SETUP 0x2
! 307: #define EHCI_QTD_GET_CERR(x) (((x) >> 10) & 0x3)
! 308: #define EHCI_QTD_SET_CERR(x) ((x) << 10)
! 309: #define EHCI_QTD_GET_C_PAGE(x) (((x) >> 12) & 0x7)
! 310: #define EHCI_QTD_SET_C_PAGE(x) ((x) << 12)
! 311: #define EHCI_QTD_GET_IOC(x) (((x) >> 15) & 0x1)
! 312: #define EHCI_QTD_IOC 0x00008000
! 313: #define EHCI_QTD_GET_BYTES(x) (((x) >> 16) & 0x7fff)
! 314: #define EHCI_QTD_SET_BYTES(x) ((x) << 16)
! 315: #define EHCI_QTD_GET_TOGGLE(x) (((x) >> 31) & 0x1)
! 316: #define EHCI_QTD_SET_TOGGLE(x) ((x) << 31)
! 317: #define EHCI_QTD_TOGGLE_MASK 0x80000000
! 318: ehci_physaddr_t qtd_buffer[EHCI_QTD_NBUFFERS];
! 319: ehci_physaddr_t qtd_buffer_hi[EHCI_QTD_NBUFFERS];
! 320: } ehci_qtd_t;
! 321: #define EHCI_QTD_ALIGN 32
! 322:
! 323: /* Queue Head */
! 324: typedef struct {
! 325: ehci_link_t qh_link;
! 326: u_int32_t qh_endp;
! 327: #define EHCI_QH_GET_ADDR(x) (((x) >> 0) & 0x7f) /* endpoint addr */
! 328: #define EHCI_QH_SET_ADDR(x) (x)
! 329: #define EHCI_QH_ADDRMASK 0x0000007f
! 330: #define EHCI_QH_GET_INACT(x) (((x) >> 7) & 0x01) /* inactivate on next */
! 331: #define EHCI_QH_INACT 0x00000080
! 332: #define EHCI_QH_GET_ENDPT(x) (((x) >> 8) & 0x0f) /* endpoint no */
! 333: #define EHCI_QH_SET_ENDPT(x) ((x) << 8)
! 334: #define EHCI_QH_GET_EPS(x) (((x) >> 12) & 0x03) /* endpoint speed */
! 335: #define EHCI_QH_SET_EPS(x) ((x) << 12)
! 336: #define EHCI_QH_SPEED_FULL 0x0
! 337: #define EHCI_QH_SPEED_LOW 0x1
! 338: #define EHCI_QH_SPEED_HIGH 0x2
! 339: #define EHCI_QH_GET_DTC(x) (((x) >> 14) & 0x01) /* data toggle control */
! 340: #define EHCI_QH_DTC 0x00004000
! 341: #define EHCI_QH_GET_HRECL(x) (((x) >> 15) & 0x01) /* head of reclamation */
! 342: #define EHCI_QH_HRECL 0x00008000
! 343: #define EHCI_QH_GET_MPL(x) (((x) >> 16) & 0x7ff) /* max packet len */
! 344: #define EHCI_QH_SET_MPL(x) ((x) << 16)
! 345: #define EHCI_QH_MPLMASK 0x07ff0000
! 346: #define EHCI_QH_GET_CTL(x) (((x) >> 27) & 0x01) /* control endpoint */
! 347: #define EHCI_QH_CTL 0x08000000
! 348: #define EHCI_QH_GET_NRL(x) (((x) >> 28) & 0x0f) /* NAK reload */
! 349: #define EHCI_QH_SET_NRL(x) ((x) << 28)
! 350: u_int32_t qh_endphub;
! 351: #define EHCI_QH_GET_SMASK(x) (((x) >> 0) & 0xff) /* intr sched mask */
! 352: #define EHCI_QH_SET_SMASK(x) ((x) << 0)
! 353: #define EHCI_QH_GET_CMASK(x) (((x) >> 8) & 0xff) /* split completion mask */
! 354: #define EHCI_QH_SET_CMASK(x) ((x) << 8)
! 355: #define EHCI_QH_GET_HUBA(x) (((x) >> 16) & 0x7f) /* hub address */
! 356: #define EHCI_QH_SET_HUBA(x) ((x) << 16)
! 357: #define EHCI_QH_GET_PORT(x) (((x) >> 23) & 0x7f) /* hub port */
! 358: #define EHCI_QH_SET_PORT(x) ((x) << 23)
! 359: #define EHCI_QH_GET_MULT(x) (((x) >> 30) & 0x03) /* pipe multiplier */
! 360: #define EHCI_QH_SET_MULT(x) ((x) << 30)
! 361: ehci_link_t qh_curqtd;
! 362: ehci_qtd_t qh_qtd;
! 363: } ehci_qh_t;
! 364: #define EHCI_QH_ALIGN 32
! 365:
! 366: /* Periodic Frame Span Traversal Node */
! 367: typedef struct {
! 368: ehci_link_t fstn_link;
! 369: ehci_link_t fstn_back;
! 370: } ehci_fstn_t;
! 371: #define EHCI_FSTN_ALIGN 32
! 372:
! 373: #endif /* _DEV_PCI_EHCIREG_H_ */
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