Annotation of sys/dev/sdmmc/sdhcreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: sdhcreg.h,v 1.4 2006/07/30 17:20:40 fgsch Exp $ */
2:
3: /*
4: * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
5: *
6: * Permission to use, copy, modify, and distribute this software for any
7: * purpose with or without fee is hereby granted, provided that the above
8: * copyright notice and this permission notice appear in all copies.
9: *
10: * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11: * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12: * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13: * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14: * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15: * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16: * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17: */
18:
19: #ifndef _SDHCREG_H_
20: #define _SDHCREG_H_
21:
22: /* PCI base address registers */
23: #define SDHC_PCI_BAR_START PCI_MAPREG_START
24: #define SDHC_PCI_BAR_END PCI_MAPREG_END
25:
26: /* PCI interface classes */
27: #define SDHC_PCI_INTERFACE_NO_DMA 0x00
28: #define SDHC_PCI_INTERFACE_DMA 0x01
29: #define SDHC_PCI_INTERFACE_VENDOR 0x02
30:
31: /* Host standard register set */
32: #define SDHC_DMA_ADDR 0x00
33: #define SDHC_BLOCK_SIZE 0x04
34: #define SDHC_BLOCK_COUNT 0x06
35: #define SDHC_BLOCK_COUNT_MAX 512
36: #define SDHC_ARGUMENT 0x08
37: #define SDHC_TRANSFER_MODE 0x0c
38: #define SDHC_MULTI_BLOCK_MODE (1<<5)
39: #define SDHC_READ_MODE (1<<4)
40: #define SDHC_AUTO_CMD12_ENABLE (1<<2)
41: #define SDHC_BLOCK_COUNT_ENABLE (1<<1)
42: #define SDHC_DMA_ENABLE (1<<0)
43: #define SDHC_COMMAND 0x0e
44: /* 14-15 reserved */
45: #define SDHC_COMMAND_INDEX_SHIFT 8
46: #define SDHC_COMMAND_INDEX_MASK 0x3f
47: #define SDHC_COMMAND_TYPE_ABORT (3<<6)
48: #define SDHC_COMMAND_TYPE_RESUME (2<<6)
49: #define SDHC_COMMAND_TYPE_SUSPEND (1<<6)
50: #define SDHC_COMMAND_TYPE_NORMAL (0<<6)
51: #define SDHC_DATA_PRESENT_SELECT (1<<5)
52: #define SDHC_INDEX_CHECK_ENABLE (1<<4)
53: #define SDHC_CRC_CHECK_ENABLE (1<<3)
54: /* 2 reserved */
55: #define SDHC_RESP_LEN_48_CHK_BUSY (3<<0)
56: #define SDHC_RESP_LEN_48 (2<<0)
57: #define SDHC_RESP_LEN_136 (1<<0)
58: #define SDHC_NO_RESPONSE (0<<0)
59: #define SDHC_RESPONSE 0x10 /* - 0x1f */
60: #define SDHC_DATA 0x20
61: #define SDHC_PRESENT_STATE 0x24
62: /* 25-31 reserved */
63: #define SDHC_CMD_LINE_SIGNAL_LEVEL (1<<24)
64: #define SDHC_DAT3_LINE_LEVEL (1<<23)
65: #define SDHC_DAT2_LINE_LEVEL (1<<22)
66: #define SDHC_DAT1_LINE_LEVEL (1<<21)
67: #define SDHC_DAT0_LINE_LEVEL (1<<20)
68: #define SDHC_WRITE_PROTECT_SWITCH (1<<19)
69: #define SDHC_CARD_DETECT_PIN_LEVEL (1<<18)
70: #define SDHC_CARD_STATE_STABLE (1<<17)
71: #define SDHC_CARD_INSERTED (1<<16)
72: /* 12-15 reserved */
73: #define SDHC_BUFFER_READ_ENABLE (1<<11)
74: #define SDHC_BUFFER_WRITE_ENABLE (1<<10)
75: #define SDHC_READ_TRANSFER_ACTIVE (1<<9)
76: #define SDHC_WRITE_TRANSFER_ACTIVE (1<<8)
77: /* 3-7 reserved */
78: #define SDHC_DAT_ACTIVE (1<<2)
79: #define SDHC_CMD_INHIBIT_DAT (1<<1)
80: #define SDHC_CMD_INHIBIT_CMD (1<<0)
81: #define SDHC_CMD_INHIBIT_MASK 0x0003
82: #define SDHC_HOST_CTL 0x28
83: #define SDHC_HIGH_SPEED (1<<2)
84: #define SDHC_4BIT_MODE (1<<1)
85: #define SDHC_LED_ON (1<<0)
86: #define SDHC_POWER_CTL 0x29
87: #define SDHC_VOLTAGE_SHIFT 1
88: #define SDHC_VOLTAGE_MASK 0x07
89: #define SDHC_VOLTAGE_3_3V 0x07
90: #define SDHC_VOLTAGE_3_0V 0x06
91: #define SDHC_VOLTAGE_1_8V 0x05
92: #define SDHC_BUS_POWER (1<<0)
93: #define SDHC_BLOCK_GAP_CTL 0x2a
94: #define SDHC_WAKEUP_CTL 0x2b
95: #define SDHC_CLOCK_CTL 0x2c
96: #define SDHC_SDCLK_DIV_SHIFT 8
97: #define SDHC_SDCLK_DIV_MASK 0xff
98: #define SDHC_SDCLK_ENABLE (1<<2)
99: #define SDHC_INTCLK_STABLE (1<<1)
100: #define SDHC_INTCLK_ENABLE (1<<0)
101: #define SDHC_TIMEOUT_CTL 0x2e
102: #define SDHC_TIMEOUT_MAX 0x0e
103: #define SDHC_SOFTWARE_RESET 0x2f
104: #define SDHC_RESET_MASK 0x5
105: #define SDHC_RESET_DAT (1<<2)
106: #define SDHC_RESET_CMD (1<<1)
107: #define SDHC_RESET_ALL (1<<0)
108: #define SDHC_NINTR_STATUS 0x30
109: #define SDHC_ERROR_INTERRUPT (1<<15)
110: #define SDHC_CARD_INTERRUPT (1<<8)
111: #define SDHC_CARD_REMOVAL (1<<7)
112: #define SDHC_CARD_INSERTION (1<<6)
113: #define SDHC_BUFFER_READ_READY (1<<5)
114: #define SDHC_BUFFER_WRITE_READY (1<<4)
115: #define SDHC_DMA_INTERRUPT (1<<3)
116: #define SDHC_BLOCK_GAP_EVENT (1<<2)
117: #define SDHC_TRANSFER_COMPLETE (1<<1)
118: #define SDHC_COMMAND_COMPLETE (1<<0)
119: #define SDHC_NINTR_STATUS_MASK 0x81ff
120: #define SDHC_EINTR_STATUS 0x32
121: #define SDHC_AUTO_CMD12_ERROR (1<<8)
122: #define SDHC_CURRENT_LIMIT_ERROR (1<<7)
123: #define SDHC_DATA_END_BIT_ERROR (1<<6)
124: #define SDHC_DATA_CRC_ERROR (1<<5)
125: #define SDHC_DATA_TIMEOUT_ERROR (1<<4)
126: #define SDHC_CMD_INDEX_ERROR (1<<3)
127: #define SDHC_CMD_END_BIT_ERROR (1<<2)
128: #define SDHC_CMD_CRC_ERROR (1<<1)
129: #define SDHC_CMD_TIMEOUT_ERROR (1<<0)
130: #define SDHC_EINTR_STATUS_MASK 0x01ff /* excluding vendor signals */
131: #define SDHC_NINTR_STATUS_EN 0x34
132: #define SDHC_EINTR_STATUS_EN 0x36
133: #define SDHC_NINTR_SIGNAL_EN 0x38
134: #define SDHC_NINTR_SIGNAL_MASK 0x01ff
135: #define SDHC_EINTR_SIGNAL_EN 0x3a
136: #define SDHC_EINTR_SIGNAL_MASK 0x01ff /* excluding vendor signals */
137: #define SDHC_CMD12_ERROR_STATUS 0x3c
138: #define SDHC_CAPABILITIES 0x40
139: #define SDHC_VOLTAGE_SUPP_1_8V (1<<26)
140: #define SDHC_VOLTAGE_SUPP_3_0V (1<<25)
141: #define SDHC_VOLTAGE_SUPP_3_3V (1<<24)
142: #define SDHC_DMA_SUPPORT (1<<22)
143: #define SDHC_HIGH_SPEED_SUPP (1<<21)
144: #define SDHC_MAX_BLK_LEN_512 0
145: #define SDHC_MAX_BLK_LEN_1024 1
146: #define SDHC_MAX_BLK_LEN_2048 2
147: #define SDHC_MAX_BLK_LEN_SHIFT 16
148: #define SDHC_MAX_BLK_LEN_MASK 0x3
149: #define SDHC_BASE_FREQ_SHIFT 8
150: #define SDHC_BASE_FREQ_MASK 0x3f
151: #define SDHC_TIMEOUT_FREQ_UNIT (1<<7) /* 0=KHz, 1=MHz */
152: #define SDHC_TIMEOUT_FREQ_SHIFT 0
153: #define SDHC_TIMEOUT_FREQ_MASK 0x1f
154: #define SDHC_MAX_CAPABILITIES 0x48
155: #define SDHC_SLOT_INTR_STATUS 0xfc
156: #define SDHC_HOST_CTL_VERSION 0xfe
157: #define SDHC_SPEC_VERS_SHIFT 0
158: #define SDHC_SPEC_VERS_MASK 0xff
159: #define SDHC_VENDOR_VERS_SHIFT 8
160: #define SDHC_VENDOR_VERS_MASK 0xff
161:
162: /* SDHC_CAPABILITIES decoding */
163: #define SDHC_BASE_FREQ_KHZ(cap) \
164: ((((cap) >> SDHC_BASE_FREQ_SHIFT) & SDHC_BASE_FREQ_MASK) * 1000)
165: #define SDHC_TIMEOUT_FREQ(cap) \
166: (((cap) >> SDHC_TIMEOUT_FREQ_SHIFT) & SDHC_TIMEOUT_FREQ_MASK)
167: #define SDHC_TIMEOUT_FREQ_KHZ(cap) \
168: (((cap) & SDHC_TIMEOUT_FREQ_UNIT) ? \
169: SDHC_TIMEOUT_FREQ(cap) * 1000: \
170: SDHC_TIMEOUT_FREQ(cap))
171:
172: /* SDHC_HOST_CTL_VERSION decoding */
173: #define SDHC_SPEC_VERSION(hcv) \
174: (((hcv) >> SDHC_SPEC_VERS_SHIFT) & SDHC_SPEC_VERS_MASK)
175: #define SDHC_VENDOR_VERSION(hcv) \
176: (((hcv) >> SDHC_VENDOR_VERS_SHIFT) & SDHC_VENDOR_VERS_MASK)
177:
178: #define SDHC_PRESENT_STATE_BITS \
179: "\20\31CL\30D3L\27D2L\26D1L\25D0L\24WPS\23CD\22CSS\21CI" \
180: "\14BRE\13BWE\12RTA\11WTA\3DLA\2CID\1CIC"
181: #define SDHC_NINTR_STATUS_BITS \
182: "\20\20ERROR\11CARD\10REMOVAL\7INSERTION\6READ\5WRITE" \
183: "\4DMA\3GAP\2XFER\1CMD"
184: #define SDHC_EINTR_STATUS_BITS \
185: "\20\11ACMD12\10CL\7DEB\6DCRC\5DT\4CI\3CEB\2CCRC\1CT"
186: #define SDHC_CAPABILITIES_BITS \
187: "\20\33Vdd1.8V\32Vdd3.0V\31Vdd3.3V\30SUSPEND\27DMA\26HIGHSPEED"
188:
189: #endif
CVSweb
![[BACK]](/icons/back.gif){kind=icon}
Return to sdhcreg.h CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / dev / sdmmc