Annotation of sys/dev/sbus/qereg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: qereg.h,v 1.3 2006/05/29 20:40:03 miod Exp $ */
! 2: /* $NetBSD: qereg.h,v 1.3 2000/07/24 04:28:51 mycroft Exp $ */
! 3:
! 4: /*-
! 5: * Copyright (c) 1999 The NetBSD Foundation, Inc.
! 6: * All rights reserved.
! 7: *
! 8: * This code is derived from software contributed to The NetBSD Foundation
! 9: * by Paul Kranenburg.
! 10: *
! 11: * Redistribution and use in source and binary forms, with or without
! 12: * modification, are permitted provided that the following conditions
! 13: * are met:
! 14: * 1. Redistributions of source code must retain the above copyright
! 15: * notice, this list of conditions and the following disclaimer.
! 16: * 2. Redistributions in binary form must reproduce the above copyright
! 17: * notice, this list of conditions and the following disclaimer in the
! 18: * documentation and/or other materials provided with the distribution.
! 19: * 3. All advertising materials mentioning features or use of this software
! 20: * must display the following acknowledgement:
! 21: * This product includes software developed by the NetBSD
! 22: * Foundation, Inc. and its contributors.
! 23: * 4. Neither the name of The NetBSD Foundation nor the names of its
! 24: * contributors may be used to endorse or promote products derived
! 25: * from this software without specific prior written permission.
! 26: *
! 27: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
! 28: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
! 29: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
! 30: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
! 31: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
! 32: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
! 33: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
! 34: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
! 35: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
! 36: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 37: * POSSIBILITY OF SUCH DAMAGE.
! 38: */
! 39:
! 40: /*
! 41: * Copyright (c) 1998 Jason L. Wright.
! 42: * All rights reserved.
! 43: *
! 44: * Redistribution and use in source and binary forms, with or without
! 45: * modification, are permitted provided that the following conditions
! 46: * are met:
! 47: * 1. Redistributions of source code must retain the above copyright
! 48: * notice, this list of conditions and the following disclaimer.
! 49: * 2. Redistributions in binary form must reproduce the above copyright
! 50: * notice, this list of conditions and the following disclaimer in the
! 51: * documentation and/or other materials provided with the distribution.
! 52: *
! 53: * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
! 54: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
! 55: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
! 56: * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
! 57: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
! 58: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
! 59: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
! 60: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
! 61: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
! 62: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
! 63: */
! 64:
! 65: /*
! 66: * QE Channel registers
! 67: */
! 68: #if 0
! 69: struct qe_cregs {
! 70: u_int32_t ctrl; /* control */
! 71: u_int32_t stat; /* status */
! 72: u_int32_t rxds; /* rx descriptor ring ptr */
! 73: u_int32_t txds; /* tx descriptor ring ptr */
! 74: u_int32_t rimask; /* rx interrupt mask */
! 75: u_int32_t timask; /* tx interrupt mask */
! 76: u_int32_t qmask; /* qec error interrupt mask */
! 77: u_int32_t mmask; /* mace error interrupt mask */
! 78: u_int32_t rxwbufptr; /* local memory rx write ptr */
! 79: u_int32_t rxrbufptr; /* local memory rx read ptr */
! 80: u_int32_t txwbufptr; /* local memory tx write ptr */
! 81: u_int32_t txrbufptr; /* local memory tx read ptr */
! 82: u_int32_t ccnt; /* collision counter */
! 83: u_int32_t pipg; /* inter-frame gap */
! 84: };
! 85: #endif
! 86: /* register indices: */
! 87: #define QE_CRI_CTRL (0*4)
! 88: #define QE_CRI_STAT (1*4)
! 89: #define QE_CRI_RXDS (2*4)
! 90: #define QE_CRI_TXDS (3*4)
! 91: #define QE_CRI_RIMASK (4*4)
! 92: #define QE_CRI_TIMASK (5*4)
! 93: #define QE_CRI_QMASK (6*4)
! 94: #define QE_CRI_MMASK (7*4)
! 95: #define QE_CRI_RXWBUF (8*4)
! 96: #define QE_CRI_RXRBUF (9*4)
! 97: #define QE_CRI_TXWBUF (10*4)
! 98: #define QE_CRI_TXRBUF (11*4)
! 99: #define QE_CRI_CCNT (12*4)
! 100: #define QE_CRI_PIPG (13*4)
! 101:
! 102: /* qe_cregs.ctrl: control. */
! 103: #define QE_CR_CTRL_RXOFF 0x00000004 /* disable receiver */
! 104: #define QE_CR_CTRL_RESET 0x00000002 /* reset this channel */
! 105: #define QE_CR_CTRL_TWAKEUP 0x00000001 /* tx dma wakeup */
! 106:
! 107: /* qe_cregs.stat: status. */
! 108: #define QE_CR_STAT_EDEFER 0x10000000 /* excessive defers */
! 109: #define QE_CR_STAT_CLOSS 0x08000000 /* loss of carrier */
! 110: #define QE_CR_STAT_ERETRIES 0x04000000 /* >16 retries */
! 111: #define QE_CR_STAT_LCOLL 0x02000000 /* late tx collision */
! 112: #define QE_CR_STAT_FUFLOW 0x01000000 /* fifo underflow */
! 113: #define QE_CR_STAT_JERROR 0x00800000 /* jabber error */
! 114: #define QE_CR_STAT_BERROR 0x00400000 /* babble error */
! 115: #define QE_CR_STAT_TXIRQ 0x00200000 /* tx interrupt */
! 116: #define QE_CR_STAT_TCCOFLOW 0x00100000 /* tx collision cntr expired */
! 117: #define QE_CR_STAT_TXDERROR 0x00080000 /* tx descriptor is bad */
! 118: #define QE_CR_STAT_TXLERR 0x00040000 /* tx late error */
! 119: #define QE_CR_STAT_TXPERR 0x00020000 /* tx parity error */
! 120: #define QE_CR_STAT_TXSERR 0x00010000 /* tx sbus error ack */
! 121: #define QE_CR_STAT_RCCOFLOW 0x00001000 /* rx collision cntr expired */
! 122: #define QE_CR_STAT_RUOFLOW 0x00000800 /* rx runt counter expired */
! 123: #define QE_CR_STAT_MCOFLOW 0x00000400 /* rx missed counter expired */
! 124: #define QE_CR_STAT_RXFOFLOW 0x00000200 /* rx fifo over flow */
! 125: #define QE_CR_STAT_RLCOLL 0x00000100 /* rx late collision */
! 126: #define QE_CR_STAT_FCOFLOW 0x00000080 /* rx frame counter expired */
! 127: #define QE_CR_STAT_CECOFLOW 0x00000040 /* rx crc error cntr expired */
! 128: #define QE_CR_STAT_RXIRQ 0x00000020 /* rx interrupt */
! 129: #define QE_CR_STAT_RXDROP 0x00000010 /* rx dropped packet */
! 130: #define QE_CR_STAT_RXSMALL 0x00000008 /* rx buffer too small */
! 131: #define QE_CR_STAT_RXLERR 0x00000004 /* rx late error */
! 132: #define QE_CR_STAT_RXPERR 0x00000002 /* rx parity error */
! 133: #define QE_CR_STAT_RXSERR 0x00000001 /* rx sbus error ack */
! 134: #define QE_CR_STAT_BITS "\020" \
! 135: "\01RXSERR\02RXPERR\03RXLERR" \
! 136: "\04RXSMALL\05RXDROP\06RXIRQ" \
! 137: "\07CECOFLOW\010FCOFLOW\011RLCOLL" \
! 138: "\012RXFOFLOW\013MCOFLOW\014RUOFLOW" \
! 139: "\015RCCOFLOW\021TXSERR\022TXPERR" \
! 140: "\023TXLERR\024TXDERROR\025TCCOFLOW" \
! 141: "\026TXIRQ\027BERROR\030JERROR" \
! 142: "\031FUFLOW\032LCOLL\033ERETRIES" \
! 143: "\034CLOSS\035EDEFER"
! 144:
! 145: /*
! 146: * Errors: all status bits except for TX/RX IRQ
! 147: */
! 148: #define QE_CR_STAT_ALLERRORS \
! 149: ( QE_CR_STAT_EDEFER | QE_CR_STAT_CLOSS | QE_CR_STAT_ERETRIES \
! 150: | QE_CR_STAT_LCOLL | QE_CR_STAT_FUFLOW | QE_CR_STAT_JERROR \
! 151: | QE_CR_STAT_BERROR | QE_CR_STAT_TCCOFLOW | QE_CR_STAT_TXDERROR \
! 152: | QE_CR_STAT_TXLERR | QE_CR_STAT_TXPERR | QE_CR_STAT_TXSERR \
! 153: | QE_CR_STAT_RCCOFLOW | QE_CR_STAT_RUOFLOW | QE_CR_STAT_MCOFLOW \
! 154: | QE_CR_STAT_RXFOFLOW | QE_CR_STAT_RLCOLL | QE_CR_STAT_FCOFLOW \
! 155: | QE_CR_STAT_CECOFLOW | QE_CR_STAT_RXDROP | QE_CR_STAT_RXSMALL \
! 156: | QE_CR_STAT_RXLERR | QE_CR_STAT_RXPERR | QE_CR_STAT_RXSERR)
! 157:
! 158: /* qe_cregs.qmask: qec error interrupt mask. */
! 159: #define QE_CR_QMASK_COFLOW 0x00100000 /* collision cntr overflow */
! 160: #define QE_CR_QMASK_TXDERROR 0x00080000 /* tx descriptor error */
! 161: #define QE_CR_QMASK_TXLERR 0x00040000 /* tx late error */
! 162: #define QE_CR_QMASK_TXPERR 0x00020000 /* tx parity error */
! 163: #define QE_CR_QMASK_TXSERR 0x00010000 /* tx sbus error ack */
! 164: #define QE_CR_QMASK_RXDROP 0x00000010 /* rx packet dropped */
! 165: #define QE_CR_QMASK_RXSMALL 0x00000008 /* rx buffer too small */
! 166: #define QE_CR_QMASK_RXLERR 0x00000004 /* rx late error */
! 167: #define QE_CR_QMASK_RXPERR 0x00000002 /* rx parity error */
! 168: #define QE_CR_QMASK_RXSERR 0x00000001 /* rx sbus error ack */
! 169:
! 170: /* qe_cregs.mmask: MACE error interrupt mask. */
! 171: #define QE_CR_MMASK_EDEFER 0x10000000 /* excess defer */
! 172: #define QE_CR_MMASK_CLOSS 0x08000000 /* carrier loss */
! 173: #define QE_CR_MMASK_ERETRY 0x04000000 /* excess retry */
! 174: #define QE_CR_MMASK_LCOLL 0x02000000 /* late collision error */
! 175: #define QE_CR_MMASK_UFLOW 0x01000000 /* underflow */
! 176: #define QE_CR_MMASK_JABBER 0x00800000 /* jabber error */
! 177: #define QE_CR_MMASK_BABBLE 0x00400000 /* babble error */
! 178: #define QE_CR_MMASK_OFLOW 0x00000800 /* overflow */
! 179: #define QE_CR_MMASK_RXCOLL 0x00000400 /* rx coll-cntr overflow */
! 180: #define QE_CR_MMASK_RPKT 0x00000200 /* runt pkt overflow */
! 181: #define QE_CR_MMASK_MPKT 0x00000100 /* missed pkt overflow */
! 182:
! 183: /* qe_cregs.pipg: inter-frame gap. */
! 184: #define QE_CR_PIPG_TENAB 0x00000020 /* enable throttle */
! 185: #define QE_CR_PIPG_MMODE 0x00000010 /* manual mode */
! 186: #define QE_CR_PIPG_WMASK 0x0000000f /* sbus wait mask */
! 187:
! 188: /*
! 189: * MACE registers
! 190: */
! 191: #if 0
! 192: struct qe_mregs {
! 193: u_int8_t rcvfifo; [0] /* receive fifo */
! 194: u_int8_t xmtfifo; [1] /* transmit fifo */
! 195: u_int8_t xmtfc; [2] /* transmit frame control */
! 196: u_int8_t xmtfs; [3] /* transmit frame status */
! 197: u_int8_t xmtrc; [4] /* tx retry count */
! 198: u_int8_t rcvfc; [5] /* receive frame control */
! 199: u_int8_t rcvfs; [6] /* receive frame status */
! 200: u_int8_t fifofc; [7] /* fifo frame count */
! 201: u_int8_t ir; [8] /* interrupt register */
! 202: u_int8_t imr; [9] /* interrupt mask register */
! 203: u_int8_t pr; [10] /* poll register */
! 204: u_int8_t biucc; [11] /* biu config control */
! 205: u_int8_t fifocc; [12] /* fifo config control */
! 206: u_int8_t maccc; [13] /* mac config control */
! 207: u_int8_t plscc; [14] /* pls config control */
! 208: u_int8_t phycc; [15] /* phy config control */
! 209: u_int8_t chipid1; [16] /* chipid, low byte */
! 210: u_int8_t chipid2; [17] /* chipid, high byte */
! 211: u_int8_t iac; [18] /* internal address config */
! 212: u_int8_t _reserved0; [19] /* reserved */
! 213: u_int8_t ladrf; [20] /* logical address filter */
! 214: u_int8_t padr; [21] /* physical address */
! 215: u_int8_t _reserved1; [22] /* reserved */
! 216: u_int8_t _reserved2; [23] /* reserved */
! 217: u_int8_t mpc; [24] /* missed packet count */
! 218: u_int8_t _reserved3; [25] /* reserved */
! 219: u_int8_t rntpc; [26] /* runt packet count */
! 220: u_int8_t rcvcc; [27] /* receive collision count */
! 221: u_int8_t _reserved4; [28] /* reserved */
! 222: u_int8_t utr; [29] /* user test register */
! 223: u_int8_t rtr1; [30] /* reserved test register 1 */
! 224: u_int8_t rtr2; [31] /* reserved test register 2 */
! 225: };
! 226: #endif
! 227: /* register indices: */
! 228: #define QE_MRI_RCVFIFO 0 /* receive fifo */
! 229: #define QE_MRI_XMTFIFO 1 /* transmit fifo */
! 230: #define QE_MRI_XMTFC 2 /* transmit frame control */
! 231: #define QE_MRI_XMTFS 3 /* transmit frame status */
! 232: #define QE_MRI_XMTRC 4 /* tx retry count */
! 233: #define QE_MRI_RCVFC 5 /* receive frame control */
! 234: #define QE_MRI_RCVFS 6 /* receive frame status */
! 235: #define QE_MRI_FIFOFC 7 /* fifo frame count */
! 236: #define QE_MRI_IR 8 /* interrupt register */
! 237: #define QE_MRI_IMR 9 /* interrupt mask register */
! 238: #define QE_MRI_PR 10 /* poll register */
! 239: #define QE_MRI_BIUCC 11 /* biu config control */
! 240: #define QE_MRI_FIFOCC 12 /* fifo config control */
! 241: #define QE_MRI_MACCC 13 /* mac config control */
! 242: #define QE_MRI_PLSCC 14 /* pls config control */
! 243: #define QE_MRI_PHYCC 15 /* phy config control */
! 244: #define QE_MRI_CHIPID1 16 /* chipid, low byte */
! 245: #define QE_MRI_CHIPID2 17 /* chipid, high byte */
! 246: #define QE_MRI_IAC 18 /* internal address config */
! 247: #define QE_MRI_LADRF 20 /* logical address filter */
! 248: #define QE_MRI_PADR 21 /* physical address */
! 249: #define QE_MRI_MPC 24 /* missed packet count */
! 250: #define QE_MRI_RNTPC 26 /* runt packet count */
! 251: #define QE_MRI_RCVCC 27 /* receive collision count */
! 252: #define QE_MRI_UTR 29 /* user test register */
! 253: #define QE_MRI_RTR1 30 /* reserved test register 1 */
! 254: #define QE_MRI_RTR2 31 /* reserved test register 2 */
! 255:
! 256: /* qe_mregs.xmtfc: transmit frame control. */
! 257: #define QE_MR_XMTFC_DRETRY 0x80 /* disable retries */
! 258: #define QE_MR_XMTFC_DXMTFCS 0x08 /* disable tx fcs */
! 259: #define QE_MR_XMTFC_APADXMT 0x01 /* enable auto padding */
! 260:
! 261: /* qe_mregs.xmtfs: transmit frame status. */
! 262: #define QE_MR_XMTFS_XMTSV 0x80 /* tx valid */
! 263: #define QE_MR_XMTFS_UFLO 0x40 /* tx underflow */
! 264: #define QE_MR_XMTFS_LCOL 0x20 /* tx late collision */
! 265: #define QE_MR_XMTFS_MORE 0x10 /* tx > 1 retries */
! 266: #define QE_MR_XMTFS_ONE 0x08 /* tx 1 retry */
! 267: #define QE_MR_XMTFS_DEFER 0x04 /* tx pkt deferred */
! 268: #define QE_MR_XMTFS_LCAR 0x02 /* tx carrier lost */
! 269: #define QE_MR_XMTFS_RTRY 0x01 /* tx retry error */
! 270:
! 271: /* qe_mregs.xmtrc: transmit retry count. */
! 272: #define QE_MR_XMTRC_EXDEF 0x80 /* tx excess defers */
! 273: #define QE_MR_XMTRC_XMTRC 0x0f /* tx retry count mask */
! 274:
! 275: /* qe_mregs.rcvfc: receive frame control. */
! 276: #define QE_MR_RCVFC_LLRCV 0x08 /* rx low latency */
! 277: #define QE_MR_RCVFC_MR 0x04 /* rx addr match/reject */
! 278: #define QE_MR_RCVFC_ASTRPRCV 0x01 /* rx auto strip */
! 279:
! 280: /* qe_mregs.rcvfs: receive frame status. */
! 281: #define QE_MR_RCVFS_OFLO 0x80 /* rx overflow */
! 282: #define QE_MR_RCVFS_CLSN 0x40 /* rx late collision */
! 283: #define QE_MR_RCVFS_FRAM 0x20 /* rx framing error */
! 284: #define QE_MR_RCVFS_FCS 0x10 /* rx fcs error */
! 285: #define QE_MR_RCVFS_RCVCNT 0x0f /* rx msg byte count mask */
! 286:
! 287: /* qe_mregs.fifofc: fifo frame count. */
! 288: #define QE_MR_FIFOFC_RCVFC 0xf0 /* rx fifo frame count */
! 289: #define QE_MR_FIFOFC_XMTFC 0x0f /* tx fifo frame count */
! 290:
! 291: /* qe_mregs.ir: interrupt register. */
! 292: #define QE_MR_IR_JAB 0x80 /* jabber error */
! 293: #define QE_MR_IR_BABL 0x40 /* babble error */
! 294: #define QE_MR_IR_CERR 0x20 /* collision error */
! 295: #define QE_MR_IR_RCVCCO 0x10 /* collision cnt overflow */
! 296: #define QE_MR_IR_RNTPCO 0x08 /* runt pkt cnt overflow */
! 297: #define QE_MR_IR_MPCO 0x04 /* miss pkt cnt overflow */
! 298: #define QE_MR_IR_RCVINT 0x02 /* packet received */
! 299: #define QE_MR_IR_XMTINT 0x01 /* packet transmitted */
! 300:
! 301: /* qe_mregs.imr: interrupt mask register. */
! 302: #define QE_MR_IMR_JABM 0x80 /* jabber errors */
! 303: #define QE_MR_IMR_BABLM 0x40 /* babble errors */
! 304: #define QE_MR_IMR_CERRM 0x20 /* collision errors */
! 305: #define QE_MR_IMR_RCVCCOM 0x10 /* rx collision count oflow */
! 306: #define QE_MR_IMR_RNTPCOM 0x08 /* runt pkt cnt ovrflw */
! 307: #define QE_MR_IMR_MPCOM 0x04 /* miss pkt cnt ovrflw */
! 308: #define QE_MR_IMR_RCVINTM 0x02 /* rx interrupts */
! 309: #define QE_MR_IMR_XMTINTM 0x01 /* tx interrupts */
! 310:
! 311: /* qe_mregs.pr: poll register. */
! 312: #define QE_MR_PR_XMTSV 0x80 /* tx status is valid */
! 313: #define QE_MR_PR_TDTREQ 0x40 /* tx data xfer request */
! 314: #define QE_MR_PR_RDTREQ 0x20 /* rx data xfer request */
! 315:
! 316: /* qe_mregs.biucc: biu config control. */
! 317: #define QE_MR_BIUCC_BSWAP 0x40 /* byte swap */
! 318: #define QE_MR_BIUCC_4TS 0x00 /* 4byte xmit start point */
! 319: #define QE_MR_BIUCC_16TS 0x10 /* 16byte xmit start point */
! 320: #define QE_MR_BIUCC_64TS 0x20 /* 64byte xmit start point */
! 321: #define QE_MR_BIUCC_112TS 0x30 /* 112byte xmit start point */
! 322: #define QE_MR_BIUCC_SWRST 0x01 /* sw-reset mace */
! 323:
! 324: /* qe_mregs.fifocc: fifo config control. */
! 325: #define QE_MR_FIFOCC_TXF8 0x00 /* tx fifo 8 write cycles */
! 326: #define QE_MR_FIFOCC_TXF32 0x80 /* tx fifo 32 write cycles */
! 327: #define QE_MR_FIFOCC_TXF16 0x40 /* tx fifo 16 write cycles */
! 328: #define QE_MR_FIFOCC_RXF64 0x20 /* rx fifo 64 write cycles */
! 329: #define QE_MR_FIFOCC_RXF32 0x10 /* rx fifo 32 write cycles */
! 330: #define QE_MR_FIFOCC_RXF16 0x00 /* rx fifo 16 write cycles */
! 331: #define QE_MR_FIFOCC_TFWU 0x08 /* tx fifo watermark update */
! 332: #define QE_MR_FIFOCC_RFWU 0x04 /* rx fifo watermark update */
! 333: #define QE_MR_FIFOCC_XMTBRST 0x02 /* tx burst enable */
! 334: #define QE_MR_FIFOCC_RCVBRST 0x01 /* rx burst enable */
! 335:
! 336: /* qe_mregs.maccc: mac config control. */
! 337: #define QE_MR_MACCC_PROM 0x80 /* promiscuous mode enable */
! 338: #define QE_MR_MACCC_DXMT2PD 0x40 /* tx 2part deferral enable */
! 339: #define QE_MR_MACCC_EMBA 0x20 /* modified backoff enable */
! 340: #define QE_MR_MACCC_DRCVPA 0x08 /* rx physical addr disable */
! 341: #define QE_MR_MACCC_DRCVBC 0x04 /* rx broadcast disable */
! 342: #define QE_MR_MACCC_ENXMT 0x02 /* enable transmitter */
! 343: #define QE_MR_MACCC_ENRCV 0x01 /* enable receiver */
! 344:
! 345: /* qe_mregs.plscc: pls config control. */
! 346: #define QE_MR_PLSCC_XMTSEL 0x08 /* tx mode select */
! 347: #define QE_MR_PLSCC_PORTMASK 0x06 /* port selection bits */
! 348: #define QE_MR_PLSCC_GPSI 0x06 /* use gpsi connector */
! 349: #define QE_MR_PLSCC_DAI 0x04 /* use dai connector */
! 350: #define QE_MR_PLSCC_TP 0x02 /* use twistedpair connector */
! 351: #define QE_MR_PLSCC_AUI 0x00 /* use aui connector */
! 352: #define QE_MR_PLSCC_ENPLSIO 0x01 /* pls i/o enable */
! 353:
! 354: /* qe_mregs.phycc: phy config control. */
! 355: #define QE_MR_PHYCC_LNKFL 0x80 /* link fail */
! 356: #define QE_MR_PHYCC_DLNKTST 0x40 /* disable link test logic */
! 357: #define QE_MR_PHYCC_REVPOL 0x20 /* rx polarity */
! 358: #define QE_MR_PHYCC_DAPC 0x10 /* autopolaritycorrect disab */
! 359: #define QE_MR_PHYCC_LRT 0x08 /* select low threshold */
! 360: #define QE_MR_PHYCC_ASEL 0x04 /* connector port auto-sel */
! 361: #define QE_MR_PHYCC_RWAKE 0x02 /* remote wakeup */
! 362: #define QE_MR_PHYCC_AWAKE 0x01 /* auto wakeup */
! 363:
! 364: /* qe_mregs.iac: internal address config. */
! 365: #define QE_MR_IAC_ADDRCHG 0x80 /* start address change */
! 366: #define QE_MR_IAC_PHYADDR 0x04 /* physical address reset */
! 367: #define QE_MR_IAC_LOGADDR 0x02 /* logical address reset */
! 368:
! 369: /* qe_mregs.utr: user test register. */
! 370: #define QE_MR_UTR_RTRE 0x80 /* enable resv test register */
! 371: #define QE_MR_UTR_RTRD 0x40 /* disab resv test register */
! 372: #define QE_MR_UTR_RPA 0x20 /* accept runt packets */
! 373: #define QE_MR_UTR_FCOLL 0x10 /* force collision status */
! 374: #define QE_MR_UTR_RCVSFCSE 0x08 /* enable fcs on rx */
! 375: #define QE_MR_UTR_INTLOOPM 0x06 /* Internal loopback w/mandec */
! 376: #define QE_MR_UTR_INTLOOP 0x04 /* Internal loopback */
! 377: #define QE_MR_UTR_EXTLOOP 0x02 /* external loopback */
! 378: #define QE_MR_UTR_NOLOOP 0x00 /* no loopback */
! 379:
! 380: /* Buffer and Ring sizes: fixed ring size */
! 381: #define QE_TX_RING_MAXSIZE 256 /* maximum tx ring size */
! 382: #define QE_RX_RING_MAXSIZE 256 /* maximum rx ring size */
! 383: #define QE_TX_RING_SIZE 16
! 384: #define QE_RX_RING_SIZE 16
! 385: #define QE_PKT_BUF_SZ 2048
! 386:
! 387: #define MC_POLY_LE 0xedb88320 /* mcast crc, little endian */
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