Annotation of sys/dev/sbus/cgtwelvereg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: cgtwelvereg.h,v 1.2 2006/07/20 11:23:49 martin Exp $ */
! 2:
! 3: /*
! 4: * Copyright (c) 2002 Miodrag Vallat. All rights reserved.
! 5: *
! 6: * Redistribution and use in source and binary forms, with or without
! 7: * modification, are permitted provided that the following conditions
! 8: * are met:
! 9: * 1. Redistributions of source code must retain the above copyright
! 10: * notice, this list of conditions and the following disclaimer.
! 11: * 2. Redistributions in binary form must reproduce the above copyright
! 12: * notice, this list of conditions and the following disclaimer in the
! 13: * documentation and/or other materials provided with the distribution.
! 14: *
! 15: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 16: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
! 17: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
! 18: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
! 19: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
! 20: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
! 21: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 22: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
! 23: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
! 24: * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 25: * POSSIBILITY OF SUCH DAMAGE.
! 26: */
! 27:
! 28: /*
! 29: * cgtwelve (GS) accelerated 24-bit framebuffer driver.
! 30: *
! 31: * Memory layout and scarce register information from SMI's cg12reg.h
! 32: */
! 33:
! 34: #define CG12_HEIGHT 900
! 35: #define CG12_WIDTH 1152
! 36:
! 37: #define CG12_HEIGHT_HR 1024
! 38: #define CG12_WIDTH_HR 1280
! 39:
! 40: /* offsets from the card mapping */
! 41: #define CG12_OFF_DPU 0x040100
! 42: #define CG12_OFF_APU 0x040200
! 43: #define CG12_OFF_DAC 0x040300
! 44: #define CG12_OFF_OVERLAY0 0x700000
! 45: #define CG12_OFF_OVERLAY1 0x780000
! 46: #define CG12_OFF_INTEN 0xc00000
! 47:
! 48: #define CG12_OFF_OVERLAY0_HR 0xe00000
! 49: #define CG12_OFF_OVERLAY1_HR 0xf00000
! 50: #define CG12_OFF_INTEN_HR 0x800000
! 51:
! 52: /* sizes of various parts */
! 53: #define CG12_SIZE_DPU 0x000100
! 54: #define CG12_SIZE_APU 0x000100
! 55: #define CG12_SIZE_DAC 0x000400
! 56: #define CG12_SIZE_OVERLAY 0x020000
! 57: #define CG12_SIZE_ENABLE 0x020000
! 58: #define CG12_SIZE_COLOR8 0x100000
! 59: #define CG12_SIZE_COLOR24 0x400000
! 60:
! 61: #define CG12_SIZE_OVERLAY_HR 0x030000
! 62: #define CG12_SIZE_ENABLE_HR 0x030000
! 63: #define CG12_SIZE_COLOR8_HR 0x180000
! 64: #define CG12_SIZE_COLOR24_HR 0x600000
! 65:
! 66: /*
! 67: * The "direct port access" register constants.
! 68: * All HACCESS values include noHSTXY, noHCLIP, and SWAP.
! 69: */
! 70:
! 71: #define CG12_HPAGE_OVERLAY 0x00000700 /* overlay page */
! 72: #define CG12_HPAGE_OVERLAY_HR 0x00000e00
! 73: #define CG12_HACCESS_OVERLAY 0x00000020 /* 1bit/pixel */
! 74: #define CG12_PLN_SL_OVERLAY 0x00000017 /* plane 23 */
! 75: #define CG12_PLN_WR_OVERLAY 0x00800000 /* write mask */
! 76: #define CG12_PLN_RD_OVERLAY 0xffffffff /* read mask */
! 77:
! 78: #define CG12_HPAGE_ENABLE 0x00000700 /* overlay page */
! 79: #define CG12_HPAGE_ENABLE_HR 0x00000e00
! 80: #define CG12_HACCESS_ENABLE 0x00000020 /* 1bit/pixel */
! 81: #define CG12_PLN_SL_ENABLE 0x00000016 /* plane 22 */
! 82: #define CG12_PLN_WR_ENABLE 0x00400000
! 83: #define CG12_PLN_RD_ENABLE 0xffffffff
! 84:
! 85: #define CG12_HPAGE_24BIT 0x00000500 /* intensity page */
! 86: #define CG12_HPAGE_24BIT_HR 0x00000a00
! 87: #define CG12_HACCESS_24BIT 0x00000025 /* 32bits/pixel */
! 88: #define CG12_PLN_SL_24BIT 0x00000000 /* planes 0-31 */
! 89: #define CG12_PLN_WR_24BIT 0x00ffffff
! 90: #define CG12_PLN_RD_24BIT 0x00ffffff
! 91:
! 92: #define CG12_HPAGE_8BIT 0x00000500 /* intensity page */
! 93: #define CG12_HPAGE_8BIT_HR 0x00000a00
! 94: #define CG12_HACCESS_8BIT 0x00000023 /* 8bits/pixel */
! 95: #define CG12_PLN_SL_8BIT 0x00000000 /* planes 0-7 */
! 96: #define CG12_PLN_WR_8BIT 0x00ffffff
! 97: #define CG12_PLN_RD_8BIT 0x000000ff
! 98:
! 99: #define CG12_HPAGE_WID 0x00000700 /* overlay page */
! 100: #define CG12_HPAGE_WID_HR 0x00000e00
! 101: #define CG12_HACCESS_WID 0x00000023 /* 8bits/pixel */
! 102: #define CG12_PLN_SL_WID 0x00000010 /* planes 16-23 */
! 103: #define CG12_PLN_WR_WID 0x003f0000
! 104: #define CG12_PLN_RD_WID 0x003f0000
! 105:
! 106: #define CG12_HPAGE_ZBUF 0x00000000 /* depth page */
! 107: #define CG12_HPAGE_ZBUF_HR 0x00000000
! 108: #define CG12_HACCESS_ZBUF 0x00000024 /* 16bits/pixel */
! 109: #define CG12_PLN_SL_ZBUF 0x00000060
! 110: #define CG12_PLN_WR_ZBUF 0xffffffff
! 111: #define CG12_PLN_RD_ZBUF 0xffffffff
! 112:
! 113: /* Direct Port Unit */
! 114: struct cgtwelve_dpu {
! 115: u_int32_t r[8];
! 116: u_int32_t reload_ctl;
! 117: u_int32_t reload_stb;
! 118: u_int32_t alu_ctl;
! 119: u_int32_t blu_ctl;
! 120: u_int32_t control;
! 121: u_int32_t xleft;
! 122: u_int32_t shift0;
! 123: u_int32_t shift1;
! 124: u_int32_t zoom;
! 125: u_int32_t bsr;
! 126: u_int32_t color0;
! 127: u_int32_t color1;
! 128: u_int32_t compout;
! 129: u_int32_t pln_rd_msk_host;
! 130: u_int32_t pln_wr_msk_host;
! 131: u_int32_t pln_rd_msk_local;
! 132: u_int32_t pln_wr_msk_local;
! 133: u_int32_t scis_ctl;
! 134: u_int32_t csr;
! 135: u_int32_t pln_reg_sl;
! 136: u_int32_t pln_sl_host;
! 137: u_int32_t pln_sl_local0;
! 138: u_int32_t pln_sl_local1;
! 139: u_int32_t broadcast;
! 140: };
! 141:
! 142: /* APU */
! 143: struct cgtwelve_apu {
! 144: u_int32_t imsg0;
! 145: u_int32_t msg0;
! 146: u_int32_t imsg1;
! 147: u_int32_t msg1;
! 148: u_int32_t ien0;
! 149: u_int32_t ien1;
! 150: u_int32_t iclear;
! 151: u_int32_t istatus;
! 152: u_int32_t cfcnt;
! 153: u_int32_t cfwptr;
! 154: u_int32_t cfrptr;
! 155: u_int32_t cfilev0;
! 156: u_int32_t cfilev1;
! 157: u_int32_t rfcnt;
! 158: u_int32_t rfwptr;
! 159: u_int32_t rfrptr;
! 160: u_int32_t rfilev0;
! 161: u_int32_t rfilev1;
! 162: u_int32_t size;
! 163: u_int32_t res0;
! 164: u_int32_t res1;
! 165: u_int32_t res2;
! 166: u_int32_t haccess;
! 167: u_int32_t hpage;
! 168: u_int32_t laccess;
! 169: u_int32_t lpage;
! 170: u_int32_t maccess;
! 171: u_int32_t ppage;
! 172: u_int32_t dwg_ctl;
! 173: u_int32_t sam;
! 174: u_int32_t sgn;
! 175: u_int32_t length;
! 176: u_int32_t dwg[8];
! 177: u_int32_t reload_ctl;
! 178: u_int32_t reload_stb;
! 179: u_int32_t c_xleft;
! 180: u_int32_t c_ytop;
! 181: u_int32_t c_xright;
! 182: u_int32_t c_ybot;
! 183: u_int32_t f_xleft;
! 184: u_int32_t f_xright;
! 185: u_int32_t x_dst;
! 186: u_int32_t y_dst;
! 187: u_int32_t dst_ctl;
! 188: u_int32_t morigin;
! 189: u_int32_t vsg_ctl;
! 190: u_int32_t h_sync;
! 191: u_int32_t hblank;
! 192: u_int32_t v_sync;
! 193: u_int32_t vblank;
! 194: u_int32_t vdpyint;
! 195: u_int32_t vssyncs;
! 196: u_int32_t hdelays;
! 197: u_int32_t stdaddr;
! 198: u_int32_t hpitches;
! 199: u_int32_t zoom;
! 200: u_int32_t test;
! 201: };
! 202:
! 203: struct cgtwelve_dac
! 204: {
! 205: u_int32_t addr_lo;
! 206: u_int8_t pad1[0x100 - 4];
! 207: u_int32_t addr_hi;
! 208: u_int8_t pad2[0x100 - 4];
! 209: u_int32_t control;
! 210: u_int8_t pad3[0x100 - 4];
! 211: u_int32_t color;
! 212: u_int8_t pad4[0x100 - 4];
! 213: };
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