Annotation of sys/dev/sbus/bppreg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: bppreg.h,v 1.2 2007/05/31 17:23:14 sobrado Exp $ */
! 2: /* $NetBSD: bppreg.h,v 1.1 1998/09/21 21:20:48 pk Exp $ */
! 3:
! 4: /*-
! 5: * Copyright (c) 1998 The NetBSD Foundation, Inc.
! 6: * All rights reserved.
! 7: *
! 8: * This code is derived from software contributed to The NetBSD Foundation
! 9: * by Paul Kranenburg.
! 10: *
! 11: * Redistribution and use in source and binary forms, with or without
! 12: * modification, are permitted provided that the following conditions
! 13: * are met:
! 14: * 1. Redistributions of source code must retain the above copyright
! 15: * notice, this list of conditions and the following disclaimer.
! 16: * 2. Redistributions in binary form must reproduce the above copyright
! 17: * notice, this list of conditions and the following disclaimer in the
! 18: * documentation and/or other materials provided with the distribution.
! 19: * 3. All advertising materials mentioning features or use of this software
! 20: * must display the following acknowledgement:
! 21: * This product includes software developed by the NetBSD
! 22: * Foundation, Inc. and its contributors.
! 23: * 4. Neither the name of The NetBSD Foundation nor the names of its
! 24: * contributors may be used to endorse or promote products derived
! 25: * from this software without specific prior written permission.
! 26: *
! 27: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
! 28: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
! 29: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
! 30: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
! 31: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
! 32: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
! 33: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
! 34: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
! 35: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
! 36: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 37: * POSSIBILITY OF SUCH DAMAGE.
! 38: */
! 39:
! 40: /* Hardware Configuration Register */
! 41: #define BPP_HCR_DSS_MASK 0x003f /* Data before strobe */
! 42: #define BPP_HCR_DSS_SHFT 0 /* (in SBus clocks)*/
! 43: #define BPP_HCR_DSW_MASK 0x7f00 /* Data Strobe Width */
! 44: #define BPP_HCR_DSW_SHFT 8 /* (in SBus clocks)*/
! 45: #define BPP_HCR_TEST 0x8000 /* */
! 46:
! 47:
! 48: /* Operation Configuration Register */
! 49: #define BPP_OCR_IDLE 0x0008 /* State machines are idle */
! 50: #define BPP_OCR_SRST 0x0080 /* Reset bit */
! 51: #define BPP_OCR_ACK_OP 0x0100 /* ACK handshake operation */
! 52: #define BPP_OCR_BUSY_OP 0x0200 /* BUSY handshake operation */
! 53: #define BPP_OCR_EN_DIAG 0x0400 /* */
! 54: #define BPP_OCR_ACK_DSEL 0x0800 /* ack line is bidirectional */
! 55: #define BPP_OCR_BUSY_DSEL 0x1000 /* busy line is bidirectional */
! 56: #define BPP_OCR_DS_DSEL 0x2000 /* data strobe line is bidirectional */
! 57: #define BPP_OCR_DATA_SRC 0x4000 /* Data source for `memory clear' */
! 58: #define BPP_OCR_MEM_SRC 0x8000 /* Enable `memory clear' */
! 59:
! 60: /* Transfer Control Register */
! 61: #define BPP_TCR_DS 0x01 /* Data Strobe */
! 62: #define BPP_TCR_ACK 0x02 /* Acknowledge */
! 63: #define BPP_TCR_BUSY 0x04 /* Busy */
! 64: #define BPP_TCR_DIR 0x08 /* Direction control */
! 65:
! 66: /* Output Register */
! 67: #define BPP_OR_SLCTIN 0x01 /* Select */
! 68: #define BPP_OR_AFXN 0x02 /* Auto Feed */
! 69: #define BPP_OR_INIT 0x04 /* Initialize */
! 70:
! 71: /* Input Register (read-only) */
! 72: #define BPP_IR_ERR 0x01 /* Err input pin */
! 73: #define BPP_IR_SLCT 0x02 /* Select input pin */
! 74: #define BPP_IR_PE 0x04 /* Paper Out input pin */
! 75:
! 76: /* Interrupt Control Register */
! 77: #define BPP_ERR_IRQ_EN 0x0001 /* Error interrupt enable */
! 78: #define BPP_ERR_IRP 0x0002 /* ERR interrupt polarity */
! 79: #define BPP_SLCT_IRQ_EN 0x0004 /* Select interrupt enable */
! 80: #define BPP_SLCT_IRP 0x0008 /* Select interrupt polarity */
! 81: #define BPP_PE_IRQ_EN 0x0010 /* Paper Empty interrupt enable */
! 82: #define BPP_PE_IRP 0x0020 /* PE interrupt polarity */
! 83: #define BPP_BUSY_IRQ_EN 0x0040 /* BUSY interrupt enable */
! 84: #define BPP_BUSY_IRP 0x0080 /* BUSY interrupt polarity */
! 85: #define BPP_ACK_IRQ_EN 0x0100 /* ACK interrupt enable */
! 86: #define BPP_DS_IRQ_EN 0x0200 /* Data Strobe interrupt enable */
! 87: #define BPP_ERR_IRQ 0x0400 /* ERR interrupt pending */
! 88: #define BPP_SLCT_IRQ 0x0800 /* SLCT interrupt pending */
! 89: #define BPP_PE_IRQ 0x1000 /* PE interrupt pending */
! 90: #define BPP_BUSY_IRQ 0x2000 /* BUSY interrupt pending */
! 91: #define BPP_ACK_IRQ 0x4000 /* ACK interrupt pending */
! 92: #define BPP_DS_IRQ 0x8000 /* DS interrupt pending */
! 93:
! 94: /* Define mask for each of all irq request, all polarity and all enable bits */
! 95: #define BPP_ALLIRQ (BPP_ERR_IRQ|BPP_SLCT_IRQ|BPP_PE_IRQ| \
! 96: BPP_BUSY_IRQ|BPP_ACK_IRQ|BPP_DS_IRQ)
! 97: #define BPP_ALLEN (BPP_ERR_IRQ_EN|BPP_SLCT_IRQ_EN| \
! 98: BPP_PE_IRQ_EN|BPP_BUSY_IRQ_EN| \
! 99: BPP_ACK_IRQ_EN|BPP_DS_IRQ_EN)
! 100: #define BPP_ALLIRP (BPP_ERR_IRP|BPP_PE_IRP|BPP_BUSY_IRP)
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