Annotation of sys/dev/pcmcia/cfxgareg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: cfxgareg.h,v 1.5 2006/11/28 12:01:27 miod Exp $ */
2:
3: /*
4: * Copyright (c) 2005, 2006, Matthieu Herrb and Miodrag Vallat
5: *
6: * Permission to use, copy, modify, and distribute this software for any
7: * purpose with or without fee is hereby granted, provided that the above
8: * copyright notice and this permission notice appear in all copies.
9: *
10: * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHORS DISCLAIM ALL WARRANTIES
11: * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12: * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR
13: * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14: * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15: * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16: * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17: */
18:
19: /*
20: * S1D13806 Registers.
21: * Registers larger than 8 bits are little-endian.
22: */
23:
24: /* Revision code register - RO */
25: #define CFREG_REV 0x0000
26: #define CR_REV_MASK 0x03 /* revision code */
27: #define CR_REV_SHIFT 0
28: #define CR_PRODUCT_MASK 0xfc /* product code */
29: #define CR_PRODUCT_SHIFT 2
30: #define PRODUCT_S1D13806 0x07
31:
32: /* Miscellaneous register - RW */
33: #define CFREG_MISC 0x0001
34: #define CM_MEMSEL 0x00
35: #define CM_REGSEL 0x80 /* register/memory select */
36:
37: /* General IO pins configuration register - RW, 12 bits */
38: #define CFREG_GPIO_CONF 0x0004
39:
40: /* General IO pins control register - RW, 12 bits */
41: #define CFREG_GPIO_CTRL 0x0008
42:
43: /* Configuration status register - RO */
44: #define CFREG_STATUS 0x000c
45:
46: /* Memory clock configuration register - RW, needs 16 bits access */
47: #define CFREG_MEMCLK 0x0010
48: #define MEMCLK_DIVIDE 0x10
49: #define MEMCLK_SRC_CLKI 0x00
50: #define MEMCLK_SRC_BUSCLK 0x01
51: #define MEMCLK_SRC_CLK3 0x02
52:
53: /* LCD Pixel clock configuration register - RW */
54: #define CFREG_LCD_PCLK 0x0014
55: #define LCD_PCLK_SRC_CLKI 0x00
56: #define LCD_PCLK_SRC_BUSCLK 0x01
57: #define LCD_PCLK_SRC_CLKI2 0x02
58: #define LCD_PCLK_SRC_MCLK 0x03
59: #define LCD_PCLK_DIV_1 0x00
60: #define LCD_PCLK_DIV_2 0x10
61: #define LCD_PCLK_DIV_3 0x20
62: #define LCD_PCLK_DIV_4 0x30
63:
64: /* CRT/TV Pixel clock configuration register - RW */
65: #define CFREG_CRTTV_PCLK 0x0018
66: #define CRT_PCLK_SRC_CLKI 0x00
67: #define CRT_PCLK_SRC_BUSCLK 0x01
68: #define CRT_PCLK_SRC_CLKI2 0x02
69: #define CRT_PCLK_SRC_MCLK 0x03
70: #define CRT_PCLK_DIV_1 0x00
71: #define CRT_PCLK_DIV_2 0x10
72: #define CRT_PCLK_DIV_3 0x20
73: #define CRT_PCLK_DIV_4 0x30
74: #define CRT_PCLK_DOUBLE 0x80
75:
76: /* MediaPlug clock configuration register - RW */
77: #define CFREG_MPLUG_CLK 0x001c
78: #define MPLUG_PCLK_SRC_CLKI 0x00
79: #define MPLUG_PCLK_SRC_BUSCLK 0x01
80: #define MPLUG_PCLK_SRC_CLKI2 0x02
81: #define MPLUG_PCLK_SRC_MCLK 0x03
82: #define MPLUG_PCLK_DIV_1 0x00
83: #define MPLUG_PCLK_DIV_2 0x10
84: #define MPLUG_PCLK_DIV_3 0x20
85: #define MPLUG_PCLK_DIV_4 0x30
86:
87: /* CPU to memory wait state select register - RW */
88: #define CFREG_WSTATE 0x001e
89: #define WSTATE_NONE 0x00
90: #define WSTATE_DUAL_MCLK 0x01
91: #define WSTATE_MCLK 0x02
92:
93: /* Memory configuration register - RW */
94: #define CFREG_MEMCNF 0x0020
95: #define MEMCNF_SDRAM_INIT 0x80
96:
97: /* DRAM refresh rate register - RW */
98: #define CFREG_DRAM_RFRSH 0x0021
99: #define DRAM_RFRSH_8MHZ 0x00
100: #define DRAM_RFRSH_16MHZ 0x01
101: #define DRAM_RFRSH_32MHZ 0x02
102: #define DRAM_RFRSH_50MHZ 0x03
103:
104: /* DRAM timing control register - RW, 10 bits */
105: #define CFREG_DRAM_TIMING 0x002a
106: #define DRAM_TIMING_33MHZ 0x0311
107: #define DRAM_TIMING_44MHZ 0x0200
108: #define DRAM_TIMING_50MHZ 0x0100
109:
110: /* Panel type register - RW */
111: #define CFREG_PANEL 0x0030
112: #define PANEL_PASSIVE 0x00
113: #define PANEL_TFT 0x01
114: #define PANEL_SINGLE 0x00
115: #define PANEL_DUAL 0x02
116: #define PANEL_MONO 0x00
117: #define PANEL_COLOR 0x04
118: #define PANEL_FORMAT_1X 0x00
119: #define PANEL_FORMAT_2X 0x08
120: #define PANEL_WIDTH_4_9 0x00 /* passive: 4 bits, TDT: 9/2x9 bits */
121: #define PANEL_WIDTH_8_12 0x10 /* passive: 8 bits, TDT: 12/2x12 bits */
122: #define PANEL_WIDTH_16_18 0x20 /* passive: 16 bits, TDT: 18 bits */
123:
124: /* MOD rate register - RW */
125: #define CFREG_MODRATE 0x0031
126:
127: /* LCD horizontal display width register - RW */
128: #define CFREG_LCD_HWIDTH 0x0032
129:
130: /* LCD horizontal non-display period register - RW */
131: #define CFREG_LCD_HNDISP 0x0034
132:
133: /* TFT FPLINE start position register - RW */
134: #define CFREG_TFT_FPLINE_START 0x0035
135:
136: /* TFT FPLINE pulse width register - RW */
137: #define CFREG_TFT_FPLINE_WIDTH 0x0036
138: #define TFT_FPLINE_POL_TFT_LOW 0x00
139: #define TFT_FPLINE_POL_TFT_HIGH 0x80
140: #define TFT_FPLINE_POL_PASSIVE_LOW 0x80
141: #define TFT_FPLINE_POL_PASSIVE_HIGH 0x00
142:
143: /* LCD vertical display height - RW, 10 bits */
144: #define CFREG_LCD_VHEIGHT 0x0038
145:
146: /* LCD vertical non-display period register - RW */
147: #define CFREG_LCD_VNDISP 0x003a
148: #define LCD_VNDISP_STATUS 0x80 /* read only */
149:
150: /* TFT FPFRAME start position register - RW */
151: #define CFREG_TFT_FPFRAME_START 0x003b
152:
153: /* TFT FPFRAME pulse width register - RW */
154: #define CFREG_TFT_FPFRAME_WIDTH 0x003c
155: #define TFT_FPFRAME_POL_TFT_LOW 0x00
156: #define TFT_FPFRAME_POL_TFT_HIGH 0x80
157: #define TFT_FPFRAME_POL_PASSIVE_LOW 0x80
158: #define TFT_FPFRAME_POL_PASSIVE_HIGH 0x00
159:
160: /* LCD line count register - RO */
161: #define CFREG_LCD_LINECNT 0x003e
162:
163: /* LCD display mode register - RW */
164: #define CFREG_LCD_MODE 0x0040
165: #define LCD_MODE_4BPP 0x02
166: #define LCD_MODE_8BPP 0x03
167: #define LCD_MODE_15BPP 0x04
168: #define LCD_MODE_16BPP 0x05
169: #define LCD_MODE_SWIVEL_BIT1 0x10
170: #define LCD_MODE_BLANK 0x80
171:
172: /* LCD miscellaneous register - RW */
173: #define CFREG_LCD_MISC 0x0041
174: #define LCD_MISC_DUAL_PANEL_BUFFER_DISABLE 0x01
175: #define LCD_MISC_DITHERING_DISABLE 0x02
176:
177: /* LCD display start address - RW, 20 bits */
178: #define CFREG_LCD_START_LOW 0x0042
179: #define CFREG_LCD_START_HIGH 0x0044
180:
181: /* LCD memory address register - RW, 11 bits */
182: #define CFREG_LCD_MEMORY 0x0046
183:
184: /* LCD pixel panning register - RW */
185: #define CFREG_LCD_PANNING 0x0048
186: #define PIXEL_PANNING_MASK_4BPP 0x03
187: #define PIXEL_PANNING_MASK_8BPP 0x01
188: #define PIXEL_PANNING_MASK_15BPP 0x00
189: #define PIXEL_PANNING_MASK_16BPP 0x00
190:
191: /* LCD display FIFO high threshold control register - RW */
192: #define CFREG_LCD_FIFO_THRESHOLD_HIGH 0x004a
193:
194: /* LCD display FIFO low threshold control register - RW */
195: #define CFREG_LCD_FIFO_THRESHOLD_LOW 0x004b
196:
197: /* CRT/TV horizontal display width register - RW */
198: #define CFREG_CRT_HWIDTH 0x0050
199:
200: /* CRT/TV horizontal non-display period register - RW */
201: #define CFREG_CRT_HNDISP 0x0052
202:
203: /* CRT/TV HRTC start position register - RW */
204: #define CFREG_CRT_HSTART 0x0053
205:
206: /* CRT/TV HRTC pulse width register - RW */
207: #define CFREG_CRT_HPULSE 0x0054
208: #define HRTC_POLARITY 0x80
209:
210: /* CRT/TV vertical display height register - RW, 10 bits */
211: #define CFREG_CRT_VHEIGHT 0x0056
212:
213: /* CRT/TV vertical non-display period register - RW */
214: #define CFREG_CRT_VNDISP 0x0058
215: #define CRT_VNDISP_STATUS 0x80 /* RO */
216:
217: /* CRT/TV VRTC start position register - RW */
218: #define CFREG_CRT_VSTART 0x0059
219:
220: /* CRT VRTC pulse width register - RW */
221: #define CFREG_CRT_VPULSE 0x005a
222:
223: /* TV output control register - RW */
224: #define CFREG_TV_CONTROL 0x005b
225: #define TV_NTSC_OUTPUT 0x00
226: #define TV_PAL_OUTPUT 0x01
227: #define TV_COMPOSITE_OUTPUT 0x00
228: #define TV_SVIDEO_OUTPUT 0x02
229: #define TV_DAC_OUTPUT_HIGH 0x00 /* 9.2 mA IREF */
230: #define TV_DAC_OUTPUT_LOW 0x08 /* 4.6 mA IREF - CRT only */
231: #define TV_LUMINANCE_FILTER 0x10
232: #define TV_CHROMINANCE_FILTER 0x20
233:
234: /* CRT/TV line count register - RW */
235: #define CFREG_CRT_LINECNT 0x005e
236:
237: /* CRT/TV display mode register - RW */
238: #define CFREG_CRT_MODE 0x0060
239: #define CRT_MODE_4BPP 0x02
240: #define CRT_MODE_8BPP 0x03
241: #define CRT_MODE_15BPP 0x04
242: #define CRT_MODE_16BPP 0x05
243: #define CRT_MODE_BLANK 0x80
244:
245: /* CRT/TV display start address - RW, 20 bits */
246: #define CFREG_CRT_START_LOW 0x0062
247: #define CFREG_CRT_START_HIGH 0x0064
248:
249: /* CRT/TV memory address register - RW, 11 bits */
250: #define CFREG_CRT_MEMORY 0x0066
251:
252: /* CRT/TV pixel panning register - RW */
253: #define CFREG_CRT_PANNING 0x0068
254:
255: /* CRT/TV display FIFO high threshold control register - RW */
256: #define CFREG_CRT_FIFO_THRESHOLD_HIGH 0x006a
257:
258: /* CRT/TV display FIFO low threshold control register - RW */
259: #define CFREG_CRT_FIFO_THRESHOLD_LOW 0x006b
260:
261: /* LCD ink/cursor control register - RW */
262: #define CFREG_LCD_CURSOR_CONTROL 0x0070
263: #define CURSOR_INACTIVE 0x00
264: #define CURSOR_CURSOR 0x01
265: #define CURSOR_INK 0x02
266:
267: /* LCD ink/cursor start address register - RW */
268: #define CFREG_LCD_CURSOR_ADDRESS 0x0071
269:
270: /* LCD cursor X position register - RW, 10 bits + sign */
271: #define CFREG_LCD_CURSOR_X 0x0072
272: #define LCD_CURSOR_X_SIGN 0x8000
273:
274: /* LCD cursor Y position register - RW, 10 bits + sign */
275: #define CFREG_LCD_CURSOR_Y 0x0074
276: #define LCD_CURSOR_Y_SIGN 0x8000
277:
278: /* LCD ink/cursor color registers - RW */
279: #define CFREG_LCD_CURSOR_B0 0x0076 /* 5 bits */
280: #define CFREG_LCD_CURSOR_G0 0x0077 /* 6 bits */
281: #define CFREG_LCD_CURSOR_R0 0x0078 /* 5 bits */
282: #define CFREG_LCD_CURSOR_B1 0x007a /* 5 bits */
283: #define CFREG_LCD_CURSOR_G1 0x007b /* 6 bits */
284: #define CFREG_LCD_CURSOR_R1 0x007c /* 5 bits */
285:
286: /* LCD ink/cursor FIFO threshold register - RW */
287: #define CFREG_LCD_CURSOR_FIFO 0x007e
288:
289: /* CRT/TV ink/cursor control register - RW */
290: #define CFREG_CRT_CURSOR_CONTROL 0x0080
291:
292: /* CRT/TV ink/cursor start address register - RW */
293: #define CFREG_CRT_CURSOR_ADDRESS 0x0081
294:
295: /* CRT/TV cursor X position register - RW, 10 bits + sign */
296: #define CFREG_CRT_CURSOR_X 0x0082
297: #define CRT_CURSOR_X_SIGN 0x8000
298:
299: /* CRT/TV cursor Y position register - RW, 10 bits + sign */
300: #define CFREG_CRT_CURSOR_Y 0x0084
301: #define CRT_CURSOR_Y_SIGN 0x8000
302:
303: /* CRT/TV ink/cursor color registers - RW */
304: #define CFREG_CRT_CURSOR_B0 0x0086 /* 5 bits */
305: #define CFREG_CRT_CURSOR_G0 0x0087 /* 6 bits */
306: #define CFREG_CRT_CURSOR_R0 0x0088 /* 5 bits */
307: #define CFREG_CRT_CURSOR_B1 0x008a /* 5 bits */
308: #define CFREG_CRT_CURSOR_G1 0x008b /* 6 bits */
309: #define CFREG_CRT_CURSOR_R1 0x008c /* 5 bits */
310:
311: /* CRT/TV ink/cursor FIFO threshold register - RW */
312: #define CFREG_CRT_CURSOR_FIFO 0x008e
313:
314: /* Bitblt control register - RW, 16 bits */
315: #define CFREG_BITBLT_CONTROL 0x0100
316: #define BITBLT_SRC_LINEAR 0x0001
317: #define BITBLT_DST_LINEAR 0x0002
318: #define BITBLT_FIFO_FULL 0x0010 /* RO */
319: #define BITBLT_FIFO_HALF_FULL 0x0020 /* RO */
320: #define BITBLT_FIFO_NOT_EMPTY 0x0040 /* RO */
321: #define BITBLT_ACTIVE 0x0080
322: #define BITBLT_COLOR_8 0x0000
323: #define BITBLT_COLOR_16 0x0100
324:
325: /* Bitblt ROP code / color expansion register - RW */
326: #define CFREG_BITBLT_ROP 0x0102
327: #define CFREG_COLOR_EXPANSION 0x0102
328: #define ROP_ZERO 0x00
329: #define ROP_DST 0x0a
330: #define ROP_SRC 0x0c
331: #define ROP_ONES 0x0f
332:
333: /* Bitblt operation register - RW */
334: #define CFREG_BITBLT_OPERATION 0x103
335: #define OP_WRITE_ROP 0x00
336: #define OP_READ 0x01
337: #define OP_MOVE_POSITIVE_ROP 0x02
338: #define OP_MOVE_NEGATIVE_ROP 0x03
339: #define OP_TRANSPARENT_WRITE 0x04
340: #define OP_TRANSPARENT_MOVE_POSITIVE 0x05
341: #define OP_PATTERN_FILL_ROP 0x06
342: #define OP_PATTERN_FILL_TRANSPARENCY 0x07
343: #define OP_COLOR_EXPANSION 0x08
344: #define OP_COLOR_EXPANSION_TRANSPARENCY 0x09
345: #define OP_MOVE_COLOR_EXPANSION 0x0a
346: #define OP_MOVE_COLOR_EXPANSION_TRANSPARENCY 0x0b
347: #define OP_SOLID_FILL 0x0c
348:
349: /* Bitblt source address register - RW, 21 bits */
350: #define CFREG_BITBLT_SRC_LOW 0x104
351: #define CFREG_BITBLT_SRC_HIGH 0x106
352:
353: /* Bitblt destination start address register - RW, 21 bits */
354: #define CFREG_BITBLT_DST_LOW 0x108
355: #define CFREG_BITBLT_DST_HIGH 0x10a
356:
357: /* Bitblt memory address offset register - RW, 11 bits */
358: #define CFREG_BITBLT_OFFSET 0x10c
359:
360: /* Bitblt width register - RW, 10 bits */
361: #define CFREG_BITBLT_WIDTH 0x110
362:
363: /* Bitblt height register - RW, 10 bits */
364: #define CFREG_BITBLT_HEIGHT 0x112
365:
366: /* Bitblt color registers - RW, 16 bits */
367: #define CFREG_BITBLT_BG 0x114
368: #define CFREG_BITBLT_FG 0x118
369:
370: /* Lookup table mode register - RW */
371: #define CFREG_LUT_MODE 0x1e0
372: #define LUT_BOTH 0x00 /* read LCD, write LCD and CRT/TV */
373: #define LUT_LCD 0x01 /* read LCD, write LCD */
374: #define LUT_CRT 0x02 /* read CRT/TV, write CRT/TV */
375:
376: /* LUT address register - RW */
377: #define CFREG_LUT_ADDRESS 0x1e2
378:
379: /* LUT data register - RW */
380: #define CFREG_LUT_DATA 0x1e4 /* data in the high 4 bits */
381:
382: /* Power save configuration register - RW */
383: #define CFREG_POWER_CONF 0x1f0
384: #define POWERSAVE_ENABLE 0x01
385: #define POWERSAVE_MBO 0x10
386:
387: /* Power save status register - RW */
388: #define CFREG_POWER_STATUS 0x1f1
389: #define POWERSAVE_STATUS 0x01
390: #define LCD_POWERSAVE_STATUS 0x02
391:
392: /* CPU to memory access watchdog timer register - RW */
393: #define CFREG_WATCHDOG 0x1f4
394:
395: /* Display mode register - RW */
396: #define CFREG_MODE 0x1fc
397: #define MODE_NO_DISPLAY 0x00
398: #define MODE_LCD 0x01 /* can be combined with all modes */
399: #define MODE_CRT 0x02
400: #define MODE_TV_NO_FLICKER 0x04
401: #define MODE_TV_FLICKER 0x06
402: #define LCD_MODE_SWIVEL_BIT_0 0x40
403:
404: /* BitBlt aperture */
405: #define CFREG_BITBLT_DATA 0x0400
406:
407: #ifdef _KERNEL
408: #define CFXGA_MEM_RANGE 0x0800
409: #endif
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