Annotation of sys/dev/pci/tgavar.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: tgavar.h,v 1.9 2006/12/17 22:18:16 miod Exp $ */
2: /* $NetBSD: tgavar.h,v 1.8 2000/04/02 19:01:11 nathanw Exp $ */
3:
4: /*
5: * Copyright (c) 1995, 1996 Carnegie-Mellon University.
6: * All rights reserved.
7: *
8: * Author: Chris G. Demetriou
9: *
10: * Permission to use, copy, modify and distribute this software and
11: * its documentation is hereby granted, provided that both the copyright
12: * notice and this permission notice appear in all copies of the
13: * software, derivative works or modified versions, and any portions
14: * thereof, and that both notices appear in supporting documentation.
15: *
16: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
17: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
18: * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
19: *
20: * Carnegie Mellon requests users of this software to return to
21: *
22: * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
23: * School of Computer Science
24: * Carnegie Mellon University
25: * Pittsburgh PA 15213-3890
26: *
27: * any improvements or extensions that they make and grant Carnegie the
28: * rights to redistribute these changes.
29: */
30:
31: #include <dev/ic/ramdac.h>
32: #include <dev/pci/tgareg.h>
33: #include <dev/wscons/wsconsio.h>
34: #include <dev/wscons/wsdisplayvar.h>
35: #include <dev/rasops/rasops.h>
36:
37: struct tga_devconfig;
38: struct fbcmap;
39: struct fbcursor;
40: struct fbcurpos;
41:
42: struct tga_conf {
43: char *tgac_name; /* name for this board type */
44:
45: struct ramdac_funcs *(*ramdac_funcs)(void);
46:
47: int tgac_phys_depth; /* physical frame buffer depth */
48: vsize_t tgac_cspace_size; /* core space size */
49: vsize_t tgac_vvbr_units; /* what '1' in the VVBR means */
50:
51: int tgac_ndbuf; /* number of display buffers */
52: vaddr_t tgac_dbuf[2]; /* display buffer offsets/addresses */
53: vsize_t tgac_dbufsz[2]; /* display buffer sizes */
54:
55: int tgac_nbbuf; /* number of display buffers */
56: vaddr_t tgac_bbuf[2]; /* back buffer offsets/addresses */
57: vsize_t tgac_bbufsz[2]; /* back buffer sizes */
58: };
59:
60: struct tga_devconfig {
61: bus_space_tag_t dc_memt;
62: bus_space_handle_t dc_memh;
63:
64: pcitag_t dc_pcitag; /* PCI tag */
65: bus_addr_t dc_pcipaddr; /* PCI phys addr. */
66:
67: bus_space_handle_t dc_regs; /* registers; XXX: need aliases */
68:
69: int dc_tga_type; /* the device type; see below */
70: int dc_tga2; /* True if it is a TGA2 */
71: const struct tga_conf *dc_tgaconf; /* device buffer configuration */
72:
73: struct ramdac_funcs
74: *dc_ramdac_funcs; /* The RAMDAC functions */
75: struct ramdac_cookie
76: *dc_ramdac_cookie; /* the RAMDAC type; see above */
77:
78: vaddr_t dc_vaddr; /* memory space virtual base address */
79: paddr_t dc_paddr; /* memory space physical base address */
80:
81: int dc_wid; /* width of frame buffer */
82: int dc_ht; /* height of frame buffer */
83: int dc_rowbytes; /* bytes in a FB scan line */
84:
85: vaddr_t dc_videobase; /* base of flat frame buffer */
86:
87: struct rasops_info dc_rinfo; /* raster display data */
88:
89: int dc_blanked; /* currently had video disabled */
90: void *dc_ramdac_private; /* RAMDAC private storage */
91:
92: void (*dc_ramdac_intr)(void *);
93: int dc_intrenabled; /* can we depend on interrupts yet? */
94: };
95:
96: struct tga_softc {
97: struct device sc_dev;
98:
99: struct tga_devconfig *sc_dc; /* device configuration */
100: void *sc_intr; /* interrupt handler info */
101: u_int sc_mode; /* wscons mode used */
102: /* XXX should record intr fns/arg */
103:
104: int nscreens;
105: };
106:
107: #define TGA_TYPE_T8_01 0 /* 8bpp, 1MB */
108: #define TGA_TYPE_T8_02 1 /* 8bpp, 2MB */
109: #define TGA_TYPE_T8_22 2 /* 8bpp, 4MB */
110: #define TGA_TYPE_T8_44 3 /* 8bpp, 8MB */
111: #define TGA_TYPE_T32_04 4 /* 32bpp, 4MB */
112: #define TGA_TYPE_T32_08 5 /* 32bpp, 8MB */
113: #define TGA_TYPE_T32_88 6 /* 32bpp, 16MB */
114: #define TGA_TYPE_POWERSTORM_4D20 7 /* unknown */
115: #define TGA_TYPE_UNKNOWN 8 /* unknown */
116:
117: #define DEVICE_IS_TGA(class, id) \
118: (((PCI_VENDOR(id) == PCI_VENDOR_DEC && \
119: PCI_PRODUCT(id) == PCI_PRODUCT_DEC_21030) || \
120: PCI_PRODUCT(id) == PCI_PRODUCT_DEC_PBXGB) ? 10 : 0)
121:
122: int tga_cnattach(bus_space_tag_t, bus_space_tag_t, pci_chipset_tag_t,
123: int, int, int);
124:
125: int tga_identify(struct tga_devconfig *);
126: const struct tga_conf *tga_getconf(int);
127:
128: int tga_builtin_set_cursor(struct tga_devconfig *,
129: struct wsdisplay_cursor *);
130: int tga_builtin_get_cursor(struct tga_devconfig *,
131: struct wsdisplay_cursor *);
132: int tga_builtin_set_curpos(struct tga_devconfig *,
133: struct wsdisplay_curpos *);
134: int tga_builtin_get_curpos(struct tga_devconfig *,
135: struct wsdisplay_curpos *);
136: int tga_builtin_get_curmax(struct tga_devconfig *,
137: struct wsdisplay_curpos *);
138:
139: /* Read a TGA register */
140: #define TGARREG(dc,reg) (bus_space_read_4((dc)->dc_memt, (dc)->dc_regs, \
141: (reg) << 2))
142:
143: /* Write a TGA register */
144: #define TGAWREG(dc,reg,val) bus_space_write_4((dc)->dc_memt, (dc)->dc_regs, \
145: (reg) << 2, (val))
146:
147: /* Write a TGA register at an alternate aliased location */
148: #define TGAWALREG(dc,reg,alias,val) bus_space_write_4( \
149: (dc)->dc_memt, (dc)->dc_regs, \
150: ((alias) * TGA_CREGS_ALIAS) + ((reg) << 2), \
151: (val))
152:
153: /* Insert a write barrier */
154: #define TGAREGWB(dc,reg, nregs) bus_space_barrier( \
155: (dc)->dc_memt, (dc)->dc_regs, \
156: ((reg) << 2), 4 * (nregs), BUS_SPACE_BARRIER_WRITE)
157:
158: /* Insert a read barrier */
159: #define TGAREGRB(dc,reg, nregs) bus_space_barrier( \
160: (dc)->dc_memt, (dc)->dc_regs, \
161: ((reg) << 2), 4 * (nregs), BUS_SPACE_BARRIER_READ)
162:
163: /* Insert a read/write barrier */
164: #define TGAREGRWB(dc,reg, nregs) bus_space_barrier( \
165: (dc)->dc_memt, (dc)->dc_regs, \
166: ((reg) << 2), 4 * (nregs), \
167: BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
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