Annotation of sys/dev/pci/tgareg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: tgareg.h,v 1.4 2001/03/18 04:37:21 nate Exp $ */
! 2: /* $NetBSD: tgareg.h,v 1.3 2000/03/04 10:28:00 elric Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 1995, 1996 Carnegie-Mellon University.
! 6: * All rights reserved.
! 7: *
! 8: * Author: Chris G. Demetriou
! 9: *
! 10: * Permission to use, copy, modify and distribute this software and
! 11: * its documentation is hereby granted, provided that both the copyright
! 12: * notice and this permission notice appear in all copies of the
! 13: * software, derivative works or modified versions, and any portions
! 14: * thereof, and that both notices appear in supporting documentation.
! 15: *
! 16: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
! 17: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
! 18: * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
! 19: *
! 20: * Carnegie Mellon requests users of this software to return to
! 21: *
! 22: * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
! 23: * School of Computer Science
! 24: * Carnegie Mellon University
! 25: * Pittsburgh PA 15213-3890
! 26: *
! 27: * any improvements or extensions that they make and grant Carnegie the
! 28: * rights to redistribute these changes.
! 29: */
! 30:
! 31: #ifndef _ALPHA_INCLUDE_TGAREG_H_
! 32: #define _ALPHA_INCLUDE_TGAREG_H_
! 33:
! 34: /*
! 35: * Device-specific PCI register offsets and contents.
! 36: */
! 37:
! 38: #define TGA_PCIREG_PVRR 0x40 /* PCI Address Extension Register */
! 39:
! 40: #define TGA_PCIREG_PAER 0x44 /* PCI VGA Redirect Register */
! 41:
! 42: /*
! 43: * TGA Memory Space offsets
! 44: */
! 45:
! 46: #define TGA_MEM_ALTROM 0x0000000 /* 0MB -- Alternate ROM space */
! 47: #define TGA2_MEM_EXTDEV 0x0000000 /* 0MB -- External Device Access */
! 48: #define TGA_MEM_CREGS 0x0100000 /* 1MB -- Core Registers */
! 49: #define TGA_CREGS_SIZE 0x0100000 /* Core registers occupy 1MB */
! 50: #define TGA_CREGS_ALIAS 0x0000400 /* Register copies every 1kB */
! 51:
! 52: #define TGA2_MEM_CLOCK 0x0060000 /* TGA2 Clock access */
! 53: #define TGA2_MEM_RAMDAC 0x0080000 /* TGA2 RAMDAC access */
! 54:
! 55: /* Display and Back Buffers mapped at config-dependent addresses */
! 56:
! 57: /*
! 58: * TGA Core Space register numbers and contents.
! 59: */
! 60:
! 61: typedef u_int32_t tga_reg_t;
! 62:
! 63: #define TGA_REG_GCBR0 0x000 /* Copy buffer 0 */
! 64: #define TGA_REG_GCBR1 0x001 /* Copy buffer 1 */
! 65: #define TGA_REG_GCBR2 0x002 /* Copy buffer 2 */
! 66: #define TGA_REG_GCBR3 0x003 /* Copy buffer 3 */
! 67: #define TGA_REG_GCBR4 0x004 /* Copy buffer 4 */
! 68: #define TGA_REG_GCBR5 0x005 /* Copy buffer 5 */
! 69: #define TGA_REG_GCBR6 0x006 /* Copy buffer 6 */
! 70: #define TGA_REG_GCBR7 0x007 /* Copy buffer 7 */
! 71:
! 72: #define TGA_REG_GFGR 0x008 /* Foreground */
! 73: #define TGA_REG_GBGR 0x009 /* Background */
! 74: #define TGA_REG_GPMR 0x00a /* Plane Mask */
! 75: #define TGA_REG_GPXR_S 0x00b /* Pixel Mask (one-shot) */
! 76: #define TGA_REG_GMOR 0x00c /* Mode */
! 77: #define TGA_REG_GOPR 0x00d /* Raster Operation */
! 78: #define TGA_REG_GPSR 0x00e /* Pixel Shift */
! 79: #define TGA_REG_GADR 0x00f /* Address */
! 80:
! 81: #define TGA_REG_GB1R 0x010 /* Bresenham 1 */
! 82: #define TGA_REG_GB2R 0x011 /* Bresenham 2 */
! 83: #define TGA_REG_GB3R 0x012 /* Bresenham 3 */
! 84:
! 85: #define TGA_REG_GCTR 0x013 /* Continue */
! 86: #define TGA_REG_GDER 0x014 /* Deep */
! 87: #define TGA_REG_GREV 0x015 /* Start/Version on TGA,
! 88: * Revision on TGA2 */
! 89: #define TGA_REG_GSMR 0x016 /* Stencil Mode */
! 90: #define TGA_REG_GPXR_P 0x017 /* Pixel Mask (persistent) */
! 91: #define TGA_REG_CCBR 0x018 /* Cursor Base Address */
! 92: #define TGA_REG_VHCR 0x019 /* Horizontal Control */
! 93: #define TGA_REG_VVCR 0x01a /* Vertical Control */
! 94: #define TGA_REG_VVBR 0x01b /* Video Base Address */
! 95: #define TGA_REG_VVVR 0x01c /* Video Valid */
! 96: #define TGA_REG_CXYR 0x01d /* Cursor XY */
! 97: #define TGA_REG_VSAR 0x01e /* Video Shift Address */
! 98: #define TGA_REG_SISR 0x01f /* Interrupt Status */
! 99: #define TGA_REG_GDAR 0x020 /* Data */
! 100: #define TGA_REG_GRIR 0x021 /* Red Increment */
! 101: #define TGA_REG_GGIR 0x022 /* Green Increment */
! 102: #define TGA_REG_GBIR 0x023 /* Blue Increment */
! 103: #define TGA_REG_GZIR_L 0x024 /* Z-increment Low */
! 104: #define TGA_REG_GZIR_H 0x025 /* Z-Increment High */
! 105: #define TGA_REG_GDBR 0x026 /* DMA Base Address */
! 106: #define TGA_REG_GBWR 0x027 /* Bresenham Width */
! 107: #define TGA_REG_GZVR_L 0x028 /* Z-value Low */
! 108: #define TGA_REG_GZVR_H 0x029 /* Z-value High */
! 109: #define TGA_REG_GZBR 0x02a /* Z-base address */
! 110: /* GADR alias 0x02b */
! 111: #define TGA_REG_GRVR 0x02c /* Red Value */
! 112: #define TGA_REG_GGVR 0x02d /* Green Value */
! 113: #define TGA_REG_GBVR 0x02e /* Blue Value */
! 114: #define TGA_REG_GSWR 0x02f /* Span Width */
! 115: #define TGA_REG_EPSR 0x030 /* Pallete and DAC Setup */
! 116:
! 117: /* reserved 0x031 - 0x3f */
! 118:
! 119: #define TGA_REG_GSNR0 0x040 /* Slope-no-go 0 */
! 120: #define TGA_REG_GSNR1 0x041 /* Slope-no-go 1 */
! 121: #define TGA_REG_GSNR2 0x042 /* Slope-no-go 2 */
! 122: #define TGA_REG_GSNR3 0x043 /* Slope-no-go 3 */
! 123: #define TGA_REG_GSNR4 0x044 /* Slope-no-go 4 */
! 124: #define TGA_REG_GSNR5 0x045 /* Slope-no-go 5 */
! 125: #define TGA_REG_GSNR6 0x046 /* Slope-no-go 6 */
! 126: #define TGA_REG_GSNR7 0x047 /* Slope-no-go 7 */
! 127:
! 128: #define TGA_REG_GSLR0 0x048 /* Slope 0 */
! 129: #define TGA_REG_GSLR1 0x049 /* Slope 1 */
! 130: #define TGA_REG_GSLR2 0x04a /* Slope 2 */
! 131: #define TGA_REG_GSLR3 0x04b /* Slope 3 */
! 132: #define TGA_REG_GSLR4 0x04c /* Slope 4 */
! 133: #define TGA_REG_GSLR5 0x04d /* Slope 5 */
! 134: #define TGA_REG_GSLR6 0x04e /* Slope 6 */
! 135: #define TGA_REG_GSLR7 0x04f /* Slope 7 */
! 136:
! 137: #define TGA_REG_GBCR0 0x050 /* Block Color 0 */
! 138: #define TGA_REG_GBCR1 0x051 /* Block Color 1 */
! 139: #define TGA_REG_GBCR2 0x052 /* Block Color 2 */
! 140: #define TGA_REG_GBCR3 0x053 /* Block Color 3 */
! 141: #define TGA_REG_GBCR4 0x054 /* Block Color 4 */
! 142: #define TGA_REG_GBCR5 0x055 /* Block Color 5 */
! 143: #define TGA_REG_GBCR6 0x056 /* Block Color 6 */
! 144: #define TGA_REG_GBCR7 0x057 /* Block Color 7 */
! 145:
! 146: #define TGA_REG_GCSR 0x058 /* Copy 64 Source */
! 147: #define TGA_REG_GCDR 0x059 /* Copy 64 Destination */
! 148: /* GC[SD]R aliases 0x05a - 0x05f */
! 149:
! 150: /* reserved 0x060 - 0x077 */
! 151:
! 152: #define TGA_REG_ERWR 0x078 /* EEPROM write */
! 153:
! 154: /* reserved 0x079 */
! 155:
! 156: #define TGA_REG_ECGR 0x07a /* Clock */
! 157:
! 158: /* reserved 0x07b */
! 159:
! 160: #define TGA_REG_EPDR 0x07c /* Pallete and DAC Data */
! 161:
! 162: /* reserved 0x07d */
! 163:
! 164: #define TGA_REG_SCSR 0x07e /* Command Status */
! 165:
! 166: /* reserved 0x07f */
! 167:
! 168: /*
! 169: * Video Valid Register
! 170: */
! 171: #define VVR_VIDEOVALID 0x00000001 /* 0 VGA, 1 TGA2 (TGA2 only) */
! 172: #define VVR_BLANK 0x00000002 /* 0 active, 1 blank */
! 173: #define VVR_CURSOR 0x00000004 /* 0 disable, 1 enable (TGA2 R/O) */
! 174: #define VVR_INTERLACE 0x00000008 /* 0 N/Int, 1 Int. (TGA2 R/O) */
! 175: #define VVR_DPMS_MASK 0x00000030 /* See "DMPS mask" below */
! 176: #define VVR_DPMS_SHIFT 4
! 177: #define VVR_DDC 0x00000040 /* DDC-in pin value (R/O) */
! 178: #define VVR_TILED 0x00000400 /* 0 linear, 1 tiled (not on TGA2) */
! 179: #define VVR_LDDLY_MASK 0x01ff0000 /* load delay in quad pixel clock ticks
! 180: (not on TGA2) */
! 181: #define VVR_LDDLY_SHIFT 16
! 182:
! 183: #endif /* _ALPHA_INCLUDE_TGAREG_H_ */
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