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Annotation of sys/dev/pci/ppbreg.h, Revision 1.1.1.1

1.1       nbrk        1: /*     $OpenBSD: ppbreg.h,v 1.2 2001/11/14 21:04:46 mickey Exp $       */
                      2: /*     $NetBSD: ppbreg.h,v 1.3 2001/07/06 18:07:16 mcr Exp $   */
                      3:
                      4: /*
                      5:  * Copyright (c) 1996 Christopher G. Demetriou.  All rights reserved.
                      6:  *
                      7:  * Redistribution and use in source and binary forms, with or without
                      8:  * modification, are permitted provided that the following conditions
                      9:  * are met:
                     10:  * 1. Redistributions of source code must retain the above copyright
                     11:  *    notice, this list of conditions and the following disclaimer.
                     12:  * 2. Redistributions in binary form must reproduce the above copyright
                     13:  *    notice, this list of conditions and the following disclaimer in the
                     14:  *    documentation and/or other materials provided with the distribution.
                     15:  * 3. All advertising materials mentioning features or use of this software
                     16:  *    must display the following acknowledgement:
                     17:  *      This product includes software developed by Christopher G. Demetriou
                     18:  *     for the NetBSD Project.
                     19:  * 4. The name of the author may not be used to endorse or promote products
                     20:  *    derived from this software without specific prior written permission
                     21:  *
                     22:  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
                     23:  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
                     24:  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
                     25:  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
                     26:  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
                     27:  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
                     28:  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
                     29:  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
                     30:  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
                     31:  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
                     32:  */
                     33:
                     34: /*
                     35:  * PCI-PCI Bridge chip register definitions and macros.
                     36:  * Derived from information found in the ``PCI to PCI Bridge
                     37:  * Architecture Specification, Revision 1.0, April 5, 1994.''
                     38:  *
                     39:  * XXX much is missing.
                     40:  */
                     41:
                     42: /*
                     43:  * Register offsets
                     44:  */
                     45: #define        PPB_REG_BASE0           0x10            /* Base Addr Reg. 0 */
                     46: #define        PPB_REG_BASE1           0x14            /* Base Addr Reg. 1 */
                     47: #define        PPB_REG_BUSINFO         0x18            /* Bus information */
                     48: #define        PPB_REG_IOSTATUS        0x1c            /* I/O base+lim & sec stat */
                     49: #define        PPB_REG_MEM             0x20            /* Memory base/limit */
                     50: #define        PPB_REG_PREFMEM         0x24            /* Pref Mem  base/limit */
                     51: #define        PPB_REG_PREFBASE_HI32   0x28            /* Pref Mem base high bits */
                     52: #define        PPB_REG_PREFLIM_HI32    0x2c            /* Pref Mem lim high bits */
                     53: #define        PPB_REG_IO_HI           0x30            /* I/O base+lim high bits */
                     54: #define        PPB_REG_BRIDGECONTROL   0x3c            /* bridge control register */
                     55:
                     56: /*
                     57:  * Macros to extract the contents of the "Bus Info" register.
                     58:  */
                     59: #define        PPB_BUSINFO_PRIMARY(bir)                                        \
                     60:            ((bir >>  0) & 0xff)
                     61: #define        PPB_BUSINFO_SECONDARY(bir)                                      \
                     62:            ((bir >>  8) & 0xff)
                     63: #define        PPB_BUSINFO_SUBORDINATE(bir)                                    \
                     64:            ((bir >> 16) & 0xff)
                     65: #define        PPB_BUSINFO_SECLAT(bir)                                         \
                     66:            ((bir >> 24) & 0xff)
                     67:
                     68: /*
                     69:  * Routine to translate between secondary bus interrupt pin/device number and
                     70:  * primary bus interrupt pin number.
                     71:  */
                     72: #define        PPB_INTERRUPT_SWIZZLE(pin, device)                              \
                     73:            ((((pin) + (device) - 1) % 4) + 1)
                     74:
                     75: /*
                     76:  * secondary bus I/O base and limits
                     77:  */
                     78: #define PPB_IOBASE_SHIFT   0
                     79: #define PPB_IOLIMIT_SHIFT  8
                     80: #define PPB_IO_MASK   0xf000
                     81: #define PPB_IO_MIN    4096
                     82:
                     83: /*
                     84:  * secondary bus memory base and limits
                     85:  */
                     86: #define PPB_MEMBASE_SHIFT  0
                     87: #define PPB_MEMLIMIT_SHIFT 16
                     88: #define PPB_MEM_MASK   0xfff00000
                     89: #define PPB_MEM_SHIFT  16
                     90: #define PPB_MEM_MIN    0x00100000
                     91:
                     92: /*
                     93:  * bridge control register (see table 3.9 of ppb rev. 1.1)
                     94:  *
                     95:  * Note these are in the *upper* 16 bits if the Bridge Control
                     96:  * Register (the bottom 16 are Interrupt Line and Interrupt Pin).
                     97:  */
                     98: #define        PPB_BC_BITBASE                     16
                     99:
                    100: #define PPB_BC_PARITYERRORRESPONSE_ENABLE  (1U << (0 + PPB_BC_BITBASE))
                    101: #define PPB_BC_SERR_ENABLE                 (1U << (1 + PPB_BC_BITBASE))
                    102: #define PPB_BC_ISA_ENABLE                  (1U << (2 + PPB_BC_BITBASE))
                    103: #define PPB_BC_VGA_ENABLE                  (1U << (3 + PPB_BC_BITBASE))
                    104: #define PPB_BC_MASTER_ABORT_MODE           (1U << (5 + PPB_BC_BITBASE))
                    105: #define PPB_BC_SECONDARY_RESET             (1U << (6 + PPB_BC_BITBASE))
                    106: #define        PPB_BC_FAST_B2B_ENABLE             (1U << (7 + PPB_BC_BITBASE))
                    107:        /* PCI 2.2 */
                    108: #define        PPB_BC_PRIMARY_DISCARD_TIMEOUT     (1U << (8 + PPB_BC_BITBASE))
                    109: #define        PPB_BC_SECONDARY_DISCARD_TIMEOUT   (1U << (9 + PPB_BC_BITBASE))
                    110: #define        PPB_BC_DISCARD_TIMER_STATUS        (1U << (10 + PPB_BC_BITBASE))
                    111: #define        PPB_BC_DISCARD_TIMER_SERR_ENABLE   (1U << (11 + PPB_BC_BITBASE))