Annotation of sys/dev/pci/plx9060reg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: plx9060reg.h,v 1.2 2005/11/21 21:52:47 miod Exp $ */
2: /* $NetBSD$ */
3:
4: /*-
5: * Copyright (c) 2000 Zembu Labs, Inc.
6: * All rights reserved.
7: *
8: * Author: Jason R. Thorpe <thorpej@zembu.com>
9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: * 3. All advertising materials mentioning features or use of this software
19: * must display the following acknowledgement:
20: * This product includes software developed by Zembu Labs, Inc.
21: * 4. Neither the name of Zembu Labs nor the names of its employees may
22: * be used to endorse or promote products derived from this software
23: * without specific prior written permission.
24: *
25: * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS
26: * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR-
27: * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS-
28: * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT,
29: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
30: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
34: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35: */
36:
37: /*
38: * Register description for the PLX 9060-family of PCI bus
39: * controllers.
40: *
41: * In order for this file to be really useful to you, you'll want to
42: * have the PLX 9060 datasheet in front of you.
43: */
44:
45: #ifndef _DEV_PCI_PLX9060REG_H_
46: #define _DEV_PCI_PLX9060REG_H_
47:
48: /*
49: * PLX 9060 PCI configuration space registers.
50: */
51:
52: #define PLX_PCI_RUNTIME_MEMADDR 0x10 /* memory mapped 9060 */
53: #define PLX_PCI_RUNTIME_IOADDR 0x14 /* i/o mapped 9060 */
54: #define PLX_PCI_LOCAL_ADDR0 0x18 /* PCI address of 9060 local bus */
55:
56: /*
57: * PLX 9060 Runtime registers, in PCI space.
58: */
59:
60: /* Local Address Space 0 Range Register */
61: #define PLX_LAS0RR 0x00
62: #define LASRR_IO 0x00000001
63: #define LASRR_MEM_1M 0x00000002
64: #define LASRR_MEM_64BIT 0x00000004
65: #define LASRR_MEM_PREFETCH 0x00000008
66: #define LASRR_MEM_MASK 0xfffffff0
67: #define LASRR_IO_MASK 0xfffffffc
68:
69:
70: /* Local Address Space 0 Local Base Address (remap) Register */
71: #define PLX_LAS0BA 0x04
72: #define LASBA_ENABLE 0x00000001
73: #define LASBA_MEM_MASK 0xfffffff0
74: #define LASBA_IO_MASK 0xfffffffc
75:
76:
77: /* Local Arbitration Register */
78: #define PLX_LAR 0x08
79: #define LAR_LATTMR 0x000000ff
80: #define LAR_PAUSETMR 0x0000ff00
81: #define LAR_LATTMR_EN 0x00010000
82: #define LAR_BREQ_EN 0x00040000
83: #define LAR_DSGIVEUP 0x00200000
84: #define LAR_DSLOCK_EN 0x00400000
85: #define LAR_PCI21_MODE 0x01000000
86:
87:
88: /* Big/Little Endian Register */
89: #define PLX_ENDIAN 0x0c
90: #define ENDIAN_CRBE 0x00000001
91: #define ENDIAN_DMBE 0x00000002
92: #define ENDIAN_DSAS0BE 0x00000004
93: #define ENDIAN_DSAERBE 0x00000008
94: #define ENDIAN_BEBL 0x00000010
95:
96:
97: /* Expansion ROM Range Register */
98: #define PLX_EROMRR 0x10
99: #define EROMRR_MASK 0xffffffc0
100:
101:
102: /* Expansion ROM Base Address (remap) Register */
103: #define PLX_EROMBA 0x14
104: #define EROMBA_BREQ_DC 0x0000000f
105: #define EROMBA_BREQ_EN 0x00000010
106: #define EROMBA_MASK 0xffffffc0
107:
108:
109: /* Local Bus Region Descriptor for PCI to Local Access Register */
110: #define PLX_LBRD 0x18
111:
112:
113: /* Local Range for Direct Master to PCI */
114: #define PLX_DMRR 0x1c
115:
116:
117: /* Local Bus Base Address for Direct Master to PCI Memory */
118: #define PLX_DMLBAM 0x20
119:
120:
121: /* Local Bus Base Address for Direct Master to PCI IO/Config */
122: #define PLX_DMLBAI 0x24
123:
124:
125: /* PCI Base Address (remap) for Direct Master to PCI Memory */
126: #define PLX_DMBPAM 0x28
127:
128:
129: /* PCI Base Address (remap) for Direct Master to PCI IO/Config */
130: #define PLX_DMPBAI 0x2c
131:
132:
133: #define PLX_MAILBOX0 0x40 /* Mailbox register 0 */
134: #define PLX_MAILBOX1 0x44 /* Mailbox register 1 */
135: #define PLX_MAILBOX2 0x48 /* Mailbox register 2 */
136: #define PLX_MAILBOX3 0x4c /* Mailbox register 3 */
137: #define PLX_MAILBOX4 0x50 /* Mailbox register 4 (not 9060ES) */
138: #define PLX_MAILBOX5 0x54 /* Mailbox register 5 (not 9060ES) */
139: #define PLX_MAILBOX6 0x58 /* Mailbox register 6 (not 9060ES) */
140: #define PLX_MAILBOX7 0x5c /* Mailbox register 7 (not 9060ES) */
141:
142:
143: #define PLX_PCI_LOCAL_DOORBELL 0x60 /* PCI -> local doorbell */
144: #define PLX_LOCAL_PCI_DOORBELL 0x64 /* local -> PCI doorbell */
145:
146:
147: /* Interrupt Control/Status */
148: #define PLX_INTCSR 0x68
149: #define INTCSR_LSERR_TAMA 0x00000001
150: #define INTCSR_LSERR_PA 0x00000002
151: #define INTCSR_SERR 0x00000004
152: #define INTCSR_PCI_EN 0x00000100
153: #define INTCSR_PCIDB_EN 0x00000200
154: #define INTCSR_PCIAB_EN 0x00000400
155: #define INTCSR_PCILOC_EN 0x00000800
156: #define INTCSR_RETRYAB_EN 0x00001000
157: #define INTCSR_PCIDB_INT 0x00002000
158: #define INTCSR_PCIAB_INT 0x00004000
159: #define INTCSR_PCILOC_INT 0x00008000
160: #define INTCSR_LOCOE_EN 0x00010000
161: #define INTCSR_LOCDB_EN 0x00020000
162: #define INTCSR_LOCDB_INT 0x00100000
163: #define INTCSR_BIST_INT 0x00800000
164: #define INTCSR_DMAB_INT 0x01000000
165: #define INTCSR_RETRYAB_INT 0x08000000
166:
167:
168: /* EEPROM Control, PCI Command Codes, User I/O Control, Init Control */
169: #define PLX_CONTROL 0x6c
170: #define CONTROL_PCIMRC 0x00000f00
171: #define CONTROL_PCIMRC_SHIFT 8
172: #define CONTROL_PCIMWC 0x0000f000
173: #define CONTROL_PCIMWC_SHIFT 12
174: #define CONTROL_GPO 0x00010000
175: #define CONTROL_GPI 0x00020000
176: #define CONTROL_EESK 0x01000000
177: #define CONTROL_EECS 0x02000000
178: #define CONTROL_EEDO 0x04000000 /* PLX -> EEPROM */
179: #define CONTROL_EEDI 0x08000000 /* EEPROM -> PLX */
180: #define CONTROL_EEPRESENT 0x10000000
181: #define CONTROL_RELOADCFG 0x20000000
182: #define CONTROL_SWR 0x40000000
183: #define CONTROL_LOCALINIT 0x80000000
184:
185: /* EEPROM opcodes */
186: #define PLX_EEPROM_OPC_READ(x) (0x0080 | ((x) & 0x3f))
187: #define PLX_EEPROM_OPC_WRITE(x) (0x0040 | ((x) & 0x3f))
188: #define PLX_EEPROM_OPC_WREN 0x0030
189: #define PLX_EEPROM_OPC_WRPR 0x0000
190: #define PLX_EEPROM_COMMAND(y) (((y) & 0xff) | 0x100)
191:
192:
193: /* PCI Configuration ID */
194: #define PLX_IDREG 0x70
195:
196: #endif /* _DEV_PCI_PLX9060REG_H_ */
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