Return to piixreg.h CVS log

Up to [local] / sys / dev / pci

Annotation of sys/dev/pci/piixreg.h, Revision 1.1.1.1

1.1       nbrk        1: /*     $OpenBSD: piixreg.h,v 1.3 2006/01/03 22:39:03 grange Exp $      */
                      2:
                      3: /*
                      4:  * Copyright (c) 2005 Alexander Yurchenko <grange@openbsd.org>
                      5:  *
                      6:  * Permission to use, copy, modify, and distribute this software for any
                      7:  * purpose with or without fee is hereby granted, provided that the above
                      8:  * copyright notice and this permission notice appear in all copies.
                      9:  *
                     10:  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
                     11:  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
                     12:  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
                     13:  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
                     14:  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
                     15:  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
                     16:  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
                     17:  */
                     18:
                     19: #ifndef _DEV_PCI_PIIXREG_H_
                     20: #define _DEV_PCI_PIIXREG_H_
                     21:
                     22: /*
                     23:  * Intel PCI-to-ISA / IDE Xcelerator (PIIX) register definitions.
                     24:  */
                     25:
                     26: /*
                     27:  * Power management registers.
                     28:  */
                     29:
                     30: /* PCI configuration registers */
                     31: #define PIIX_SMB_BASE  0x90            /* SMBus base address */
                     32: #define PIIX_SMB_HOSTC 0xd0            /* SMBus host configuration */
                     33: #define PIIX_SMB_HOSTC_HSTEN   (1 << 16)       /* enable host controller */
                     34: #define PIIX_SMB_HOSTC_SMI     (0 << 17)       /* SMI */
                     35: #define PIIX_SMB_HOSTC_IRQ     (4 << 17)       /* IRQ */
                     36: #define PIIX_SMB_HOSTC_INTMASK (7 << 17)
                     37:
                     38: /* SMBus I/O registers */
                     39: #define PIIX_SMB_HS    0x00            /* host status */
                     40: #define PIIX_SMB_HS_BUSY       (1 << 0)        /* running a command */
                     41: #define PIIX_SMB_HS_INTR       (1 << 1)        /* command completed */
                     42: #define PIIX_SMB_HS_DEVERR     (1 << 2)        /* command error */
                     43: #define PIIX_SMB_HS_BUSERR     (1 << 3)        /* transaction collision */
                     44: #define PIIX_SMB_HS_FAILED     (1 << 4)        /* failed bus transaction */
                     45: #define PIIX_SMB_HS_BITS       "\020\001BUSY\002INTR\003DEVERR\004BUSERR\005FAILED"
                     46: #define PIIX_SMB_HC    0x02            /* host control */
                     47: #define PIIX_SMB_HC_INTREN     (1 << 0)        /* enable interrupts */
                     48: #define PIIX_SMB_HC_KILL       (1 << 1)        /* kill current transaction */
                     49: #define PIIX_SMB_HC_CMD_QUICK  (0 << 2)        /* QUICK command */
                     50: #define PIIX_SMB_HC_CMD_BYTE   (1 << 2)        /* BYTE command */
                     51: #define PIIX_SMB_HC_CMD_BDATA  (2 << 2)        /* BYTE DATA command */
                     52: #define PIIX_SMB_HC_CMD_WDATA  (3 << 2)        /* WORD DATA command */
                     53: #define PIIX_SMB_HC_CMD_BLOCK  (5 << 2)        /* BLOCK command */
                     54: #define PIIX_SMB_HC_START      (1 << 6)        /* start transaction */
                     55: #define PIIX_SMB_HCMD  0x03            /* host command */
                     56: #define PIIX_SMB_TXSLVA        0x04            /* transmit slave address */
                     57: #define PIIX_SMB_TXSLVA_READ   (1 << 0)        /* read direction */
                     58: #define PIIX_SMB_TXSLVA_ADDR(x)        (((x) & 0x7f) << 1) /* 7-bit address */
                     59: #define PIIX_SMB_HD0   0x05            /* host data 0 */
                     60: #define PIIX_SMB_HD1   0x06            /* host data 1 */
                     61: #define PIIX_SMB_HBDB  0x07            /* host block data byte */
                     62: #define PIIX_SMB_SC    0x08            /* slave control */
                     63: #define PIIX_SMB_SC_ALERTEN    (1 << 3)        /* enable SMBALERT# */
                     64:
                     65: #define PIIX_SMB_SIZE  0x10            /* SMBus I/O space size */
                     66:
                     67: #endif /* !_DEV_PCI_PIIXREG_H_ */