Annotation of sys/dev/pci/pcireg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: pcireg.h,v 1.32 2006/07/31 11:06:33 mickey Exp $ */
! 2: /* $NetBSD: pcireg.h,v 1.26 2000/05/10 16:58:42 thorpej Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved.
! 6: * Copyright (c) 1994, 1996 Charles Hannum. All rights reserved.
! 7: *
! 8: * Redistribution and use in source and binary forms, with or without
! 9: * modification, are permitted provided that the following conditions
! 10: * are met:
! 11: * 1. Redistributions of source code must retain the above copyright
! 12: * notice, this list of conditions and the following disclaimer.
! 13: * 2. Redistributions in binary form must reproduce the above copyright
! 14: * notice, this list of conditions and the following disclaimer in the
! 15: * documentation and/or other materials provided with the distribution.
! 16: * 3. All advertising materials mentioning features or use of this software
! 17: * must display the following acknowledgement:
! 18: * This product includes software developed by Charles Hannum.
! 19: * 4. The name of the author may not be used to endorse or promote products
! 20: * derived from this software without specific prior written permission.
! 21: *
! 22: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 23: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
! 24: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
! 25: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
! 26: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
! 27: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
! 28: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
! 29: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
! 30: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
! 31: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
! 32: */
! 33:
! 34: #ifndef _DEV_PCI_PCIREG_H_
! 35: #define _DEV_PCI_PCIREG_H_
! 36:
! 37: /*
! 38: * Standardized PCI configuration information
! 39: *
! 40: * XXX This is not complete.
! 41: */
! 42:
! 43: /*
! 44: * Device identification register; contains a vendor ID and a device ID.
! 45: */
! 46: #define PCI_ID_REG 0x00
! 47:
! 48: typedef u_int16_t pci_vendor_id_t;
! 49: typedef u_int16_t pci_product_id_t;
! 50:
! 51: #define PCI_VENDOR_SHIFT 0
! 52: #define PCI_VENDOR_MASK 0xffff
! 53: #define PCI_VENDOR(id) \
! 54: (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK)
! 55:
! 56: #define PCI_PRODUCT_SHIFT 16
! 57: #define PCI_PRODUCT_MASK 0xffff
! 58: #define PCI_PRODUCT(id) \
! 59: (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK)
! 60:
! 61: #define PCI_ID_CODE(vid,pid) \
! 62: ((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \
! 63: (((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT))
! 64:
! 65: /*
! 66: * Command and status register.
! 67: */
! 68: #define PCI_COMMAND_STATUS_REG 0x04
! 69:
! 70: #define PCI_COMMAND_IO_ENABLE 0x00000001
! 71: #define PCI_COMMAND_MEM_ENABLE 0x00000002
! 72: #define PCI_COMMAND_MASTER_ENABLE 0x00000004
! 73: #define PCI_COMMAND_SPECIAL_ENABLE 0x00000008
! 74: #define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010
! 75: #define PCI_COMMAND_PALETTE_ENABLE 0x00000020
! 76: #define PCI_COMMAND_PARITY_ENABLE 0x00000040
! 77: #define PCI_COMMAND_STEPPING_ENABLE 0x00000080
! 78: #define PCI_COMMAND_SERR_ENABLE 0x00000100
! 79: #define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200
! 80:
! 81: #define PCI_STATUS_CAPLIST_SUPPORT 0x00100000
! 82: #define PCI_STATUS_66MHZ_SUPPORT 0x00200000
! 83: #define PCI_STATUS_UDF_SUPPORT 0x00400000
! 84: #define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000
! 85: #define PCI_STATUS_PARITY_ERROR 0x01000000
! 86: #define PCI_STATUS_DEVSEL_FAST 0x00000000
! 87: #define PCI_STATUS_DEVSEL_MEDIUM 0x02000000
! 88: #define PCI_STATUS_DEVSEL_SLOW 0x04000000
! 89: #define PCI_STATUS_DEVSEL_MASK 0x06000000
! 90: #define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000
! 91: #define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000
! 92: #define PCI_STATUS_MASTER_ABORT 0x20000000
! 93: #define PCI_STATUS_SPECIAL_ERROR 0x40000000
! 94: #define PCI_STATUS_PARITY_DETECT 0x80000000
! 95:
! 96: #define PCI_COMMAND_STATUS_BITS \
! 97: ("\020\01IO\02MEM\03MASTER\04SPECIAL\05INVALIDATE\06PALETTE\07PARITY"\
! 98: "\010STEPPING\011SERR\012BACKTOBACK\025CAPLIST\026CLK66\027UDF"\
! 99: "\030BACK2BACK_STAT\031PARITY_STAT\032DEVSEL_MEDIUM\033DEVSEL_SLOW"\
! 100: "\034TARGET_TARGET_ABORT\035MASTER_TARGET_ABORT\036MASTER_ABORT"\
! 101: "\037SPECIAL_ERROR\040PARITY_DETECT")
! 102: /*
! 103: * PCI Class and Revision Register; defines type and revision of device.
! 104: */
! 105: #define PCI_CLASS_REG 0x08
! 106:
! 107: typedef u_int8_t pci_class_t;
! 108: typedef u_int8_t pci_subclass_t;
! 109: typedef u_int8_t pci_interface_t;
! 110: typedef u_int8_t pci_revision_t;
! 111:
! 112: #define PCI_CLASS_SHIFT 24
! 113: #define PCI_CLASS_MASK 0xff
! 114: #define PCI_CLASS(cr) \
! 115: (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK)
! 116:
! 117: #define PCI_SUBCLASS_SHIFT 16
! 118: #define PCI_SUBCLASS_MASK 0xff
! 119: #define PCI_SUBCLASS(cr) \
! 120: (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK)
! 121:
! 122: #define PCI_INTERFACE_SHIFT 8
! 123: #define PCI_INTERFACE_MASK 0xff
! 124: #define PCI_INTERFACE(cr) \
! 125: (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK)
! 126:
! 127: #define PCI_REVISION_SHIFT 0
! 128: #define PCI_REVISION_MASK 0xff
! 129: #define PCI_REVISION(cr) \
! 130: (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK)
! 131:
! 132: /* base classes */
! 133: #define PCI_CLASS_PREHISTORIC 0x00
! 134: #define PCI_CLASS_MASS_STORAGE 0x01
! 135: #define PCI_CLASS_NETWORK 0x02
! 136: #define PCI_CLASS_DISPLAY 0x03
! 137: #define PCI_CLASS_MULTIMEDIA 0x04
! 138: #define PCI_CLASS_MEMORY 0x05
! 139: #define PCI_CLASS_BRIDGE 0x06
! 140: #define PCI_CLASS_COMMUNICATIONS 0x07
! 141: #define PCI_CLASS_SYSTEM 0x08
! 142: #define PCI_CLASS_INPUT 0x09
! 143: #define PCI_CLASS_DOCK 0x0a
! 144: #define PCI_CLASS_PROCESSOR 0x0b
! 145: #define PCI_CLASS_SERIALBUS 0x0c
! 146: #define PCI_CLASS_WIRELESS 0x0d
! 147: #define PCI_CLASS_I2O 0x0e
! 148: #define PCI_CLASS_SATCOM 0x0f
! 149: #define PCI_CLASS_CRYPTO 0x10
! 150: #define PCI_CLASS_DASP 0x11
! 151: #define PCI_CLASS_UNDEFINED 0xff
! 152:
! 153: /* 0x00 prehistoric subclasses */
! 154: #define PCI_SUBCLASS_PREHISTORIC_MISC 0x00
! 155: #define PCI_SUBCLASS_PREHISTORIC_VGA 0x01
! 156:
! 157: /* 0x01 mass storage subclasses */
! 158: #define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00
! 159: #define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01
! 160: #define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02
! 161: #define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03
! 162: #define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04
! 163: #define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05
! 164: #define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06
! 165: #define PCI_SUBCLASS_MASS_STORAGE_SAS 0x07
! 166: #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80
! 167:
! 168: /* 0x02 network subclasses */
! 169: #define PCI_SUBCLASS_NETWORK_ETHERNET 0x00
! 170: #define PCI_SUBCLASS_NETWORK_TOKENRING 0x01
! 171: #define PCI_SUBCLASS_NETWORK_FDDI 0x02
! 172: #define PCI_SUBCLASS_NETWORK_ATM 0x03
! 173: #define PCI_SUBCLASS_NETWORK_ISDN 0x04
! 174: #define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05
! 175: #define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06
! 176: #define PCI_SUBCLASS_NETWORK_MISC 0x80
! 177:
! 178: /* 0x03 display subclasses */
! 179: #define PCI_SUBCLASS_DISPLAY_VGA 0x00
! 180: #define PCI_SUBCLASS_DISPLAY_XGA 0x01
! 181: #define PCI_SUBCLASS_DISPLAY_3D 0x02
! 182: #define PCI_SUBCLASS_DISPLAY_MISC 0x80
! 183:
! 184: /* 0x04 multimedia subclasses */
! 185: #define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00
! 186: #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01
! 187: #define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02
! 188: #define PCI_SUBCLASS_MULTIMEDIA_HDAUDIO 0x03
! 189: #define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80
! 190:
! 191: /* 0x05 memory subclasses */
! 192: #define PCI_SUBCLASS_MEMORY_RAM 0x00
! 193: #define PCI_SUBCLASS_MEMORY_FLASH 0x01
! 194: #define PCI_SUBCLASS_MEMORY_MISC 0x80
! 195:
! 196: /* 0x06 bridge subclasses */
! 197: #define PCI_SUBCLASS_BRIDGE_HOST 0x00
! 198: #define PCI_SUBCLASS_BRIDGE_ISA 0x01
! 199: #define PCI_SUBCLASS_BRIDGE_EISA 0x02
! 200: #define PCI_SUBCLASS_BRIDGE_MC 0x03
! 201: #define PCI_SUBCLASS_BRIDGE_PCI 0x04
! 202: #define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05
! 203: #define PCI_SUBCLASS_BRIDGE_NUBUS 0x06
! 204: #define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07
! 205: #define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08
! 206: #define PCI_SUBCLASS_BRIDGE_STPCI 0x09
! 207: #define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a
! 208: #define PCI_SUBCLASS_BRIDGE_MISC 0x80
! 209:
! 210: /* 0x07 communications subclasses */
! 211: #define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00
! 212: #define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01
! 213: #define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02
! 214: #define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03
! 215: #define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04
! 216: #define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05
! 217: #define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80
! 218:
! 219: /* 0x08 system subclasses */
! 220: #define PCI_SUBCLASS_SYSTEM_PIC 0x00
! 221: #define PCI_SUBCLASS_SYSTEM_DMA 0x01
! 222: #define PCI_SUBCLASS_SYSTEM_TIMER 0x02
! 223: #define PCI_SUBCLASS_SYSTEM_RTC 0x03
! 224: #define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04
! 225: #define PCI_SUBCLASS_SYSTEM_SDHC 0x05
! 226: #define PCI_SUBCLASS_SYSTEM_MISC 0x80
! 227:
! 228: /* 0x09 input subclasses */
! 229: #define PCI_SUBCLASS_INPUT_KEYBOARD 0x00
! 230: #define PCI_SUBCLASS_INPUT_DIGITIZER 0x01
! 231: #define PCI_SUBCLASS_INPUT_MOUSE 0x02
! 232: #define PCI_SUBCLASS_INPUT_SCANNER 0x03
! 233: #define PCI_SUBCLASS_INPUT_GAMEPORT 0x04
! 234: #define PCI_SUBCLASS_INPUT_MISC 0x80
! 235:
! 236: /* 0x0a dock subclasses */
! 237: #define PCI_SUBCLASS_DOCK_GENERIC 0x00
! 238: #define PCI_SUBCLASS_DOCK_MISC 0x80
! 239:
! 240: /* 0x0b processor subclasses */
! 241: #define PCI_SUBCLASS_PROCESSOR_386 0x00
! 242: #define PCI_SUBCLASS_PROCESSOR_486 0x01
! 243: #define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02
! 244: #define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10
! 245: #define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20
! 246: #define PCI_SUBCLASS_PROCESSOR_MIPS 0x30
! 247: #define PCI_SUBCLASS_PROCESSOR_COPROC 0x40
! 248:
! 249: /* 0x0c serial bus subclasses */
! 250: #define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00
! 251: #define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01
! 252: #define PCI_SUBCLASS_SERIALBUS_SSA 0x02
! 253: #define PCI_SUBCLASS_SERIALBUS_USB 0x03
! 254: #define PCI_SUBCLASS_SERIALBUS_FIBER 0x04
! 255: #define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05
! 256: #define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06
! 257: #define PCI_SUBCLASS_SERIALBUS_IPMI 0x07
! 258: #define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08
! 259: #define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09
! 260:
! 261: /* 0x0d wireless subclasses */
! 262: #define PCI_SUBCLASS_WIRELESS_IRDA 0x00
! 263: #define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01
! 264: #define PCI_SUBCLASS_WIRELESS_RF 0x10
! 265: #define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11
! 266: #define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12
! 267: #define PCI_SUBCLASS_WIRELESS_802_11A 0x20
! 268: #define PCI_SUBCLASS_WIRELESS_802_11B 0x21
! 269: #define PCI_SUBCLASS_WIRELESS_MISC 0x80
! 270:
! 271: /* 0x0e I2O (Intelligent I/O) subclasses */
! 272: #define PCI_SUBCLASS_I2O_STANDARD 0x00
! 273:
! 274: /* 0x0f satellite communication subclasses */
! 275: /* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */
! 276: #define PCI_SUBCLASS_SATCOM_TV 0x01
! 277: #define PCI_SUBCLASS_SATCOM_AUDIO 0x02
! 278: #define PCI_SUBCLASS_SATCOM_VOICE 0x03
! 279: #define PCI_SUBCLASS_SATCOM_DATA 0x04
! 280:
! 281: /* 0x10 encryption/decryption subclasses */
! 282: #define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00
! 283: #define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10
! 284: #define PCI_SUBCLASS_CRYPTO_MISC 0x80
! 285:
! 286: /* 0x11 data acquisition and signal processing subclasses */
! 287: #define PCI_SUBCLASS_DASP_DPIO 0x00
! 288: #define PCI_SUBCLASS_DASP_TIMEFREQ 0x01
! 289: #define PCI_SUBCLASS_DASP_SYNC 0x10
! 290: #define PCI_SUBCLASS_DASP_MGMT 0x20
! 291: #define PCI_SUBCLASS_DASP_MISC 0x80
! 292:
! 293: /*
! 294: * PCI BIST/Header Type/Latency Timer/Cache Line Size Register.
! 295: */
! 296: #define PCI_BHLC_REG 0x0c
! 297:
! 298: #define PCI_BIST_SHIFT 24
! 299: #define PCI_BIST_MASK 0xff
! 300: #define PCI_BIST(bhlcr) \
! 301: (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK)
! 302:
! 303: #define PCI_HDRTYPE_SHIFT 16
! 304: #define PCI_HDRTYPE_MASK 0xff
! 305: #define PCI_HDRTYPE(bhlcr) \
! 306: (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK)
! 307:
! 308: #define PCI_HDRTYPE_TYPE(bhlcr) \
! 309: (PCI_HDRTYPE(bhlcr) & 0x7f)
! 310: #define PCI_HDRTYPE_MULTIFN(bhlcr) \
! 311: ((PCI_HDRTYPE(bhlcr) & 0x80) != 0)
! 312:
! 313: #define PCI_LATTIMER_SHIFT 8
! 314: #define PCI_LATTIMER_MASK 0xff
! 315: #define PCI_LATTIMER(bhlcr) \
! 316: (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK)
! 317:
! 318: #define PCI_CACHELINE_SHIFT 0
! 319: #define PCI_CACHELINE_MASK 0xff
! 320: #define PCI_CACHELINE(bhlcr) \
! 321: (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK)
! 322:
! 323: /* config registers for header type 0 devices */
! 324:
! 325: #define PCI_MAPS 0x10
! 326: #define PCI_CARDBUSCIS 0x28
! 327: #define PCI_SUBVEND_0 0x2c
! 328: #define PCI_SUBDEV_0 0x2e
! 329: #define PCI_INTLINE 0x3c
! 330: #define PCI_INTPIN 0x3d
! 331: #define PCI_MINGNT 0x3e
! 332: #define PCI_MAXLAT 0x3f
! 333:
! 334: /* config registers for header type 1 devices */
! 335:
! 336: #define PCI_SECSTAT_1 0 /**/
! 337:
! 338: #define PCI_PRIBUS_1 0x18
! 339: #define PCI_SECBUS_1 0x19
! 340: #define PCI_SUBBUS_1 0x1a
! 341: #define PCI_SECLAT_1 0x1b
! 342:
! 343: #define PCI_IOBASEL_1 0x1c
! 344: #define PCI_IOLIMITL_1 0x1d
! 345: #define PCI_IOBASEH_1 0 /**/
! 346: #define PCI_IOLIMITH_1 0 /**/
! 347:
! 348: #define PCI_MEMBASE_1 0x20
! 349: #define PCI_MEMLIMIT_1 0x22
! 350:
! 351: #define PCI_PMBASEL_1 0x24
! 352: #define PCI_PMLIMITL_1 0x26
! 353: #define PCI_PMBASEH_1 0 /**/
! 354: #define PCI_PMLIMITH_1 0 /**/
! 355:
! 356: #define PCI_BRIDGECTL_1 0 /**/
! 357:
! 358: #define PCI_SUBVEND_1 0x34
! 359: #define PCI_SUBDEV_1 0x36
! 360:
! 361: /* config registers for header type 2 devices */
! 362:
! 363: #define PCI_SECSTAT_2 0x16
! 364:
! 365: #define PCI_PRIBUS_2 0x18
! 366: #define PCI_SECBUS_2 0x19
! 367: #define PCI_SUBBUS_2 0x1a
! 368: #define PCI_SECLAT_2 0x1b
! 369:
! 370: #define PCI_MEMBASE0_2 0x1c
! 371: #define PCI_MEMLIMIT0_2 0x20
! 372: #define PCI_MEMBASE1_2 0x24
! 373: #define PCI_MEMLIMIT1_2 0x28
! 374: #define PCI_IOBASE0_2 0x2c
! 375: #define PCI_IOLIMIT0_2 0x30
! 376: #define PCI_IOBASE1_2 0x34
! 377: #define PCI_IOLIMIT1_2 0x38
! 378:
! 379: #define PCI_BRIDGECTL_2 0x3e
! 380:
! 381: #define PCI_SUBVEND_2 0x40
! 382: #define PCI_SUBDEV_2 0x42
! 383:
! 384: #define PCI_PCCARDIF_2 0x44
! 385:
! 386: /*
! 387: * Mapping registers
! 388: */
! 389: #define PCI_MAPREG_START 0x10
! 390: #define PCI_MAPREG_END 0x28
! 391: #define PCI_MAPREG_PPB_END 0x18
! 392: #define PCI_MAPREG_PCB_END 0x14
! 393:
! 394: #define PCI_MAPREG_TYPE(mr) \
! 395: ((mr) & PCI_MAPREG_TYPE_MASK)
! 396: #define PCI_MAPREG_TYPE_MASK 0x00000001
! 397:
! 398: #define PCI_MAPREG_TYPE_MEM 0x00000000
! 399: #define PCI_MAPREG_TYPE_IO 0x00000001
! 400:
! 401: #define PCI_MAPREG_MEM_TYPE(mr) \
! 402: ((mr) & PCI_MAPREG_MEM_TYPE_MASK)
! 403: #define PCI_MAPREG_MEM_TYPE_MASK 0x00000006
! 404:
! 405: #define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000
! 406: #define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002
! 407: #define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004
! 408:
! 409: #define _PCI_MAPREG_TYPEBITS(reg) \
! 410: (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO ? \
! 411: reg & PCI_MAPREG_TYPE_MASK : \
! 412: reg & (PCI_MAPREG_TYPE_MASK|PCI_MAPREG_MEM_TYPE_MASK))
! 413:
! 414: #define PCI_MAPREG_MEM_PREFETCHABLE(mr) \
! 415: (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0)
! 416: #define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008
! 417:
! 418: #define PCI_MAPREG_MEM_ADDR(mr) \
! 419: ((mr) & PCI_MAPREG_MEM_ADDR_MASK)
! 420: #define PCI_MAPREG_MEM_SIZE(mr) \
! 421: (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr))
! 422: #define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0
! 423:
! 424: #define PCI_MAPREG_MEM64_ADDR(mr) \
! 425: ((mr) & PCI_MAPREG_MEM64_ADDR_MASK)
! 426: #define PCI_MAPREG_MEM64_SIZE(mr) \
! 427: (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr))
! 428: #define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL
! 429:
! 430: #define PCI_MAPREG_IO_ADDR(mr) \
! 431: ((mr) & PCI_MAPREG_IO_ADDR_MASK)
! 432: #define PCI_MAPREG_IO_SIZE(mr) \
! 433: (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr))
! 434: #define PCI_MAPREG_IO_ADDR_MASK 0xfffffffe
! 435:
! 436: /*
! 437: * Cardbus CIS pointer (PCI rev. 2.1)
! 438: */
! 439: #define PCI_CARDBUS_CIS_REG 0x28
! 440:
! 441: /*
! 442: * Subsystem identification register; contains a vendor ID and a device ID.
! 443: * Types/macros for PCI_ID_REG apply.
! 444: * (PCI rev. 2.1)
! 445: */
! 446: #define PCI_SUBSYS_ID_REG 0x2c
! 447:
! 448: /*
! 449: * Expansion ROM Base Address register
! 450: * (PCI rev. 2.0)
! 451: */
! 452: #define PCI_ROM_REG 0x30
! 453:
! 454: #define PCI_ROM_ENABLE 0x00000001
! 455: #define PCI_ROM_ADDR_MASK 0xfffff800
! 456: #define PCI_ROM_ADDR(mr) \
! 457: ((mr) & PCI_ROM_ADDR_MASK)
! 458: #define PCI_ROM_SIZE(mr) \
! 459: (PCI_ROM_ADDR(mr) & -PCI_ROM_ADDR(mr))
! 460:
! 461: /*
! 462: * capabilities link list (PCI rev. 2.2)
! 463: */
! 464: #define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */
! 465: #define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */
! 466: #define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff)
! 467: #define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff)
! 468: #define PCI_CAPLIST_CAP(cr) ((cr) & 0xff)
! 469:
! 470: #define PCI_CAP_RESERVED 0x00
! 471: #define PCI_CAP_PWRMGMT 0x01
! 472: #define PCI_CAP_AGP 0x02
! 473: #define PCI_CAP_VPD 0x03
! 474: #define PCI_CAP_SLOTID 0x04
! 475: #define PCI_CAP_MSI 0x05
! 476: #define PCI_CAP_CPCI_HOTSWAP 0x06
! 477: #define PCI_CAP_PCIX 0x07
! 478: #define PCI_CAP_LDT 0x08
! 479: #define PCI_CAP_VENDSPEC 0x09
! 480: #define PCI_CAP_DEBUGPORT 0x0a
! 481: #define PCI_CAP_CPCI_RSRCCTL 0x0b
! 482: #define PCI_CAP_HOTPLUG 0x0c
! 483: #define PCI_CAP_AGP8 0x0e
! 484: #define PCI_CAP_SECURE 0x0f
! 485: #define PCI_CAP_PCIEXPRESS 0x10
! 486: #define PCI_CAP_MSIX 0x11
! 487:
! 488: /*
! 489: * Power Management Control Status Register; access via capability pointer.
! 490: */
! 491: #define PCI_PMCSR 0x04
! 492: #define PCI_PMCSR_STATE_MASK 0x03
! 493: #define PCI_PMCSR_STATE_D0 0x00
! 494: #define PCI_PMCSR_STATE_D1 0x01
! 495: #define PCI_PMCSR_STATE_D2 0x02
! 496: #define PCI_PMCSR_STATE_D3 0x03
! 497:
! 498: /*
! 499: * Interrupt Configuration Register; contains interrupt pin and line.
! 500: */
! 501: #define PCI_INTERRUPT_REG 0x3c
! 502:
! 503: typedef u_int8_t pci_intr_pin_t;
! 504: typedef u_int8_t pci_intr_line_t;
! 505:
! 506: #define PCI_INTERRUPT_PIN_SHIFT 8
! 507: #define PCI_INTERRUPT_PIN_MASK 0xff
! 508: #define PCI_INTERRUPT_PIN(icr) \
! 509: (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK)
! 510:
! 511: #define PCI_INTERRUPT_LINE_SHIFT 0
! 512: #define PCI_INTERRUPT_LINE_MASK 0xff
! 513: #define PCI_INTERRUPT_LINE(icr) \
! 514: (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK)
! 515:
! 516: #define PCI_MIN_GNT_SHIFT 16
! 517: #define PCI_MIN_GNT_MASK 0xff
! 518: #define PCI_MIN_GNT(icr) \
! 519: (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK)
! 520:
! 521: #define PCI_MAX_LAT_SHIFT 24
! 522: #define PCI_MAX_LAT_MASK 0xff
! 523: #define PCI_MAX_LAT(icr) \
! 524: (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK)
! 525:
! 526: #define PCI_INTERRUPT_PIN_NONE 0x00
! 527: #define PCI_INTERRUPT_PIN_A 0x01
! 528: #define PCI_INTERRUPT_PIN_B 0x02
! 529: #define PCI_INTERRUPT_PIN_C 0x03
! 530: #define PCI_INTERRUPT_PIN_D 0x04
! 531: #define PCI_INTERRUPT_PIN_MAX 0x04
! 532:
! 533: /*
! 534: * Vital Product Data resource tags.
! 535: */
! 536: struct pci_vpd_smallres {
! 537: uint8_t vpdres_byte0; /* length of data + tag */
! 538: /* Actual data. */
! 539: } __packed;
! 540:
! 541: struct pci_vpd_largeres {
! 542: uint8_t vpdres_byte0;
! 543: uint8_t vpdres_len_lsb; /* length of data only */
! 544: uint8_t vpdres_len_msb;
! 545: /* Actual data. */
! 546: } __packed;
! 547:
! 548: #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80)
! 549:
! 550: #define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7)
! 551: #define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf)
! 552:
! 553: #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f)
! 554:
! 555: #define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */
! 556: #define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */
! 557: #define PCI_VPDRES_TYPE_END_TAG 0xf /* small */
! 558:
! 559: #define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */
! 560: #define PCI_VPDRES_TYPE_VPD 0x10 /* large */
! 561:
! 562: struct pci_vpd {
! 563: uint8_t vpd_key0;
! 564: uint8_t vpd_key1;
! 565: uint8_t vpd_len; /* length of data only */
! 566: /* Actual data. */
! 567: } __packed;
! 568:
! 569: /*
! 570: * Recommended VPD fields:
! 571: *
! 572: * PN Part number of assembly
! 573: * FN FRU part number
! 574: * EC EC level of assembly
! 575: * MN Manufacture ID
! 576: * SN Serial Number
! 577: *
! 578: * Conditionally recommended VPD fields:
! 579: *
! 580: * LI Load ID
! 581: * RL ROM Level
! 582: * RM Alterable ROM Level
! 583: * NA Network Address
! 584: * DD Device Driver Level
! 585: * DG Diagnostic Level
! 586: * LL Loadable Microcode Level
! 587: * VI Vendor ID/Device ID
! 588: * FU Function Number
! 589: * SI Subsystem Vendor ID/Subsystem ID
! 590: *
! 591: * Additional VPD fields:
! 592: *
! 593: * Z0-ZZ User/Product Specific
! 594: */
! 595:
! 596: #endif /* _DEV_PCI_PCIREG_H_ */
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