Annotation of sys/dev/pci/pciide_sis_reg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: pciide_sis_reg.h,v 1.7 2004/10/17 18:16:12 grange Exp $ */
2: /* $NetBSD: pciide_sis_reg.h,v 1.6 2000/05/15 08:46:01 bouyer Exp $ */
3:
4: /*
5: * Copyright (c) 1998 Manuel Bouyer.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: * 3. All advertising materials mentioning features or use of this software
16: * must display the following acknowledgement:
17: * This product includes software developed by Manuel Bouyer.
18: * 4. Neither the name of the University nor the names of its contributors
19: * may be used to endorse or promote products derived from this software
20: * without specific prior written permission.
21: *
22: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32: *
33: */
34:
35: #ifndef _DEV_PCI_PCIIDE_SIS_REG_H_
36: #define _DEV_PCI_PCIIDE_SIS_REG_H_
37:
38: /*
39: * Registers definitions for SiS SiS5597/98 PCI IDE controller.
40: * Available from http://www.sis.com.tw/html/databook.html
41: */
42:
43: /* IDE timing control registers (32 bits), for all but 96x */
44: #define SIS_TIM(channel) (0x40 + (channel * 4))
45: /* for 730, 630 and older (66, 100OLD) */
46: #define SIS_TIM66_REC_OFF(drive) (16 * (drive))
47: #define SIS_TIM66_ACT_OFF(drive) (8 + 16 * (drive))
48: #define SIS_TIM66_UDMA_TIME_OFF(drive) (12 + 16 * (drive))
49: /* for older than 96x (100NEW, 133OLD) */
50: #define SIS_TIM100_REC_OFF(drive) (16 * (drive))
51: #define SIS_TIM100_ACT_OFF(drive) (4 + 16 * (drive))
52: #define SIS_TIM100_UDMA_TIME_OFF(drive) (8 + 16 * (drive))
53:
54: /*
55: * From FreeBSD: on 96x, the timing registers may start from 0x40 or 0x70
56: * depending on the value from register 0x57. 32bits of timing info for
57: * each drive.
58: */
59: #define SIS_TIM133(reg57, channel, drive) \
60: ((((reg57) & 0x40) ? 0x70 : 0x40) + ((channel) << 3) + ((drive) << 2))
61:
62: /* IDE general control register 0 (8 bits) */
63: #define SIS_CTRL0 0x4a
64: #define SIS_CTRL0_PCIBURST 0x80
65: #define SIS_CTRL0_FAST_PW 0x20
66: #define SIS_CTRL0_BO 0x08
67: #define SIS_CTRL0_CHAN0_EN 0x02 /* manual (v2.0) is wrong!!! */
68: #define SIS_CTRL0_CHAN1_EN 0x04 /* manual (v2.0) is wrong!!! */
69:
70: /* IDE general control register 1 (8 bits) */
71: #define SIS_CTRL1 0x4b
72: #define SIS_CTRL1_POSTW_EN(chan, drv) (0x10 << ((drv) + 2 * (chan)))
73: #define SIS_CTRL1_PREFETCH_EN(chan, drv) (0x01 << ((drv) + 2 * (chan)))
74:
75: /* IDE misc control register (8 bit) */
76: #define SIS_MISC 0x52
77: #define SIS_MISC_TIM_SEL 0x08
78: #define SIS_MISC_GTC 0x04
79: #define SIS_MISC_FIFO_SIZE 0x01
80:
81: /* following are from FreeBSD (sorry, no description) */
82: #define SIS_REG_49 0x49
83: #define SIS_REG_50 0x50
84: #define SIS_REG_51 0x51
85: #define SIS_REG_52 0x52
86: #define SIS_REG_53 0x53
87: #define SIS_REG_57 0x57
88:
89: #define SIS_REG_CBL 0x48
90: #define SIS_REG_CBL_33(channel) (0x10 << (channel))
91: #define SIS96x_REG_CBL(channel) (0x51 + (channel) * 2)
92: #define SIS96x_REG_CBL_33 0x80
93:
94: #define SIS_PRODUCT_5518 0x5518
95:
96: /* Private data */
97: struct pciide_sis {
98: u_int8_t sis_type;
99: };
100:
101: /* timings values, mostly from FreeBSD */
102: /* PIO timings, for all up to 133NEW */
103: static const u_int8_t sis_pio_act[] =
104: {12, 6, 4, 3, 3};
105: static const u_int8_t sis_pio_rec[] =
106: {11, 7, 4, 3, 1};
107: /* DMA timings for 66 and 100OLD */
108: static const u_int8_t sis_udma66_tim[] =
109: {15, 13, 11, 10, 9, 8};
110: /* DMA timings for 100NEW */
111: static const u_int8_t sis_udma100new_tim[] =
112: {0x8b, 0x87, 0x85, 0x84, 0x82, 0x81};
113: /* DMA timings for 133OLD */
114: static const u_int8_t sis_udma133old_tim[] =
115: {0x8f, 0x8a, 0x87, 0x85, 0x83, 0x82, 0x81};
116: /* PIO, DMA and UDMA timings for 133NEW */
117: static const u_int32_t sis_pio133new_tim[] =
118: {0x28269008, 0x0c266008, 0x4263008, 0x0c0a3008, 0x05093008};
119: static const u_int32_t sis_dma133new_tim[] =
120: {0x22196008, 0x0c0a3008, 0x05093008};
121: static const u_int32_t sis_udma133new_tim[] =
122: {0x9f4, 0x64a, 0x474, 0x254, 0x234, 0x224, 0x214};
123:
124: #endif /* !_DEV_PCI_PCIIDE_SIS_REG_H_ */
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