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1.1 nbrk 1: /* $OpenBSD: pciide_sii3112_reg.h,v 1.5 2006/02/10 21:45:41 kettenis Exp $ */
2: /* $NetBSD: pciide_sii3112_reg.h,v 1.1 2003/03/20 04:22:50 thorpej Exp $ */
3:
4: /*
5: * Copyright (c) 2003 Wasabi Systems, Inc.
6: * All rights reserved.
7: *
8: * Written by Jason R. Thorpe for Wasabi Systems, Inc.
9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: * 3. All advertising materials mentioning features or use of this software
19: * must display the following acknowledgement:
20: * This product includes software developed for the NetBSD Project by
21: * Wasabi Systems, Inc.
22: * 4. The name of Wasabi Systems, Inc. may not be used to endorse
23: * or promote products derived from this software without specific prior
24: * written permission.
25: *
26: * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
27: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
30: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36: * POSSIBILITY OF SUCH DAMAGE.
37: */
38:
39: #ifndef _DEV_PCI_PCIIDE_SII3112_REG_H_
40: #define _DEV_PCI_PCIIDE_SII3112_REG_H_
41:
42: /*
43: * PCI configuration space registers.
44: */
45:
46: #define SII3112_PCI_CFGCTL 0x40
47: #define CFGCTL_CFGWREN (1U << 0) /* enable cfg writes */
48: #define CFGCTL_BA5INDEN (1U << 1) /* BA5 indirect access enable */
49:
50: #define SII3112_PCI_SWDATA 0x44
51:
52: #define SII3112_PCI_BM_IDE0 0x70
53: /* == BAR4+0x00 */
54:
55: #define SII3112_PCI_PRD_IDE0 0x74
56: /* == BAR4+0x04 */
57:
58: #define SII3112_PCI_BM_IDE1 0x78
59: /* == BAR4+0x08 */
60:
61: #define SII3112_PCI_PRD_IDE1 0x7c
62: /* == BAR4+0x0c */
63:
64: #define SII3112_DTM_IDE0 0x80 /* Data Transfer Mode - IDE0 */
65: #define SII3112_DTM_IDE1 0x84 /* Data Transfer Mode - IDE1 */
66: #define DTM_IDEx_PIO 0x00000000 /* PCI DMA, IDE PIO (or 1) */
67: #define DTM_IDEx_DMA 0x00000002 /* PCI DMA, IDE DMA (or 3) */
68:
69:
70: #define SII3112_SCS_CMD 0x88 /* System Config Status */
71: #define SCS_CMD_PBM_RESET (1U << 0) /* PBM module reset */
72: #define SCS_CMD_ARB_RESET (1U << 1) /* ARB module reset */
73: #define SCS_CMD_FF1_RESET (1U << 4) /* IDE1 FIFO reset */
74: #define SCS_CMD_FF0_RESET (1U << 5) /* IDE0 FIFO reset */
75: #define SCS_CMD_IDE1_RESET (1U << 6) /* IDE1 module reset */
76: #define SCS_CMD_IDE0_RESET (1U << 7) /* IDE0 module reset */
77: #define SCS_CMD_FF3_RESET (1U << 8) /* IDE3 FIFO reset (3114) */
78: #define SCS_CMD_FF2_RESET (1U << 9) /* IDE2 FIFO reset (3114) */
79: #define SCS_CMD_IDE3_RESET (1U << 10) /* IDE3 module reset (3114) */
80: #define SCS_CMD_IDE2_RESET (1U << 11) /* IDE2 module reset (3114) */
81: #define SCS_CMD_BA5_EN (1U << 16) /* BA5 is enabled (3112) */
82: #define SCS_CMD_M66EN (1U << 16) /* 1=66MHz, 0=33MHz (3114) */
83: #define SCS_CMD_IDE0_INT_BLOCK (1U << 22) /* IDE0 interrupt block */
84: #define SCS_CMD_IDE1_INT_BLOCK (1U << 23) /* IDE1 interrupt block */
85: #define SCS_CMD_IDE2_INT_BLOCK (1U << 24) /* IDE2 interrupt block */
86: #define SCS_CMD_IDE3_INT_BLOCK (1U << 25) /* IDE3 interrupt block */
87:
88: #define SII3112_SSDR 0x8c /* System SW Data Register */
89:
90: #define SII3112_FMA_CSR 0x90 /* Flash Memory Addr - CSR */
91:
92: #define SII3112_FM_DATA 0x94 /* Flash Memory Data */
93:
94: #define SII3112_EEA_CSR 0x98 /* EEPROM Memory Addr - CSR */
95:
96: #define SII3112_EE_DATA 0x9c /* EEPROM Data */
97:
98: #define SII3112_TCS_IDE0 0xa0 /* IDEx config, status */
99: #define SII3112_TCS_IDE1 0xb0
100: #define TCS_IDEx_BCA (1U << 1) /* buffered command active */
101: #define TCS_IDEx_CH_RESET (1U << 2) /* channel reset */
102: #define TCS_IDEx_VDMA_INT (1U << 10) /* virtual DMA interrupt */
103: #define TCS_IDEx_INT (1U << 11) /* interrupt status */
104: #define TCS_IDEx_WTT (1U << 12) /* watchdog timer timeout */
105: #define TCS_IDEx_WTEN (1U << 13) /* watchdog timer enable */
106: #define TCS_IDEx_WTINTEN (1U << 14) /* watchdog timer int. enable */
107:
108: #define SII3112_BA5_IND_ADDR 0xc0 /* BA5 indirect address */
109:
110: #define SII3112_BA5_IND_DATA 0xc4 /* BA5 indirect data */
111:
112: /*
113: * Register map for BA5 register space, indexed by channel.
114: */
115: static const struct {
116: bus_addr_t ba5_IDEDMA_CMD;
117: bus_addr_t ba5_IDEDMA_CTL;
118: bus_addr_t ba5_IDEDMA_TBL;
119: bus_addr_t ba5_IDEDMA_CMD2;
120: bus_addr_t ba5_IDEDMA_CTL2;
121: bus_addr_t ba5_IDE_TF0;
122: bus_addr_t ba5_IDE_TF1;
123: bus_addr_t ba5_IDE_TF2;
124: bus_addr_t ba5_IDE_TF3;
125: bus_addr_t ba5_IDE_TF4;
126: bus_addr_t ba5_IDE_TF5;
127: bus_addr_t ba5_IDE_TF6;
128: bus_addr_t ba5_IDE_TF7;
129: bus_addr_t ba5_IDE_TF8;
130: bus_addr_t ba5_IDE_RAD;
131: bus_addr_t ba5_IDE_TF9;
132: bus_addr_t ba5_IDE_TF10;
133: bus_addr_t ba5_IDE_TF11;
134: bus_addr_t ba5_IDE_TF12;
135: bus_addr_t ba5_IDE_TF13;
136: bus_addr_t ba5_IDE_TF14;
137: bus_addr_t ba5_IDE_TF15;
138: bus_addr_t ba5_IDE_TF16;
139: bus_addr_t ba5_IDE_TF17;
140: bus_addr_t ba5_IDE_TF18;
141: bus_addr_t ba5_IDE_TF19;
142: bus_addr_t ba5_IDE_RABC;
143: bus_addr_t ba5_IDE_CMD_STS;
144: bus_addr_t ba5_IDE_CFG_STS;
145: bus_addr_t ba5_IDE_DTM;
146: bus_addr_t ba5_SControl;
147: bus_addr_t ba5_SStatus;
148: bus_addr_t ba5_SError;
149: bus_addr_t ba5_SActive; /* 3114 */
150: bus_addr_t ba5_SMisc;
151: bus_addr_t ba5_PHY_CONFIG;
152: bus_addr_t ba5_SIEN;
153: bus_addr_t ba5_SFISCfg;
154: } satalink_ba5_regmap[] = {
155: { /* Channel 0 */
156: .ba5_IDEDMA_CMD = 0x000,
157: .ba5_IDEDMA_CTL = 0x002,
158: .ba5_IDEDMA_TBL = 0x004,
159: .ba5_IDEDMA_CMD2 = 0x010,
160: .ba5_IDEDMA_CTL2 = 0x012,
161: .ba5_IDE_TF0 = 0x080, /* wd_data */
162: .ba5_IDE_TF1 = 0x081, /* wd_error */
163: .ba5_IDE_TF2 = 0x082, /* wd_seccnt */
164: .ba5_IDE_TF3 = 0x083, /* wd_sector */
165: .ba5_IDE_TF4 = 0x084, /* wd_cyl_lo */
166: .ba5_IDE_TF5 = 0x085, /* wd_cyl_hi */
167: .ba5_IDE_TF6 = 0x086, /* wd_sdh */
168: .ba5_IDE_TF7 = 0x087, /* wd_command */
169: .ba5_IDE_TF8 = 0x08a, /* wd_altsts */
170: .ba5_IDE_RAD = 0x08c,
171: .ba5_IDE_TF9 = 0x091, /* Features 2 */
172: .ba5_IDE_TF10 = 0x092, /* Sector Count 2 */
173: .ba5_IDE_TF11 = 0x093, /* Start Sector 2 */
174: .ba5_IDE_TF12 = 0x094, /* Cylinder Low 2 */
175: .ba5_IDE_TF13 = 0x095, /* Cylinder High 2 */
176: .ba5_IDE_TF14 = 0x096, /* Device/Head 2 */
177: .ba5_IDE_TF15 = 0x097, /* Cmd Sts 2 */
178: .ba5_IDE_TF16 = 0x098, /* Sector Count 2 ext */
179: .ba5_IDE_TF17 = 0x099, /* Start Sector 2 ext */
180: .ba5_IDE_TF18 = 0x09a, /* Cyl Low 2 ext */
181: .ba5_IDE_TF19 = 0x09b, /* Cyl High 2 ext */
182: .ba5_IDE_RABC = 0x09c,
183: .ba5_IDE_CMD_STS = 0x0a0,
184: .ba5_IDE_CFG_STS = 0x0a1,
185: .ba5_IDE_DTM = 0x0b4,
186: .ba5_SControl = 0x100,
187: .ba5_SStatus = 0x104,
188: .ba5_SError = 0x108,
189: .ba5_SActive = 0x10c,
190: .ba5_SMisc = 0x140,
191: .ba5_PHY_CONFIG = 0x144,
192: .ba5_SIEN = 0x148,
193: .ba5_SFISCfg = 0x14c,
194: },
195: { /* Channel 1 */
196: .ba5_IDEDMA_CMD = 0x008,
197: .ba5_IDEDMA_CTL = 0x00a,
198: .ba5_IDEDMA_TBL = 0x00c,
199: .ba5_IDEDMA_CMD2 = 0x018,
200: .ba5_IDEDMA_CTL2 = 0x01a,
201: .ba5_IDE_TF0 = 0x0c0, /* wd_data */
202: .ba5_IDE_TF1 = 0x0c1, /* wd_error */
203: .ba5_IDE_TF2 = 0x0c2, /* wd_seccnt */
204: .ba5_IDE_TF3 = 0x0c3, /* wd_sector */
205: .ba5_IDE_TF4 = 0x0c4, /* wd_cyl_lo */
206: .ba5_IDE_TF5 = 0x0c5, /* wd_cyl_hi */
207: .ba5_IDE_TF6 = 0x0c6, /* wd_sdh */
208: .ba5_IDE_TF7 = 0x0c7, /* wd_command */
209: .ba5_IDE_TF8 = 0x0ca, /* wd_altsts */
210: .ba5_IDE_RAD = 0x0cc,
211: .ba5_IDE_TF9 = 0x0d1, /* Features 2 */
212: .ba5_IDE_TF10 = 0x0d2, /* Sector Count 2 */
213: .ba5_IDE_TF11 = 0x0d3, /* Start Sector 2 */
214: .ba5_IDE_TF12 = 0x0d4, /* Cylinder Low 2 */
215: .ba5_IDE_TF13 = 0x0d5, /* Cylinder High 2 */
216: .ba5_IDE_TF14 = 0x0d6, /* Device/Head 2 */
217: .ba5_IDE_TF15 = 0x0d7, /* Cmd Sts 2 */
218: .ba5_IDE_TF16 = 0x0d8, /* Sector Count 2 ext */
219: .ba5_IDE_TF17 = 0x0d9, /* Start Sector 2 ext */
220: .ba5_IDE_TF18 = 0x0da, /* Cyl Low 2 ext */
221: .ba5_IDE_TF19 = 0x0db, /* Cyl High 2 ext */
222: .ba5_IDE_RABC = 0x0dc,
223: .ba5_IDE_CMD_STS = 0x0e0,
224: .ba5_IDE_CFG_STS = 0x0e1,
225: .ba5_IDE_DTM = 0x0f4,
226: .ba5_SControl = 0x180,
227: .ba5_SStatus = 0x184,
228: .ba5_SError = 0x188,
229: .ba5_SActive = 0x18c,
230: .ba5_SMisc = 0x1c0,
231: .ba5_PHY_CONFIG = 0x1c4,
232: .ba5_SIEN = 0x1c8,
233: .ba5_SFISCfg = 0x1cc,
234: },
235: { /* Channel 2 (3114) */
236: .ba5_IDEDMA_CMD = 0x200,
237: .ba5_IDEDMA_CTL = 0x202,
238: .ba5_IDEDMA_TBL = 0x204,
239: .ba5_IDEDMA_CMD2 = 0x210,
240: .ba5_IDEDMA_CTL2 = 0x212,
241: .ba5_IDE_TF0 = 0x280, /* wd_data */
242: .ba5_IDE_TF1 = 0x281, /* wd_error */
243: .ba5_IDE_TF2 = 0x282, /* wd_seccnt */
244: .ba5_IDE_TF3 = 0x283, /* wd_sector */
245: .ba5_IDE_TF4 = 0x284, /* wd_cyl_lo */
246: .ba5_IDE_TF5 = 0x285, /* wd_cyl_hi */
247: .ba5_IDE_TF6 = 0x286, /* wd_sdh */
248: .ba5_IDE_TF7 = 0x287, /* wd_command */
249: .ba5_IDE_TF8 = 0x28a, /* wd_altsts */
250: .ba5_IDE_RAD = 0x28c,
251: .ba5_IDE_TF9 = 0x291, /* Features 2 */
252: .ba5_IDE_TF10 = 0x292, /* Sector Count 2 */
253: .ba5_IDE_TF11 = 0x293, /* Start Sector 2 */
254: .ba5_IDE_TF12 = 0x294, /* Cylinder Low 2 */
255: .ba5_IDE_TF13 = 0x295, /* Cylinder High 2 */
256: .ba5_IDE_TF14 = 0x296, /* Device/Head 2 */
257: .ba5_IDE_TF15 = 0x297, /* Cmd Sts 2 */
258: .ba5_IDE_TF16 = 0x298, /* Sector Count 2 ext */
259: .ba5_IDE_TF17 = 0x299, /* Start Sector 2 ext */
260: .ba5_IDE_TF18 = 0x29a, /* Cyl Low 2 ext */
261: .ba5_IDE_TF19 = 0x29b, /* Cyl High 2 ext */
262: .ba5_IDE_RABC = 0x29c,
263: .ba5_IDE_CMD_STS = 0x2a0,
264: .ba5_IDE_CFG_STS = 0x2a1,
265: .ba5_IDE_DTM = 0x2b4,
266: .ba5_SControl = 0x300,
267: .ba5_SStatus = 0x304,
268: .ba5_SError = 0x308,
269: .ba5_SActive = 0x30c,
270: .ba5_SMisc = 0x340,
271: .ba5_PHY_CONFIG = 0x344,
272: .ba5_SIEN = 0x348,
273: .ba5_SFISCfg = 0x34c,
274: },
275: { /* Channel 3 (3114) */
276: .ba5_IDEDMA_CMD = 0x208,
277: .ba5_IDEDMA_CTL = 0x20a,
278: .ba5_IDEDMA_TBL = 0x20c,
279: .ba5_IDEDMA_CMD2 = 0x218,
280: .ba5_IDEDMA_CTL2 = 0x21a,
281: .ba5_IDE_TF0 = 0x2c0, /* wd_data */
282: .ba5_IDE_TF1 = 0x2c1, /* wd_error */
283: .ba5_IDE_TF2 = 0x2c2, /* wd_seccnt */
284: .ba5_IDE_TF3 = 0x2c3, /* wd_sector */
285: .ba5_IDE_TF4 = 0x2c4, /* wd_cyl_lo */
286: .ba5_IDE_TF5 = 0x2c5, /* wd_cyl_hi */
287: .ba5_IDE_TF6 = 0x2c6, /* wd_sdh */
288: .ba5_IDE_TF7 = 0x2c7, /* wd_command */
289: .ba5_IDE_TF8 = 0x2ca, /* wd_altsts */
290: .ba5_IDE_RAD = 0x2cc,
291: .ba5_IDE_TF9 = 0x2d1, /* Features 2 */
292: .ba5_IDE_TF10 = 0x2d2, /* Sector Count 2 */
293: .ba5_IDE_TF11 = 0x2d3, /* Start Sector 2 */
294: .ba5_IDE_TF12 = 0x2d4, /* Cylinder Low 2 */
295: .ba5_IDE_TF13 = 0x2d5, /* Cylinder High 2 */
296: .ba5_IDE_TF14 = 0x2d6, /* Device/Head 2 */
297: .ba5_IDE_TF15 = 0x2d7, /* Cmd Sts 2 */
298: .ba5_IDE_TF16 = 0x2d8, /* Sector Count 2 ext */
299: .ba5_IDE_TF17 = 0x2d9, /* Start Sector 2 ext */
300: .ba5_IDE_TF18 = 0x2da, /* Cyl Low 2 ext */
301: .ba5_IDE_TF19 = 0x2db, /* Cyl High 2 ext */
302: .ba5_IDE_RABC = 0x2dc,
303: .ba5_IDE_CMD_STS = 0x2e0,
304: .ba5_IDE_CFG_STS = 0x2e1,
305: .ba5_IDE_DTM = 0x2f4,
306: .ba5_SControl = 0x380,
307: .ba5_SStatus = 0x384,
308: .ba5_SError = 0x388,
309: .ba5_SActive = 0x38c,
310: .ba5_SMisc = 0x3c0,
311: .ba5_PHY_CONFIG = 0x3c4,
312: .ba5_SIEN = 0x3c8,
313: .ba5_SFISCfg = 0x3cc,
314: },
315: };
316:
317: #define ba5_SIS 0x214 /* summary interrupt status */
318:
319: /* Interrupt steering bit in BA5[0x200]. */
320: #define IDEDMA_CMD_INT_STEER (1U << 1)
321:
322: /* Private data */
323: struct pciide_satalink {
324: bus_space_tag_t ba5_st;
325: bus_space_handle_t ba5_sh;
326: int ba5_en;
327:
328: struct {
329: bus_space_tag_t cmd_iot;
330: bus_space_handle_t cmd_baseioh;
331: bus_space_handle_t cmd_iohs[WDC_NREG+WDC_NSHADOWREG];
332:
333: bus_space_tag_t ctl_iot;
334: bus_space_handle_t ctl_ioh;
335:
336: bus_space_handle_t dma_iohs[IDEDMA_NREGS];
337: } regs[4];
338: };
339:
340: static INLINE uint32_t
341: ba5_read_4_ind(struct pciide_softc *sc, pcireg_t reg)
342: {
343: uint32_t rv;
344: int s;
345:
346: s = splbio();
347: pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg);
348: rv = pci_conf_read(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA);
349: splx(s);
350:
351: return (rv);
352: }
353:
354: static INLINE uint32_t
355: ba5_read_4(struct pciide_softc *sc, bus_size_t reg)
356: {
357: struct pciide_satalink *sl = sc->sc_cookie;
358:
359: if (__predict_true(sl->ba5_en != 0))
360: return (bus_space_read_4(sl->ba5_st, sl->ba5_sh, reg));
361:
362: return (ba5_read_4_ind(sc, reg));
363: }
364:
365: #define BA5_READ_4(sc, chan, reg) \
366: ba5_read_4((sc), satalink_ba5_regmap[(chan)].reg)
367:
368: static INLINE void
369: ba5_write_4_ind(struct pciide_softc *sc, pcireg_t reg, uint32_t val)
370: {
371: int s;
372:
373: s = splbio();
374: pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg);
375: pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA, val);
376: splx(s);
377: }
378:
379: static INLINE void
380: ba5_write_4(struct pciide_softc *sc, bus_size_t reg, uint32_t val)
381: {
382: struct pciide_satalink *sl = sc->sc_cookie;
383:
384: if (__predict_true(sl->ba5_en != 0))
385: bus_space_write_4(sl->ba5_st, sl->ba5_sh, reg, val);
386: else
387: ba5_write_4_ind(sc, reg, val);
388: }
389:
390: #define BA5_WRITE_4(sc, chan, reg, val) \
391: ba5_write_4((sc), satalink_ba5_regmap[(chan)].reg, (val))
392:
393: u_int8_t sii3114_read_reg(struct channel_softc *, enum wdc_regs);
394: void sii3114_write_reg(struct channel_softc *, enum wdc_regs, u_int8_t);
395:
396: struct channel_softc_vtbl wdc_sii3114_vtbl = {
397: sii3114_read_reg,
398: sii3114_write_reg,
399: wdc_default_lba48_write_reg,
400: wdc_default_read_raw_multi_2,
401: wdc_default_write_raw_multi_2,
402: wdc_default_read_raw_multi_4,
403: wdc_default_write_raw_multi_4
404: };
405:
406: #endif /* _DEV_PCI_PCIIDE_SII3112_REG_H_ */