Annotation of sys/dev/pci/pciide_piix_reg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: pciide_piix_reg.h,v 1.11 2006/04/25 09:09:42 jsg Exp $ */
2: /* $NetBSD: pciide_piix_reg.h,v 1.5 2001/01/05 15:29:40 bouyer Exp $ */
3:
4: /*
5: * Copyright (c) 1998 Manuel Bouyer.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: * 3. All advertising materials mentioning features or use of this software
16: * must display the following acknowledgement:
17: * This product includes software developed by Manuel Bouyer.
18: * 4. Neither the name of the University nor the names of its contributors
19: * may be used to endorse or promote products derived from this software
20: * without specific prior written permission.
21: *
22: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32: *
33: */
34:
35: #ifndef _DEV_PCI_PCIIDE_PIIX_REG_H_
36: #define _DEV_PCI_PCIIDE_PIIX_REG_H_
37:
38: /*
39: * Registers definitions for Intel's PIIX series PCI IDE controllers.
40: * See Intel's
41: * "82371FB (PIIX) and 82371SB (PIIX3) PCI ISA IDE XCELERATOR"
42: * "82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)" and
43: * "Intel 82801AA (ICH) and Intel 82801AB (ICH0) I/O Controller Hub"
44: * available from http://developer.intel.com/
45: */
46:
47: /*
48: * Bus master interface base address register
49: */
50: #define PIIX_BMIBA 0x20
51: #define PIIX_BMIBA_ADDR(x) (x & 0x0000FFFF0)
52: #define PIIX_BMIBA_RTE(x) (x & 0x000000001)
53: #define PIIX_BMIBA_RTE_IO 0x000000001 /* base addr maps to I/O space */
54:
55: /*
56: * IDE timing register
57: * 0x40/0x41 is for primary, 0x42/0x43 for secondary channel
58: */
59: #define PIIX_IDETIM 0x40
60: #define PIIX_IDETIM_READ(x, channel) (((x) >> (16 * (channel))) & 0x0000FFFF)
61: #define PIIX_IDETIM_SET(x, bytes, channel) \
62: ((x) | ((bytes) << (16 * (channel))))
63: #define PIIX_IDETIM_CLEAR(x, bytes, channel) \
64: ((x) & ~((bytes) << (16 * (channel))))
65:
66: #define PIIX_IDETIM_IDE 0x8000 /* PIIX decode IDE registers */
67: #define PIIX_IDETIM_SITRE 0x4000 /* slaves IDE timing registers
68: enabled (PIIX3/4 only) */
69: #define PIIX_IDETIM_ISP_MASK 0x3000 /* IOrdy sample point */
70: #define PIIX_IDETIM_ISP_SHIFT 12
71: #define PIIX_IDETIM_ISP_SET(x) ((x) << PIIX_IDETIM_ISP_SHIFT)
72: #define PIIX_IDETIM_RTC_MASK 0x0300 /* recovery time */
73: #define PIIX_IDETIM_RTC_SHIFT 8
74: #define PIIX_IDETIM_RTC_SET(x) ((x) << PIIX_IDETIM_RTC_SHIFT)
75: #define PIIX_IDETIM_DTE(d) (0x0008 << (4 * (d))) /* DMA timing only */
76: #define PIIX_IDETIM_PPE(d) (0x0004 << (4 * (d))) /* prefetch/posting */
77: #define PIIX_IDETIM_IE(d) (0x0002 << (4 * (d))) /* IORDY enable */
78: #define PIIX_IDETIM_TIME(d) (0x0001 << (4 * (d))) /* Fast timing enable */
79: /*
80: * Slave IDE timing register (PIIX3/4 only)
81: * This register must be enabled via the PIIX_IDETIM_SITRE bit
82: */
83: #define PIIX_SIDETIM 0x44
84: #define PIIX_SIDETIM_ISP_MASK(channel) (0x0c << ((channel) * 4))
85: #define PIIX_SIDETIM_ISP_SHIFT 2
86: #define PIIX_SIDETIM_ISP_SET(x, channel) \
87: (x << (PIIX_SIDETIM_ISP_SHIFT + ((channel) * 4)))
88: #define PIIX_SIDETIM_RTC_MASK(channel) (0x03 << ((channel) * 4))
89: #define PIIX_SIDETIM_RTC_SHIFT 0
90: #define PIIX_SIDETIM_RTC_SET(x, channel) \
91: (x << (PIIX_SIDETIM_RTC_SHIFT + ((channel) * 4)))
92:
93: /*
94: * Ultra DMA/33 register (PIIX4 only)
95: */
96: #define PIIX_UDMAREG 0x48
97: /* Control register */
98: #define PIIX_UDMACTL_DRV_EN(channel, drive) (0x01 << ((channel) * 2 + (drive)))
99: /* Ultra DMA/33 timing register (PIIX4 only) */
100: #define PIIX_UDMATIM_SHIFT 16
101: #define PIIX_UDMATIM_SET(x, channel, drive) \
102: (((x) << ((channel * 8) + (drive * 4))) << PIIX_UDMATIM_SHIFT)
103:
104: /*
105: * IDE config register (ICH/ICH0/ICH2 only)
106: */
107: #define PIIX_CONFIG 0x54
108: #define PIIX_CONFIG_PINGPONG 0x0400
109: /* The following are only for the 82801AA (ICH) and 82801BA (ICH2) */
110: #define PIIX_CONFIG_CR(channel, drive) (0x0010 << ((channel) * 2 + (drive)))
111: #define PIIX_CONFIG_UDMA66(channel, drive) (0x0001 << ((channel) * 2 + (drive)))
112: /* The following are only for the 82801BA (ICH2) */
113: #define PIIX_CONFIG_UDMA100(channel, drive) (0x1000 << ((channel) * 2 + (drive)))
114:
115: /*
116: * these tables define the differents values to upload to the
117: * ISP and RTC registers for the various PIO and DMA mode
118: * (from the PIIX4 doc).
119: */
120: static int8_t piix_isp_pio[] = {0x00, 0x00, 0x01, 0x02, 0x02};
121: static int8_t piix_rtc_pio[] = {0x00, 0x00, 0x00, 0x01, 0x03};
122: static int8_t piix_isp_dma[] = {0x00, 0x02, 0x02};
123: static int8_t piix_rtc_dma[] = {0x00, 0x02, 0x03};
124: static int8_t piix4_sct_udma[] = {0x00, 0x01, 0x02, 0x01, 0x02, 0x01};
125:
126: /*
127: * ICH5/ICH5R SATA registers definitions
128: */
129: #define ICH5_SATA_MAP 0x90 /* Address Map Register */
130: #define ICH5_SATA_MAP_MV_MASK 0x07 /* Map Value mask */
131: #define ICH5_SATA_MAP_COMBINED 0x04 /* Combined mode */
132:
133: #define ICH5_SATA_PI 0x09 /* Program Interface register */
134: #define ICH5_SATA_PI_PRI_NATIVE 0x01 /* Put Pri IDE channel in native mode */
135: #define ICH5_SATA_PI_SEC_NATIVE 0x04 /* Put Sec IDE channel in native mode */
136:
137: #define ICH_SATA_PCS 0x92 /* Port Control and Status Register */
138: #define ICH_SATA_PCS_P0E 0x01 /* Port 0 enabled */
139: #define ICH_SATA_PCS_P1E 0x02 /* Port 1 enabled */
140: #define ICH_SATA_PCS_P0P 0x10 /* Port 0 present */
141: #define ICH_SATA_PCS_P1P 0x20 /* Port 1 present */
142:
143: /*
144: * ICH6/ICH7 SATA registers definitions
145: */
146: #define ICH6_SATA_MAP_CMB_MASK 0x03 /* Combined mode bits */
147: #define ICH6_SATA_MAP_CMB_PRI 0x01 /* Combined mode, IDE Primary */
148: #define ICH6_SATA_MAP_CMB_SEC 0x02 /* Combined mode, IDE Secondary */
149: #define ICH7_SATA_MAP_SMS_MASK 0xc0 /* SATA Mode Select */
150: #define ICH7_SATA_MAP_SMS_IDE 0x00
151: #define ICH7_SATA_MAP_SMS_AHCI 0x40
152: #define ICH7_SATA_MAP_SMS_RAID 0x80
153:
154:
155: #endif /* !_DEV_PCI_PCIIDE_PIIX_REG_H_ */
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