Annotation of sys/dev/pci/pciide_natsemi_reg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: pciide_natsemi_reg.h,v 1.7 2007/06/24 12:41:19 kettenis Exp $ */
! 2:
! 3: /*
! 4: * Copyright (c) 2001 Jason L. Wright (jason@thought.net)
! 5: * Copyright (c) 2004 Alexander Yurchenko <grange@openbsd.org>
! 6: * All rights reserved.
! 7: *
! 8: * Redistribution and use in source and binary forms, with or without
! 9: * modification, are permitted provided that the following conditions
! 10: * are met:
! 11: * 1. Redistributions of source code must retain the above copyright
! 12: * notice, this list of conditions and the following disclaimer.
! 13: * 2. Redistributions in binary form must reproduce the above copyright
! 14: * notice, this list of conditions and the following disclaimer in the
! 15: * documentation and/or other materials provided with the distribution.
! 16: *
! 17: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 18: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
! 19: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
! 20: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
! 21: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
! 22: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
! 23: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 24: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
! 25: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
! 26: * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 27: * POSSIBILITY OF SUCH DAMAGE.
! 28: */
! 29:
! 30: #ifndef _DEV_PCI_PCIIDE_NATSEMI_REG_H_
! 31: #define _DEV_PCI_PCIIDE_NATSEMI_REG_H_
! 32:
! 33: /*
! 34: * Register definitions for National Semiconductor PC87415. Definitions
! 35: * based on "PC87415: PCI-IDE DMA Master Mode Interface Controller"
! 36: * (March 1996) datasheet from their website.
! 37: */
! 38:
! 39: #define NATSEMI_CTRL1 0x40 /* Control register1 */
! 40: #define NATSEMI_CTRL1_SWRST 0x04 /* sw rst to ch1/ch2 on */
! 41: #define NATSEMI_CTRL1_IDEPWR 0x08
! 42: #define NATSEMI_CTRL1_CH1INTMAP 0x10
! 43: #define NATSEMI_CTRL1_CH2INTMAP 0x20
! 44: #define NATSEMI_CTRL1_INTAMASK 0x40
! 45: #define NATSEMI_CTRL1_IDWR 0x80 /* write to did/vid enable */
! 46:
! 47: #define NATSEMI_CTRL2 0x41 /* Control register2 */
! 48: #define NATSEMI_CTRL2_CH1MASK 0x01 /* channel 1 intr masked */
! 49: #define NATSEMI_CTRL2_CH2MASK 0x02 /* channel 2 intr masked */
! 50: #define NATSEMI_CTRL2_BARDIS 0x04 /* PCI BAR 2/3 disable */
! 51: #define NATSEMI_CTRL2_WATCHDOG 0x08 /* enable watchdog timer */
! 52: #define NATSEMI_CTRL2_BUF1BYP 0x10 /* bypass buffer 1 */
! 53: #define NATSEMI_CTRL2_BUF2BYP 0x20 /* bypass buffer 2 */
! 54: #define NATSEMI_CTRL2_IDE1MAP 0x40 /* IDE at bar 1 */
! 55: #define NATSEMI_CTRL2_IDE2MAP 0x80 /* IDE at bar 2 */
! 56:
! 57: #define NATSEMI_CHMASK(chn) (NATSEMI_CTRL2_CH1MASK << (chn))
! 58:
! 59: #define NATSEMI_CTRL3 0x42 /* Control register3 */
! 60: #define NATSEMI_CTRL3_CH1PREDIS 0x01 /* channel 1 prefetch disable */
! 61: #define NATSEMI_CTRL3_CH2PREDIS 0x02 /* channel 2 prefetch disable */
! 62: #define NATSEMI_CTRL3_RSTIDLE 0x04 /* reset idle state */
! 63: #define NATSEMI_CTRL3_C1D1DMARQ 0x10 /* c1d1 dmarq handshaking */
! 64: #define NATSEMI_CTRL3_C1D2DMARQ 0x20 /* c1d2 dmarq handshaking */
! 65: #define NATSEMI_CTRL3_C2D1DMARQ 0x40 /* c2d1 dmarq handshaking */
! 66: #define NATSEMI_CTRL3_C2D2DMARQ 0x80 /* c2d2 dmarq handshaking */
! 67:
! 68: #define NATSEMI_WBS 0x43 /* Write buffer status */
! 69: #define NATSEMI_WBS_WB1NMPTY 0x01 /* chan 1 write buf not empty */
! 70: #define NATSEMI_WBS_WB2NMPTY 0x02 /* chan 2 write buf not empty */
! 71:
! 72: #define NATSEMI_C1D1DRT 0x44 /* Channel 1/device 1 data read timing */
! 73: #define NATSEMI_C1D1DWT 0x45 /* Channel 1/device 1 data write timing */
! 74: #define NATSEMI_C1D2DRT 0x48 /* Channel 1/device 2 data read timing */
! 75: #define NATSEMI_C1D2DWT 0x49 /* Channel 1/device 2 data write timing */
! 76: #define NATSEMI_C2D1DRT 0x4c /* Channel 2/device 1 data read timing */
! 77: #define NATSEMI_C2D1DWT 0x4d /* Channel 2/device 1 data write timing */
! 78: #define NATSEMI_C2D2DRT 0x50 /* Channel 2/device 2 data read timing */
! 79: #define NATSEMI_C2D2DWT 0x51 /* Channel 2/device 2 data write timing */
! 80:
! 81: #define NATSEMI_CCBT 0x54 /* Command and control block timing */
! 82:
! 83: #define NATSEMI_SECT 0x55 /* Sector size */
! 84: #define NATSEMI_SECT_C1UNUSED 0x0f /* not used */
! 85: #define NATSEMI_SECT_C1_512 0x0e /* 512 bytes */
! 86: #define NATSEMI_SECT_C1_1024 0x0c /* 1024 bytes */
! 87: #define NATSEMI_SECT_C1_2048 0x08 /* 2048 bytes */
! 88: #define NATSEMI_SECT_C1_4096 0x00 /* 4096 bytes */
! 89: #define NATSEMI_SECT_C2UNUSED 0xf0 /* not used */
! 90: #define NATSEMI_SECT_C2_512 0xe0 /* 512 bytes */
! 91: #define NATSEMI_SECT_C2_1024 0xc0 /* 1024 bytes */
! 92: #define NATSEMI_SECT_C2_2048 0x80 /* 2048 bytes */
! 93: #define NATSEMI_SECT_C2_4096 0x00 /* 4096 bytes */
! 94:
! 95: #define NATSEMI_RTREG(c,d) (0x44 + (c * 8) + (d * 4) + 0)
! 96: #define NATSEMI_WTREG(c,d) (0x44 + (c * 8) + (d * 4) + 1)
! 97:
! 98: /* 17 - N = number of clocks */
! 99: static u_int8_t natsemi_pio_pulse[] = { 7, 12, 13, 14, 14 };
! 100: static u_int8_t natsemi_dma_pulse[] = { 7, 10, 10 };
! 101: /* 16 - N = number of clocks */
! 102: static u_int8_t natsemi_pio_recover[] = { 6, 8, 11, 13, 15 };
! 103: static u_int8_t natsemi_dma_recover[] = { 6, 8, 9 };
! 104:
! 105:
! 106: /*
! 107: * Register definitions for National Semiconductor SCx200 IDE found
! 108: * on Geode SC1100 IAOC.
! 109: */
! 110: #define SCx200_TIM_PIO(chan, drive) (0x40 + 16 * (chan) + 8 * (drive))
! 111: #define SCx200_TIM_DMA(chan, drive) (0x44 + 16 * (chan) + 8 * (drive))
! 112:
! 113: #define SCx200_PIOFORMAT_SHIFT 31
! 114:
! 115: /* PIO mode timings */
! 116: const static u_int32_t scx200_pio33[2][5] = {
! 117: /* Format 0 */
! 118: { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 },
! 119: /* Format 1 */
! 120: { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010 }};
! 121: const static u_int32_t scx200_pio66[2][5] = {
! 122: /* Fromat 0 */
! 123: { 0x0000f8e4, 0x000153f3, 0x000213f1, 0x00034231, 0x00041131 },
! 124: /* Format 1 */
! 125: { 0xf8e4f8e4, 0x53f3f353, 0x13f18141, 0x42314231, 0x11311131 }};
! 126:
! 127: /* DMA mode timings */
! 128: const static u_int32_t scx200_dma33[] = { 0x00077771, 0x00012121, 0x00002020 };
! 129: const static u_int32_t scx200_dma66[] = { 0x000ffff3, 0x00035352, 0x00015151 };
! 130:
! 131: /* UDMA mode timings */
! 132: const static u_int32_t scx200_udma33[] = { 0x00921250, 0x00911140, 0x00911030 };
! 133: const static u_int32_t scx200_udma66[] = { 0x009436a1, 0x00933481, 0x00923261 };
! 134:
! 135: #endif /* !_DEV_PCI_PCIIDE_NATSEMI_REG_H_ */
CVSweb
![[BACK]](/icons/back.gif){kind=icon}
Return to pciide_natsemi_reg.h CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / dev / pci