Annotation of sys/dev/pci/pciide_i31244_reg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: pciide_i31244_reg.h,v 1.2 2006/11/19 20:09:59 brad Exp $ */
! 2: /* $NetBSD: pciide_i31244_reg.h,v 1.2 2005/02/11 21:12:32 rearnsha Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 2002 Wasabi Systems, Inc.
! 6: * All rights reserved.
! 7: *
! 8: * Written by Jason R. Thorpe for Wasabi Systems, Inc.
! 9: *
! 10: * Redistribution and use in source and binary forms, with or without
! 11: * modification, are permitted provided that the following conditions
! 12: * are met:
! 13: * 1. Redistributions of source code must retain the above copyright
! 14: * notice, this list of conditions and the following disclaimer.
! 15: * 2. Redistributions in binary form must reproduce the above copyright
! 16: * notice, this list of conditions and the following disclaimer in the
! 17: * documentation and/or other materials provided with the distribution.
! 18: * 3. All advertising materials mentioning features or use of this software
! 19: * must display the following acknowledgement:
! 20: * This product includes software developed for the NetBSD Project by
! 21: * Wasabi Systems, Inc.
! 22: * 4. The name of Wasabi Systems, Inc. may not be used to endorse
! 23: * or promote products derived from this software without specific prior
! 24: * written permission.
! 25: *
! 26: * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
! 27: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
! 28: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
! 29: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
! 30: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
! 31: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
! 32: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
! 33: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
! 34: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
! 35: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 36: * POSSIBILITY OF SUCH DAMAGE.
! 37: */
! 38:
! 39: #ifndef _DEV_PCI_PCIIDE_I31244_REG_H_
! 40: #define _DEV_PCI_PCIIDE_I31244_REG_H_
! 41:
! 42: /*
! 43: * Register definitions for the Intel i31244 Serial ATA Controller.
! 44: */
! 45:
! 46: /*
! 47: * In DPA mode, the i31244 has a single 64-bit BAR.
! 48: */
! 49: #define ARTISEA_PCI_DPA_BASE PCI_MAPREG_START
! 50:
! 51: /*
! 52: * Extended Control and Status Register 0
! 53: */
! 54: #define ARTISEA_PCI_SUECSR0 0x98
! 55: #define SUECSR0_LED0_ONLY (1U << 28) /* activity on LED0 only */
! 56: #define SUECSR0_SFSS (1U << 16) /* Superset Features
! 57: Secondary Select */
! 58:
! 59: #define ARTISEA_PCI_SUDCSCR 0xa0
! 60: #define SUDCSCR_DMA_WCAE 0x02 /* Write cache align enable */
! 61: #define SUDCSCR_DMA_RCAE 0x01 /* Read cache align enable */
! 62:
! 63: /*
! 64: * DPA mode shared registers.
! 65: */
! 66: #define ARTISEA_SUPDIPR 0x00 /* DPA interrupt pending register */
! 67: #define SUPDIPR_PORTSHIFT(x) ((x) * 8)
! 68: #define SUPDIPR_PHY_CS (1U << 0) /* PHY change state */
! 69: #define SUPDIPR_PHY_RDY (1U << 1) /* PHY ready */
! 70: #define SUPDIPR_FIFO_ERR (1U << 2) /* FIFO error */
! 71: #define SUPDIPR_ERR_RCVD (1U << 3) /* ERR received */
! 72: #define SUPDIPR_U_FIS_R (1U << 4) /* unrecog. FIS reception */
! 73: #define SUPDIPR_DATA_I (1U << 5) /* data integrity */
! 74: #define SUPDIPR_CRC_ED (1U << 6) /* CRC error detected */
! 75: #define SUPDIPR_IDE (1U << 7) /* IDE interrupt */
! 76:
! 77: #define ARTISEA_SUPDIMR 0x04 /* DPA interrupt mask register */
! 78: /* See SUPDIPR bits. */
! 79:
! 80: /*
! 81: * DPA mode offset to per-port registers.
! 82: */
! 83: #define ARTISEA_DPA_PORT_BASE(x) (((x) + 1) * 0x200)
! 84:
! 85: /*
! 86: * DPA mode per-port registers.
! 87: */
! 88: #define ARTISEA_SUPDDR 0x00 /* DPA data port register */
! 89: /* ATA/ATAPI compatible */
! 90:
! 91: #define ARTISEA_SUPDER 0x04 /* DPA error register */
! 92: /* ATA/ATAPI compatible */
! 93:
! 94: #define ARTISEA_SUPDFR 0x06 /* DPA features register */
! 95: /* ATA/ATAPI compatible */
! 96:
! 97: #define ARTISEA_SUPDCSR 0x08 /* DPA sector count register */
! 98: /* ATA/ATAPI compatible */
! 99:
! 100: #define ARTISEA_SUPDSNR 0x0c /* DPA sector number register */
! 101: /* ATA/ATAPI compatible */
! 102:
! 103: #define ARTISEA_SUPDCLR 0x10 /* DPA cylinder low register */
! 104: /* ATA/ATAPI compatible */
! 105:
! 106: #define ARTISEA_SUPDCHR 0x14 /* DPA cylinder high register */
! 107: /* ATA/ATAPI compatible */
! 108:
! 109: #define ARTISEA_SUPDDHR 0x18 /* DPA device/head register */
! 110: /* ATA/ATAPI compatible */
! 111:
! 112: #define ARTISEA_SUPDSR 0x1c /* DPA status register */
! 113: /* ATA/ATAPI compatible */
! 114:
! 115: #define ARTISEA_SUPDCR 0x1d /* DPA command register */
! 116: /* ATA/ATAPI compatible */
! 117:
! 118: #define ARTISEA_SUPDASR 0x28 /* DPA alt. status register */
! 119: /* ATA/ATAPI compatible */
! 120:
! 121: #define ARTISEA_SUPDDCTLR 0x29 /* DPA device control register */
! 122: /* ATA/ATAPI compatible */
! 123:
! 124: #define ARTISEA_SUPDUDDTPR 0x64 /* DPA upper DMA desc. table pointer */
! 125:
! 126: #define ARTISEA_SUPDUDDPR 0x6c /* DPA upper DMA data buffer pointer */
! 127:
! 128: #define ARTISEA_SUPDDCMDR 0x70 /* DPA DMA command register */
! 129: /* Almost compatible with PCI IDE, but not quite. */
! 130: #define SUPDDCMDR_START (1U << 0) /* start DMA transfer (c) */
! 131: #define SUPDDCMDR_WRITE (1U << 3) /* write *to memory* (c) */
! 132: #define SUPDDCMDR_DP_DMA_ACT (1U << 8) /* first party DMA active */
! 133: #define SUPDDCMDR_FP_DMA_DIR (1U << 9) /* 1 = host->device */
! 134:
! 135: #define ARTISEA_SUPDDSR 0x72 /* DPA DMA status register */
! 136: /* PCI IDE compatible */
! 137:
! 138: #define ARTISEA_SUPDDDTPR 0x74 /* DPA DMA desc. table pointer */
! 139:
! 140: #define ARTISEA_SUPERSET_DPA_OFF 0x100 /* offset to Superset regs: DPA mode */
! 141:
! 142: #define ARTISEA_SUPDSSSR 0x000 /* DPA SATA SStatus register */
! 143: #define SUPDSSSR_IPM_NP (0 << 8) /* device not present */
! 144: #define SUPDSSSR_IPM_ACT (1U << 8) /* active state */
! 145: #define SUPDSSSR_IPM_PARTIAL (2U << 8) /* partial power mgmt */
! 146: #define SUPDSSSR_IPM_SLUMBER (6U << 8) /* slumber power mgmt */
! 147: #define SUPDSSSR_SPD_NP (0 << 4) /* device not present */
! 148: #define SUPDSSSR_SPD_G1 (1U << 4) /* Generation 1 speed */
! 149: #define SUPDSSSR_DET_NP (0 << 0) /* device not present */
! 150: #define SUPDSSSR_DET_PHY_CNE (1U << 0) /* PHY comm. not established */
! 151: #define SUPDSSSR_DET_PHY_CE (3U << 0) /* PHY comm. established */
! 152: #define SUPDSSSR_DET_PHY_LOOP (4U << 0) /* loopback mode */
! 153:
! 154: #define ARTISEA_SUPDSSER 0x004 /* DPA SATA SError register */
! 155: #define SUPDSSER_DIAG_F (1U << 25) /* invalid FIS type */
! 156: #define SUPDSSER_DIAG_T (1U << 24) /* not implemented */
! 157: #define SUPDSSER_DIAG_S (1U << 23) /* not implemented */
! 158: #define SUPDSSER_DIAG_H (1U << 22) /* handshake error */
! 159: #define SUPDSSER_DIAG_C (1U << 21) /* CRC error */
! 160: #define SUPDSSER_DIAG_D (1U << 20) /* disparity error */
! 161: #define SUPDSSER_DIAG_B (1U << 19) /* not implemented */
! 162: #define SUPDSSER_DIAG_W (1U << 18) /* comm wake */
! 163: #define SUPDSSER_DIAG_I (1U << 17) /* not implemented */
! 164: #define SUPDSSER_DIAG_N (1U << 16) /* PHY RDY state change */
! 165: #define SUPDSSER_ERR_E (1U << 11) /* internal error */
! 166: #define SUPDSSER_ERR_P (1U << 10) /* protocol error */
! 167: #define SUPDSSER_ERR_C (1U << 9) /* non-recovered comm. */
! 168: #define SUPDSSER_ERR_T (1U << 8) /* non-recovered TDIE */
! 169: #define SUPDSSER_ERR_M (1U << 1) /* recovered comm. */
! 170: #define SUPDSSER_ERR_I (1U << 0) /* not implemented */
! 171:
! 172: #define ARTISEA_SUPDSSCR 0x008 /* DPA SATA SControl register */
! 173: #define SUPDSSCR_IPM_ANY (0 << 8) /* no IPM mode restrictions */
! 174: #define SUPDSSCR_IPM_NO_PARTIAL (1U << 8) /* no PARTIAL mode */
! 175: #define SUPDSSCR_IPM_NO_SLUMBER (2U << 8) /* no SLUMBER mode */
! 176: #define SUPDSSCR_IPM_NONE (3U << 8) /* no PM allowed */
! 177: #define SUPDSSCR_SPD_ANY (0 << 4) /* no speed restrictions */
! 178: #define SUPDSSCR_SPD_G1 (1U << 4) /* <= Generation 1 */
! 179: #define SUPDSSCR_DET_NORM (0 << 0) /* normal operation */
! 180: #define SUPDSSCR_DET_INIT (1U << 0) /* comm. init */
! 181: #define SUPDSSCR_DET_DISABLE (4U << 0) /* disable interface */
! 182:
! 183: #define ARTISEA_SUPDSDBR 0x00c /* DPA Set Device Bits register */
! 184:
! 185: #define ARTISEA_SUPDPFR 0x040 /* DPA PHY feature register */
! 186: #define SUPDPFR_SSCEN (1U << 16) /* SSC enable */
! 187: #define SUPDPFR_FVS (1U << 14) /* full voltage swing */
! 188:
! 189: #define ARTISEA_SUPDBFCSR 0x044 /* DPA BIST FIS ctrl/stat register */
! 190: #define SUPDBFCSR_PAT_D21_5 (0 << 30) /* D21.5s */
! 191: #define SUPDBFCSR_PAT_D24_3 (1U << 30) /* D24.3s */
! 192: #define SUPDBFCSR_PAT_D10_2 (2U << 30) /* D10.2 / K28.5 */
! 193: #define SUPDBFCSR_PAT_COUNT (3U << 30) /* counting */
! 194: #define SUPDBFCSR_CS_D21_5 (0 << 28)
! 195: #define SUPDBFCSR_CS_D24_3 (1U << 28)
! 196: #define SUPDBFCSR_CS_D10_2 (2U << 28)
! 197: #define SUPDBFCSR_CS_COUNT (3U << 30)
! 198: #define SUPDBFCSR_CLEAR_ERRS (1U << 25) /* clear errors/frames */
! 199: #define SUPDBFCSR_CE (1U << 24) /* BIST check enable */
! 200: #define SUPDBFCSR_PE (1U << 23) /* BIST pattern enable */
! 201: #define SUPDBFCSR_K28_5 ((1U << 16) | \
! 202: (1U << 8) /* send K28.5s */
! 203: #define SUPDBFCSR_BIST_ACT_RX (1U << 15) /* BIST Act. FIS was rx'd */
! 204: #define SUPDBFCSR_BIST_ACT_RX_TO (1U << 14) /* ...with transmit-only */
! 205: #define SUPDBFCSR_BIST_ACT_RX_AB (1U << 13) /* ...with align-bypass */
! 206: #define SUPDBFCSR_BIST_ACT_RX_SB (1U << 12) /* ...with scrambling-bypass */
! 207: #define SUPDBFCSR_BIST_ACT_RX_RT (1U << 11) /* ...with retimed */
! 208: #define SUPDBFCSR_BIST_ACT_RX_P (1U << 10) /* ...with primitive */
! 209: #define SUPDBFCSR_BIST_ACT_RX_AFEL (1U << 9) /* ...with AFE loopback */
! 210: #define SUPDBFCSR_BIST_ACT_TX (1U << 7) /* send BIST Act. FIS */
! 211: #define SUPDBFCSR_BIST_ACT_TX_TO (1U << 6) /* ...with transmit-only */
! 212: #define SUPDBFCSR_BIST_ACT_TX_AB (1U << 5) /* ...with align-bypass */
! 213: #define SUPDBFCSR_BIST_ACT_TX_SB (1U << 4) /* ...with scrambling-bypass */
! 214: #define SUPDBFCSR_BIST_ACT_TX_RT (1U << 3) /* ...with retimed */
! 215: #define SUPDBFCSR_BIST_ACT_TX_P (1U << 2) /* ...with primitive */
! 216: #define SUPDBFCSR_BIST_ACT_TX_AFEL (1U << 1) /* ...with AFE loopback */
! 217: #define SUPDBFCSR_INIT_NE_TO (1U << 0) /* init. near-end tx-only */
! 218:
! 219: #define ARTISEA_SUPDBER 0x048 /* DPA BIST errors register */
! 220:
! 221: #define ARTISEA_SUPDBFR 0x04c /* DPA BIST frames register */
! 222:
! 223: #define ARTISEA_SUPDHBDLR 0x050 /* DPA Host BIST data low register */
! 224:
! 225: #define ARTISEA_SUPDHBDHR 0x054 /* DPA Host BIST data high register */
! 226:
! 227: #define ARTISEA_SUPDDBDLR 0x058 /* DPA Device BIST data low */
! 228:
! 229: #define ARTISEA_SUPDDBDHR 0x05c /* DPA Device BIST data high */
! 230:
! 231: #define ARTISEA_SUPDDSFCSR 0x068 /* DPA DMA setup FIS ctrl/stat */
! 232: #define SUPDDSFCSR_DIR (1U << 31) /* First Party setup FIS
! 233: word 0 direction bit
! 234: (1 == tx -> rx) */
! 235: #define SUPDDSFCSR_INTR (1U << 30) /* rcvd's First Party setup
! 236: FIS with I bit set */
! 237: #define SUPDDSFCSR_START_SETUP (1U << 28) /* send DMA setup FIS */
! 238: #define SUPDDSFCSR_EN_FP_AP (1U << 27) /* enab. FP DMA auto-process */
! 239: #define SUPDDSFCSR_ABORT_TSM (1U << 24) /* abort xport/link SMs */
! 240:
! 241: #define ARTISEA_SUPDHDBILR 0x06c /* DPA Host DMA Buff. Id low */
! 242:
! 243: #define ARTISEA_SUPDHDBIHR 0x070 /* DPA Host DMA Buff. Id high */
! 244:
! 245: #define ARTISEA_SUPDHRDR0 0x074 /* DPA Host Resvd. DWORD 0 */
! 246:
! 247: #define ARTISEA_SUPDHDBOR 0x078 /* DPA Host DMA Buff. offset */
! 248:
! 249: #define ARTISEA_SUPDHDTCR 0x07c /* DPA Host DMA xfer count */
! 250:
! 251: #define ARTISEA_SUPDHRDR1 0x080 /* DPA Host Resvd. DWORD 1 */
! 252:
! 253: #define ARTISEA_SUPDDDBILR 0x084 /* DPA Device DMA Buff. Id low */
! 254:
! 255: #define ARTISEA_SUPDDDBIHR 0x088 /* DPA Device DMA Buff. Id high */
! 256:
! 257: #define ARTISEA_SUPDDRDR0 0x08c /* DPA Device Resvd. DWORD 0 */
! 258:
! 259: #define ARTISEA_SUPDDDBOR 0x090 /* DPA Device DMA Buff. offset */
! 260:
! 261: #define ARTISEA_SUPDDTCR 0x094 /* DPA Device DMA xfer count */
! 262:
! 263: #define ARTISEA_SUPDDRDR1 0x09c /* DPA Device Resvd. DWORD 1 */
! 264:
! 265: #endif /* _DEV_PCI_PCIIDE_I31244_REG_H_ */
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