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Annotation of sys/dev/pci/pciide_cmd_reg.h, Revision 1.1

1.1     ! nbrk        1: /*     $OpenBSD: pciide_cmd_reg.h,v 1.9 2004/09/24 07:38:38 grange Exp $       */
        !             2: /*     $NetBSD: pciide_cmd_reg.h,v 1.9 2000/08/02 20:23:46 bouyer Exp $        */
        !             3:
        !             4: /*
        !             5:  * Copyright (c) 1998 Manuel Bouyer.
        !             6:  *
        !             7:  * Redistribution and use in source and binary forms, with or without
        !             8:  * modification, are permitted provided that the following conditions
        !             9:  * are met:
        !            10:  * 1. Redistributions of source code must retain the above copyright
        !            11:  *    notice, this list of conditions and the following disclaimer.
        !            12:  * 2. Redistributions in binary form must reproduce the above copyright
        !            13:  *    notice, this list of conditions and the following disclaimer in the
        !            14:  *    documentation and/or other materials provided with the distribution.
        !            15:  * 3. All advertising materials mentioning features or use of this software
        !            16:  *    must display the following acknowledgement:
        !            17:  *     This product includes software developed by Manuel Bouyer.
        !            18:  * 4. Neither the name of the University nor the names of its contributors
        !            19:  *    may be used to endorse or promote products derived from this software
        !            20:  *    without specific prior written permission.
        !            21:  *
        !            22:  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
        !            23:  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
        !            24:  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
        !            25:  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
        !            26:  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
        !            27:  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
        !            28:  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
        !            29:  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
        !            30:  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
        !            31:  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
        !            32:  *
        !            33:  */
        !            34:
        !            35: #ifndef _DEV_PCI_PCIIDE_CMD_REG_H_
        !            36: #define _DEV_PCI_PCIIDE_CMD_REG_H_
        !            37:
        !            38: /*
        !            39:  * Registers definitions for CMD Technologies's PCI 064x IDE controllers.
        !            40:  * Available from http://www.cmd.com/
        !            41:  */
        !            42:
        !            43: /* Interesting revision of the 0646 */
        !            44: #define CMD0646U2_REV 0x05
        !            45: #define CMD0646U_REV 0x03
        !            46:
        !            47: /* Configuration (RO) */
        !            48: #define CMD_CONF 0x50
        !            49: #define CMD_CONF_REV_MASK      0x03 /* 0640/3/6 only */
        !            50: #define CMD_CONF_DRV0_INTR     0x04
        !            51: #define CMD_CONF_DEVID         0x18 /* 0640/3/6 only */
        !            52: #define CMD_CONF_VESAPRT       0x20 /* 0640/3/6 only */
        !            53: #define CMD_CONF_DSA1          0x40
        !            54: #define CMD_CONF_DSA0          0x80 /* 0640/3/6 only */
        !            55:
        !            56: /* Control register (RW) */
        !            57: #define CMD_CTRL 0x51
        !            58: #define CMD_CTRL_HR_FIFO               0x01 /* 0640/3/6 only */
        !            59: #define CMD_CTRL_HW_FIFO               0x02 /* 0640/3/6 only */
        !            60: #define CMD_CTRL_DEVSEL                        0x04
        !            61: #define CMD_CTRL_2PORT                 0x08
        !            62: #define CMD_CTRL_PAR                   0x10 /* 0640/3/6 only */
        !            63: #define CMD_CTRL_HW_HLD                        0x20 /* 0640/3/6 only */
        !            64: #define CMD_CTRL_DRV0_RAHEAD           0x40
        !            65: #define CMD_CTRL_DRV1_RAHEAD           0x80
        !            66:
        !            67: /*
        !            68:  * data read/write timing registers . 0640 uses the same for drive 0 and 1
        !            69:  * on the secondary channel
        !            70:  */
        !            71: #define CMD_DATA_TIM(chan, drive) \
        !            72:        (((chan) == 0) ? \
        !            73:                ((drive) == 0) ? 0x54: 0x56 \
        !            74:                : \
        !            75:                ((drive) == 0) ? 0x58 : 0x5b)
        !            76:
        !            77: /* secondary channel status and addr timings */
        !            78: #define CMD_ARTTIM23   0x57
        !            79: #define CMD_ARTTIM23_IRQ       0x10
        !            80: #define CMD_ARTTIM23_RHAEAD(d) ((0x4) << (d))
        !            81:
        !            82: /* DMA master read mode select */
        !            83: #define CMD_DMA_MODE 0x71
        !            84: #define CMD_DMA_MASK           0x03
        !            85: #define CMD_DMA                        0x00
        !            86: #define CMD_DMA_MULTIPLE       0x01
        !            87: #define CMD_DMA_LINE           0x03
        !            88: /* the followings bits are only for 0646U/646U2/648/649 */
        !            89: #define CMD_DMA_IRQ(chan)      (0x4 << (chan))
        !            90: #define CMD_DMA_IRQ_DIS(chan)  (0x10 << (chan))
        !            91: #define CMD_DMA_RST            0x40
        !            92:
        !            93: /* the followings are only for 0646U/646U2/648/649 */
        !            94: /* busmaster control/status register */
        !            95: #define CMD_BICSR      0x79
        !            96: #define CMD_BICSR_80(chan)     (0x01 << (chan))
        !            97: /* Ultra/DMA timings reg */
        !            98: #define CMD_UDMATIM(channel)   (0x73 + (8 * (channel)))
        !            99: #define CMD_UDMATIM_UDMA(drive)        (0x01 << (drive))
        !           100: #define CMD_UDMATIM_UDMA33(drive) (0x04 << (drive))
        !           101: #define CMD_UDMATIM_TIM_MASK   0x3
        !           102: #define CMD_UDMATIM_TIM_OFF(drive) (4 + ((drive) * 2))
        !           103: static int8_t cmd0646_9_tim_udma[] = {0x03, 0x02, 0x01, 0x02, 0x01, 0x00};
        !           104:
        !           105: /*
        !           106:  * timings values for the 0643/6/8/9
        !           107:  * for all dma_mode we have to have
        !           108:  * DMA_timings(dma_mode) >= PIO_timings(dma_mode + 2)
        !           109:  */
        !           110: static int8_t cmd0643_9_data_tim_pio[] = {0xA9, 0x57, 0x44, 0x32, 0x3F};
        !           111: static int8_t cmd0643_9_data_tim_dma[] = {0x87, 0x32, 0x3F};
        !           112:
        !           113: #endif /* !_DEV_PCI_PCIIDE_CMD_REG_H_ */