Annotation of sys/dev/pci/pccbbreg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: pccbbreg.h,v 1.9 2006/04/26 21:21:53 brad Exp $ */
! 2: /* $NetBSD: pccbbreg.h,v 1.5 2000/06/07 09:02:47 haya Exp $ */
! 3: /*
! 4: * Copyright (c) 1999 HAYAKAWA Koichi. All rights reserved.
! 5: *
! 6: * Redistribution and use in source and binary forms, with or without
! 7: * modification, are permitted provided that the following conditions
! 8: * are met:
! 9: * 1. Redistributions of source code must retain the above copyright
! 10: * notice, this list of conditions and the following disclaimer.
! 11: * 2. Redistributions in binary form must reproduce the above copyright
! 12: * notice, this list of conditions and the following disclaimer in the
! 13: * documentation and/or other materials provided with the distribution.
! 14: * 3. All advertising materials mentioning features or use of this software
! 15: * must display the following acknowledgement:
! 16: * This product includes software developed by HAYAKAWA Koichi.
! 17: * 4. The name of the author may not be used to endorse or promote products
! 18: * derived from this software without specific prior written permission.
! 19: *
! 20: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 21: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
! 22: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
! 23: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
! 24: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
! 25: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
! 26: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
! 27: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
! 28: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
! 29: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
! 30: */
! 31:
! 32: #ifndef _DEV_PCI_PCCBBREG_H_
! 33: #define _DEV_PCI_PCCBBREG_H_
! 34:
! 35: #define PCI_SOCKBASE 0x10 /* Socket Base Address Register */
! 36: #define PCI_BUSNUM 0x18 /* Latency timer, Subordinate bus number */
! 37: #define PCI_BCR_INTR 0x3C /* Intr line, intr pin, bridge control regs */
! 38: #define PCI_LEGACY 0x44 /* Legacy IO register address (32 bits) */
! 39: #define PCI_SYSCTRL 0x80 /* System control */
! 40: #define PCI_CBCTRL 0x90 /* Retry status, Card ctrl, Device ctrl */
! 41:
! 42: #define PCI_CLASS_INTERFACE_MASK 0xFFFFFF00
! 43: #define PCI_CLASS_INTERFACE_YENTA 0x06070000
! 44:
! 45: /* CardBus latency timer, Subordinate bus no, CardBus bus no and PCI bus no */
! 46: #define PCI_CB_LSCP_REG 0x18
! 47:
! 48: /* CardBus memory and io windows */
! 49: #define PCI_CB_MEMBASE0 0x1C
! 50: #define PCI_CB_MEMLIMIT0 0x20
! 51: #define PCI_CB_MEMBASE1 0x24
! 52: #define PCI_CB_MEMLIMIT1 0x28
! 53: #define PCI_CB_IOBASE0 0x2C
! 54: #define PCI_CB_IOLIMIT0 0x30
! 55: #define PCI_CB_IOBASE1 0x34
! 56: #define PCI_CB_IOLIMIT1 0x38
! 57:
! 58: /* PCI_CB_LSCP_REG */
! 59: #define PCI_CB_LATENCY_SHIFT 24
! 60: #define PCI_CB_LATENCY_MASK 0xFF
! 61: #define PCI_CB_LATENCY(x)( \
! 62: ((x) >> PCI_CB_LATENCY_SHIFT) & PCI_CB_LATENCY_MASK)
! 63:
! 64: /*
! 65: * Cardbus socket registers
! 66: */
! 67: #define CB_SOCKET_EVENT 0x00 /* Event */
! 68: #define CB_SOCKET_EVENT_CSTS 0x01 /* CARDSTS event occurs */
! 69: #define CB_SOCKET_EVENT_CD 0x06 /* CD event occurs */
! 70: #define CB_SOCKET_EVENT_CD1 0x02 /* CD1 event occurs */
! 71: #define CB_SOCKET_EVENT_CD2 0x04 /* CD2 event occurs */
! 72: #define CB_SOCKET_EVENT_POWER 0x08 /* Power cycle event occurs */
! 73:
! 74: #define CB_SOCKET_MASK 0x04 /* Mask */
! 75: #define CB_SOCKET_MASK_CSTS 0x01 /* CARDSTS event mask */
! 76: #define CB_SOCKET_MASK_CD 0x06 /* CD event mask */
! 77: #define CB_SOCKET_MASK_POWER 0x08 /* Power cycle event mask */
! 78:
! 79: #define CB_SOCKET_STAT 0x08 /* Present-state */
! 80: #define CB_SOCKET_STAT_CARDSTS 0x00000001 /* Card status change bit */
! 81: #define CB_SOCKET_STAT_CD1 0x00000002 /* Card detect 1 */
! 82: #define CB_SOCKET_STAT_CD2 0x00000004 /* Card detect 2 */
! 83: #define CB_SOCKET_STAT_CD 0x00000006 /* Card detect 1 and 2 */
! 84: #define CB_SOCKET_STAT_PWRCYCLE 0x00000008 /* Power cycle */
! 85: #define CB_SOCKET_STAT_16BIT 0x00000010 /* 16-bit card */
! 86: #define CB_SOCKET_STAT_CB 0x00000020 /* Cardbus card */
! 87: #define CB_SOCKET_STAT_IREQ 0x00000040 /* READY(~IREQ)//(~CINT) */
! 88: /* bit */
! 89: #define CB_SOCKET_STAT_NOTCARD 0x00000080 /* Inserted card is */
! 90: /* unrecognisable */
! 91: #define CB_SOCKET_STAT_DATALOST 0x00000100 /* Data lost */
! 92: #define CB_SOCKET_STAT_BADVCC 0x00000200 /* Bad Vcc Request */
! 93: #define CB_SOCKET_STAT_5VCARD 0x00000400 /* 5 V Card */
! 94: #define CB_SOCKET_STAT_3VCARD 0x00000800 /* 3.3 V Card */
! 95: #define CB_SOCKET_STAT_XVCARD 0x00001000 /* X.X V Card */
! 96: #define CB_SOCKET_STAT_YVCARD 0x00002000 /* Y.Y V Card */
! 97: #define CB_SOCKET_STAT_5VSOCK 0x10000000 /* 5 V Socket */
! 98: #define CB_SOCKET_STAT_3VSOCK 0x20000000 /* 3.3 V Socket */
! 99: #define CB_SOCKET_STAT_XVSOCK 0x40000000 /* X.X V Socket */
! 100: #define CB_SOCKET_STAT_YVSOCK 0x80000000 /* Y.Y V Socket */
! 101:
! 102: #define CB_SOCKET_FORCE 0x0C /* Force event */
! 103: #define CB_SOCKET_FORCE_BADVCC 0x0200 /* Bad Vcc Request */
! 104:
! 105: #define CB_SOCKET_CTRL 0x10 /* Control */
! 106: #define CB_SOCKET_CTRL_VPPMASK 0x007
! 107: #define CB_SOCKET_CTRL_VPP_OFF 0x000
! 108: #define CB_SOCKET_CTRL_VPP_12V 0x001
! 109: #define CB_SOCKET_CTRL_VPP_5V 0x002
! 110: #define CB_SOCKET_CTRL_VPP_3V 0x003
! 111: #define CB_SOCKET_CTRL_VPP_XV 0x004
! 112: #define CB_SOCKET_CTRL_VPP_YV 0x005
! 113:
! 114: #define CB_SOCKET_CTRL_VCCMASK 0x070
! 115: #define CB_SOCKET_CTRL_VCC_OFF 0x000
! 116: #define CB_SOCKET_CTRL_VCC_5V 0x020
! 117: #define CB_SOCKET_CTRL_VCC_3V 0x030
! 118: #define CB_SOCKET_CTRL_VCC_XV 0x040
! 119: #define CB_SOCKET_CTRL_VCC_YV 0x050
! 120:
! 121: #define CB_SOCKET_CTRL_STOPCLK 0x080
! 122:
! 123: #define PCCBB_SOCKEVENT_BITS "\020\001CSTS\002CD1\003CD2\004PWR"
! 124: #define PCCBB_SOCKSTATE_BITS \
! 125: "\020\001CSTS\002CD1\003CD3\004PWR\00516BIT\006CB\007CINT\010NOTA" \
! 126: "\011DLOST\012BADVCC\0135v\0143v\015Xv\016Yv\0355vS\0363vS\037XvS\040YvS"
! 127:
! 128: /* PCI_BCR_INTR bits for generic PCI-CardBus bridge */
! 129: #define CB_BCR_RESET_ENABLE 0x00400000
! 130: #define CB_BCR_INTR_IREQ_ENABLE 0x00800000
! 131: #define CB_BCR_PREFETCH_MEMWIN0 0x01000000
! 132: #define CB_BCR_PREFETCH_MEMWIN1 0x02000000
! 133: #define CB_BCR_WRITE_POST_ENABLE 0x04000000
! 134:
! 135: /* TI [14][245]xx */
! 136: #define PCI12XX_MMCTRL 0x84
! 137:
! 138: /* TI 12xx/14xx/15xx (except 1250, 1251, 1251B/1450) */
! 139: #define PCI12XX_MFUNC 0x8c
! 140: #define PCI12XX_MFUNC_PIN0 0x0000000F
! 141: #define PCI12XX_MFUNC_PIN0_INTA 0x02
! 142: #define PCI12XX_MFUNC_PIN1 0x000000F0
! 143: #define PCI12XX_MFUNC_PIN1_INTB 0x20
! 144: #define PCI12XX_MFUNC_PIN2 0x00000F00
! 145: #define PCI12XX_MFUNC_PIN3 0x0000F000
! 146: #define PCI12XX_MFUNC_PIN4 0x000F0000
! 147: #define PCI12XX_MFUNC_PIN5 0x00F00000
! 148: #define PCI12XX_MFUNC_PIN6 0x0F000000
! 149:
! 150: /* PCI_CBCTRL bits for TI PCI113X */
! 151: #define PCI113X_CBCTRL_INT_SERIAL 0x040000
! 152: #define PCI113X_CBCTRL_INT_ISA 0x020000
! 153: #define PCI113X_CBCTRL_INT_MASK 0x060000
! 154: #define PCI113X_CBCTRL_RIENB 0x008000 /* Ring indicate output */
! 155: /* enable */
! 156: #define PCI113X_CBCTRL_ZVENAB 0x004000 /* ZV mode enable */
! 157: #define PCI113X_CBCTRL_PCI_IRQ_ENA 0x002000 /* PCI intr enable */
! 158: /* (funct and CSC) */
! 159: #define PCI113X_CBCTRL_PCI_INTR 0x001000 /* PCI functional intr req */
! 160: #define PCI113X_CBCTRL_PCI_CSC 0x000800 /* CSC intr route to PCI */
! 161: #define PCI113X_CBCTRL_PCI_CSC_D 0x000400 /* Unknown */
! 162: #define PCI113X_CBCTRL_SPK_ENA 0x000200 /* Speaker enable */
! 163: #define PCI113X_CBCTRL_INTR_DET 0x000100 /* Functional interrupt */
! 164: /* detect */
! 165:
! 166: /* PCI_CBCTRL bits for TI PCI12XX */
! 167: #define PCI12XX_SYSCTRL_INTRTIE 0x20000000u
! 168: #define PCI12XX_SYSCTRL_VCCPROT 0x200000
! 169: #define PCI12XX_SYSCTRL_PWRSAVE 0x000040
! 170: #define PCI12XX_SYSCTRL_SUBSYSRW 0x000020
! 171: #define PCI12XX_SYSCTRL_CB_DPAR 0x000010
! 172: #define PCI12XX_SYSCTRL_CDMA_EN 0x000008
! 173: #define PCI12XX_SYSCTRL_KEEPCLK 0x000002
! 174: #define PCI12XX_SYSCTRL_RIMUX 0x000001
! 175: #define PCI12XX_CBCTRL_CSC 0x20000000u
! 176: #define PCI12XX_CBCTRL_ASYNC_CSC 0x01000000u
! 177: #define PCI12XX_CBCTRL_INT_SERIAL 0x060000
! 178: #define PCI12XX_CBCTRL_INT_PCI_SERIAL 0x040000
! 179: #define PCI12XX_CBCTRL_INT_ISA 0x020000
! 180: #define PCI12XX_CBCTRL_INT_PCI 0x000000
! 181: #define PCI12XX_CBCTRL_INT_MASK 0x060000
! 182: #define PCI12XX_CBCTRL_RIENB 0x008000 /* Ring indicate output */
! 183: /* enable */
! 184: #define PCI12XX_CBCTRL_ZVENAB 0x004000 /* ZV mode enable */
! 185: #define PCI12XX_CBCTRL_AUD2MUX 0x000400 /* Unknown */
! 186: #define PCI12XX_CBCTRL_SPK_ENA 0x000200 /* Speaker enable */
! 187: #define PCI12XX_CBCTRL_INTR_DET 0x000100 /* Functional interrupt */
! 188: /* detect */
! 189:
! 190:
! 191: /* PCI_BCR_INTR additional bit for Rx5C46[567] */
! 192: #define CB_BCRI_RL_3E0_ENA 0x08000000
! 193: #define CB_BCRI_RL_3E2_ENA 0x10000000
! 194:
! 195: /*
! 196: * Special register definition for Toshiba ToPIC95/97
! 197: * These values are borrowed from pcmcia-cs/Linux.
! 198: */
! 199: #define TOPIC_SOCKET_CTRL 0x90
! 200: #define TOPIC_SOCKET_CTRL_SCR_IRQSEL 0x00000001 /* PCI intr */
! 201:
! 202: #define TOPIC_SLOT_CTRL 0xA0
! 203: #define TOPIC_SLOT_CTRL_SLOTON 0x00000080
! 204: #define TOPIC_SLOT_CTRL_SLOTEN 0x00000040
! 205: #define TOPIC_SLOT_CTRL_ID_LOCK 0x00000020
! 206: #define TOPIC_SLOT_CTRL_ID_WP 0x00000010
! 207: #define TOPIC_SLOT_CTRL_PORT_MASK 0x0000000C
! 208: #define TOPIC_SLOT_CTRL_PORT_SHIFT 2
! 209: #define TOPIC_SLOT_CTRL_OSF_MASK 0x00000003
! 210: #define TOPIC_SLOT_CTRL_OSF_SHIFT 0
! 211:
! 212: #define TOPIC_SLOT_CTRL_INTB 0x00002000
! 213: #define TOPIC_SLOT_CTRL_INTA 0x00001000
! 214: #define TOPIC_SLOT_CTRL_INT_MASK 0x00003000
! 215: #define TOPIC_SLOT_CTRL_CLOCK_MASK 0x00000C00
! 216: #define TOPIC_SLOT_CTRL_CLOCK_2 0x00000800 /* PCI Clock/2 */
! 217: #define TOPIC_SLOT_CTRL_CLOCK_1 0x00000400 /* PCI Clock */
! 218: #define TOPIC_SLOT_CTRL_CLOCK_0 0x00000000 /* No clock */
! 219: #define TOPIC97_SLOT_CTRL_STSIRQP 0x00000400 /* Status change intr */
! 220: /* pulse */
! 221: #define TOPIC97_SLOT_CTRL_IRQP 0x00000200 /* Function intr pulse */
! 222: #define TOPIC97_SLOT_CTRL_PCIINT 0x00000100 /* Intr routing to PCI INT */
! 223:
! 224: #define TOPIC_SLOT_CTRL_CARDBUS 0x80000000
! 225: #define TOPIC_SLOT_CTRL_VS1 0x04000000
! 226: #define TOPIC_SLOT_CTRL_VS2 0x02000000
! 227: #define TOPIC_SLOT_CTRL_SWDETECT 0x01000000
! 228:
! 229: #define TOPIC_REG_CTRL 0x00A4
! 230: #define TOPIC_REG_CTRL_RESUME_RESET 0x80000000
! 231: #define TOPIC_REG_CTRL_REMOVE_RESET 0x40000000
! 232: #define TOPIC97_REG_CTRL_CLKRUN_ENA 0x20000000
! 233: #define TOPIC97_REG_CTRL_TESTMODE 0x10000000
! 234: #define TOPIC97_REG_CTRL_IOPLUP 0x08000000
! 235: #define TOPIC_REG_CTRL_BUFOFF_PWROFF 0x02000000
! 236: #define TOPIC_REG_CTRL_BUFOFF_SIGOFF 0x01000000
! 237: #define TOPIC97_REG_CTRL_CB_DEV_MASK 0x0000F800
! 238: #define TOPIC97_REG_CTRL_CB_DEV_SHIFT 11
! 239: #define TOPIC97_REG_CTRL_RI_DISABLE 0x00000004
! 240: #define TOPIC97_REG_CTRL_CAUDIO_OFF 0x00000002
! 241: #define TOPIC_REG_CTRL_CAUDIO_INVERT 0x00000001
! 242:
! 243: /*
! 244: * Additional (subset of) Topic100 registers from
! 245: * Toshiba datasheet (Draft Rev. 01.4) 98/10/07
! 246: */
! 247: #define TOPIC100_PMCSR 0x84 /* Power mgmt ctrl/stat register */
! 248: #define TOPIC100_PMCSR_MASK 0x00000003
! 249: #define TOPIC100_PMCSR_D0 0x0
! 250:
! 251: /*
! 252: * Additional O2Micro registers
! 253: *
! 254: * 'reserved' register at 0x94/D4. allows setting read prefetch and write
! 255: * bursting. read prefetching for example makes the RME Hammerfall DSP
! 256: * working. for some bridges it is at 0x94, for others at 0xD4. it's
! 257: * ok to write to both registers on all O2 bridges.
! 258: * from Eric Still, 02Micro.
! 259: */
! 260: #define O2MICRO_RESERVED1 0x94
! 261: #define O2MICRO_RESERVED2 0xD4
! 262: #define O2MICRO_RES_READ_PREFETCH 0x02
! 263: #define O2MICRO_RES_WRITE_BURST 0x08
! 264:
! 265: #endif /* _DEV_PCI_PCCBBREG_H_ */
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