Annotation of sys/dev/pci/nofnreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: nofnreg.h,v 1.6 2003/06/02 19:08:58 jason Exp $ */
2:
3: /*
4: * Copyright (c) 2002 Jason L. Wright (jason@thought.net)
5: * All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: *
16: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
25: * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26: * POSSIBILITY OF SUCH DAMAGE.
27: *
28: * Effort sponsored in part by the Defense Advanced Research Projects
29: * Agency (DARPA) and Air Force Research Laboratory, Air Force
30: * Materiel Command, USAF, under agreement number F30602-01-2-0537.
31: *
32: */
33:
34: #define NOFN_BAR0_REGS 0x10 /* main register set */
35: #define NOFN_BAR1 0x14 /* memory space 1 */
36: #define NOFN_BAR2 0x18 /* memory space 2 */
37: #define NOFN_BAR3_PK 0x1c /* public key unit */
38:
39: #define NOFN_MIPS_PCI_BASE_0 0x0000 /* mips pci base address 0 */
40: #define NOFN_MIPS_PCI_WIN_SZ_0 0x0008 /* mips pci window size 0 */
41: #define NOFN_PCI_XLAT_0 0x0010 /* pci translation 0 */
42: #define NOFN_MIPS_PCI_BASE_1 0x0018 /* mips pci base address 1 */
43: #define NOFN_MIPS_PCI_WIN_SZ_1 0x0020 /* mips pci window size 1 */
44: #define NOFN_PCI_XLAT_1 0x0028 /* pci translation 1 */
45: #define NOFN_MIPS_SDRAM_BASE 0x0030 /* mips sdram base addr */
46: #define NOFN_MIPS_SDRAM_SZ 0x0038 /* mips sdram size */
47: #define NOFN_PCI_BARM0_SHADOW 0x0040 /* pci mbar0 shadow */
48: #define NOFN_PCI_BARM1_SHADOW 0x0050 /* pci mbar1 shadow */
49: #define NOFN_PCI_BARM_SZ 0x0060 /* size of memory window */
50: #define NOFN_XPARNT_MEM_EN 0x0068 /* enable transparent mem */
51: #define NOFN_PCI_BARR_SHADOW 0x0070 /* pci bar0 shadow, s/c regs */
52: #define NOFN_MIPS_REG_BASE 0x0078 /* mips register base */
53: #define NOFN_MAX_FREE_IDX 0x0080 /* maximum free index */
54: #define NOFN_TRAP_IN_Q 0x0090 /* enqueue core desc */
55: #define NOFN_OUT_CMPLT 0x00a0 /* output completion */
56: #define NOFN_TRAP_OUT_Q 0x00a8 /* dequeue core desc */
57: #define NOFN_CHOKE_CORE_IN_Q 0x00b0 /* choke core on input */
58: #define NOFN_DONE_BITMAP 0x00b8 /* done bitmap */
59: #define NOFN_HEAD_DESC_PTR 0x00c0 /* last core descriptor */
60: #define NOFN_TAIL_DESC_PTR 0x00c8 /* next core descriptor */
61: #define NOFN_RSLT_POST_ADR 0x00d0 /* result post address */
62: #define NOFN_SM_CTX_BASE 0x00d8 /* small session ctx base */
63: #define NOFN_DESC_BASE 0x00e8 /* core descriptor base */
64: #define NOFN_LG_CTX_BASE 0x00e0 /* large context base */
65: #define NOFN_SESSION_NUM_MASK 0x00f0 /* session number mask */
66: #define NOFN_HOST_MBOX_0 0x00f8 /* host mailbox 0 */
67: #define NOFN_REVID 0x0098 /* revision id */
68: #define NOFN_HOST_SIGNAL 0x0100 /* host signal */
69: #define NOFN_MIPS_MBOX_0 0x0108 /* mips mailbox 0 */
70: #define NOFN_MIPS_SIGNAL 0x0110 /* mips signal */
71: #define NOFN_SPINLOCK_0 0x0118 /* spinlock 0 */
72: #define NOFN_SPINLOCK_1 0x0120 /* spinlock 1 */
73: #define NOFN_PCI_INT 0x0130 /* generate a pci intr */
74: #define NOFN_PCI_INT_STAT 0x0138 /* pci interrupt status */
75: #define NOFN_PCI_INT_MASK 0x0140 /* pci interrupt mask */
76: #define NOFN_MIPS_INT 0x0148 /* mips interrupt trigger */
77: #define NOFN_MIPS_INT_STAT 0x0150 /* mips interrupt status */
78: #define NOFN_SDRAM_CFG 0x0168 /* sdram configuration */
79: #define NOFN_ENDIAN_CFG 0x0170 /* endian configuration */
80: #define NOFN_EPT 0x0178 /* endian private xfer */
81: #define NOFN_MIPS_RST 0x0180 /* mips reset */
82: #define NOFN_EEPROM_DATA_0 0x0188 /* eeprom data 0 */
83: #define NOFN_EEPROM_DATA_1 0x0190 /* eeprom data 1 */
84: #define NOFN_EEPROM_DATA_2 0x0198 /* eeprom data 2 */
85: #define NOFN_EEPROM_DATA_3 0x01a0 /* eeprom data 3 */
86: #define NOFN_CHIP_CFG 0x01d8 /* chip configuration */
87: #define NOFN_SCRATCH_0 0x01e0 /* scratch 0 */
88: #define NOFN_SCRATCH_1 0x01e8 /* scratch 1 */
89: #define NOFN_SCRATCH_2 0x01f0 /* scratch 2 */
90: #define NOFN_SCRATCH_3 0x01f8 /* scratch 3 */
91: #define NOFN_CMD_RING_CTL 0x0200 /* command ring control */
92: #define NOFN_CMD_RING_BASE 0x0208 /* command ring base */
93: #define NOFN_CMD_RING_LEN 0x0210 /* command ring length */
94: #define NOFN_CMD_RING_HEAD 0x0218 /* command ring head */
95: #define NOFN_CMD_RING_TAIL 0x0220 /* command ring tail */
96: #define NOFN_DST_RING_CTL 0x0230 /* dest ring control */
97: #define NOFN_DST_RING_BASE 0x0238 /* dest ring base */
98: #define NOFN_DST_RING_LEN 0x0240 /* dest ring length */
99: #define NOFN_DST_RING_HEAD 0x0248 /* dest ring head */
100: #define NOFN_DST_RING_TAIL 0x0250 /* dest ring tail */
101: #define NOFN_RSLT_RING_CTL 0x0258 /* result ring control */
102: #define NOFN_RSLT_RING_BASE 0x0260 /* result ring base */
103: #define NOFN_RSLT_RING_LEN 0x0268 /* result ring length */
104: #define NOFN_RSLT_RING_HEAD 0x0270 /* result ring head */
105: #define NOFN_RSLT_RING_TAIL 0x0278 /* result ring tail */
106: #define NOFN_SRC_RING_CTL 0x0288 /* src ring control */
107: #define NOFN_SRC_RING_BASE 0x0290 /* src ring base */
108: #define NOFN_SRC_RING_LEN 0x0298 /* src ring len */
109: #define NOFN_SRC_RING_HEAD 0x02a0 /* src ring head */
110: #define NOFN_SRC_RING_TAIL 0x02a8 /* src ring tail */
111: #define NOFN_FREE_RING_CTL 0x02b8 /* free ring control */
112: #define NOFN_FREE_RING_BASE 0x02c0 /* free ring base */
113: #define NOFN_FREE_RING_LEN 0x02c8 /* free ring len */
114: #define NOFN_FREE_RING_HEAD 0x02d0 /* free ring head */
115: #define NOFN_FREE_RING_TAIL 0x02d8 /* free ring tail */
116: #define NOFN_ECC_TEST 0x02e0 /* ecc test */
117: #define NOFN_ECC_SNGL_ADR 0x02e8 /* ecc singlebit error addr */
118: #define NOFN_ECC_SNGL_ECC 0x02f0 /* ecc singlebit error bits */
119: #define NOFN_ECC_SNGL_CNT 0x02f8 /* ecc singlebit error count */
120: #define NOFN_ECC_MULTI_ADR 0x0300 /* ecc multibit error addr */
121: #define NOFN_ECC_MULTI_ECC 0x0308 /* ecc multibit error bits */
122: #define NOFN_ECC_MULTI_DATAL 0x0310 /* ecc multibit err data lo */
123: #define NOFN_ECC_MULTI_DATAH 0x0318 /* ecc multibit err data hi */
124: #define NOFN_MIPS_ERR_ADR 0x0320 /* mips parity error addr */
125: #define NOFN_MIPS_ERR_DATA 0x0328 /* mips parity error data */
126: #define NOFN_MIPS_ERR_PAR 0x0330 /* mips parity error bits */
127: #define NOFN_MIPS_PAR_TEST 0x0338 /* mips parity test */
128: #define NOFN_MIPS_MBOX_1 0x0340 /* mips mailbox 1 */
129: #define NOFN_MIPS_MBOX_2 0x0348 /* mips mailbox 2 */
130: #define NOFN_MIPS_MBOX_3 0x0350 /* mips mailbox 3 */
131: #define NOFN_HOST_MBOX_1 0x0358 /* host mailbox 1 */
132: #define NOFN_HOST_MBOX_2 0x0360 /* host mailbox 2 */
133: #define NOFN_HOST_MBOX_3 0x0368 /* host mailbox 3 */
134: #define NOFN_MIPS_INT_0_MASK 0x0400 /* mips intr mask 0 */
135: #define NOFN_MIPS_INT_1_MASK 0x0408 /* mips intr mask 1 */
136: #define NOFN_MIPS_INT_2_MASK 0x0410 /* mips intr mask 2 */
137: #define NOFN_MIPS_PCI_RD_ERRADR 0x0418 /* failed read address */
138: #define NOFN_MIPS_PCI_WR_ERRADR 0x0420 /* failed write address */
139: #define NOFN_MIPS_EP0_LMT 0x0428 /* mips private limit */
140: #define NOFN_PCI_INIT_ERR_ADR 0x0430 /* pci failure address */
141: #define NOFN_ECC_SNGL_DATAL 0x0438 /* ecc singlebit err dat lo */
142: #define NOFN_ECC_SNGL_DATAH 0x0440 /* ecc singlebit err dat hi */
143: #define NOFN_GPDMA_DATA_0 0x0480 /* gpdma data 0 */
144: #define NOFN_GPDMA_DATA_1 0x0488 /* gpdma data 1 */
145: #define NOFN_GPDMA_DATA_2 0x0490 /* gpdma data 2 */
146: #define NOFN_GPDMA_DATA_3 0x0498 /* gpdma data 3 */
147: #define NOFN_GPDMA_DATA_4 0x04a0 /* gpdma data 4 */
148: #define NOFN_GPDMA_DATA_5 0x04a8 /* gpdma data 5 */
149: #define NOFN_GPDMA_DATA_6 0x04b0 /* gpdma data 6 */
150: #define NOFN_GPDMA_DATA_7 0x04b8 /* gpdma data 7 */
151: #define NOFN_GPDMA_DATA_8 0x04c0 /* gpdma data 8 */
152: #define NOFN_GPDMA_DATA_9 0x04c8 /* gpdma data 9 */
153: #define NOFN_GPDMA_DATA_10 0x04d0 /* gpdma data 10 */
154: #define NOFN_GPDMA_DATA_11 0x04d8 /* gpdma data 11 */
155: #define NOFN_GPDMA_DATA_12 0x04e0 /* gpdma data 12 */
156: #define NOFN_GPDMA_DATA_13 0x04e8 /* gpdma data 13 */
157: #define NOFN_GPDMA_DATA_14 0x04f0 /* gpdma data 14 */
158: #define NOFN_GPDMA_DATA_15 0x04f8 /* gpdma data 15 */
159: #define NOFN_GPDMA_CTL 0x0500 /* gpdma control */
160: #define NOFN_GPDMA_ADR 0x0508 /* gpdma address */
161: #define NOFN_MIPS_PK_BASE 0x0510 /* mips pk base address */
162: #define NOFN_PCI_BAR3_SHADOW 0x0518 /* pci bar3 shadow */
163: #define NOFN_AES_ROUNDS 0x0520 /* number of rounds in AES */
164: #define NOFN_MIPS_INIT 0x0530 /* mips init */
165: #define NOFN_MIPS_INIT_CTL 0x0528 /* mips init control */
166: #define NOFN_UART_TX 0x0538 /* uart tx data */
167: #define NOFN_UART_RX 0x0540 /* uart rx data */
168: #define NOFN_UART_CLK_LOW 0x0548 /* uart clock, low bits */
169: #define NOFN_UART_CLK_HIGH 0x0550 /* uart clock, high bits */
170: #define NOFN_UART_STAT 0x0558 /* uart status */
171: #define NOFN_MIPS_FLASH_BASE 0x0560 /* mips flash base addr */
172: #define NOFN_MIPS_FLASH_SZ 0x0568 /* mips flash size */
173: #define NOFN_MIPS_FLASH_XLATE 0x0570 /* mips address translation */
174: #define NOFN_MIPS_SRAM_BASE 0x0578 /* mips sram base address */
175: #define NOFN_MIPS_SRAM_SZ 0x0580 /* mips sram size */
176: #define NOFN_MIPS_SRAM_XLATE 0x0588 /* mips sram xlate */
177: #define NOFN_MIPS_MEM_LOCK 0x0590 /* mips memory lock */
178: #define NOFN_MIPS_SDRAM2_BASE 0x0598 /* mips sdram2 base addr */
179: #define NOFN_MIPS_SDRAM2_SZ 0x05a0 /* mips sdram2 size */
180: #define NOFN_MIPS_EPO2_LMT 0x05a8 /* address boundary */
181:
182: #define REVID_7851_1 0x00140000 /* 7851, first silicon */
183: #define REVID_7851_2 0x00140001 /* 7851, second silicon */
184: #define REVID_7814_7854_1 0x00140002 /* 7814/7854, first silicon */
185: #define REVID_8154_1 0x00180000 /* 8154, first silicon */
186: #define REVID_8065_1 0x00160000 /* 8065, first silicon */
187: #define REVID_8165_1 0x00170000 /* 8165, first silicon */
188:
189: #define PCIINTMASK_PK 0x80000000 /* pk processor idle */
190: #define PCIINTMASK_RNGRDY 0x40000000 /* pk rng has 8 32bit words */
191: #define PCIINTMASK_MIPSINT 0x00080000 /* mips interrupt */
192: #define PCIINTMASK_ERR_OUT 0x00010000 /* err: outbound dma */
193: #define PCIINTMASK_ERR_FREE 0x00008000 /* err: free descriptor */
194: #define PCIINTMASK_ERR_DEST 0x00004000 /* err: dest descriptor */
195: #define PCIINTMASK_ERR_RES 0x00002000 /* err: result cycle */
196: #define PCIINTMASK_ERR_RESP 0x00001000 /* err: post address cycle */
197: #define PCIINTMASK_DESCOVF 0x00000800 /* descriptor overflow */
198: #define PCIINTMASK_RESDONE 0x00000400 /* result done */
199: #define PCIINTMASK_DESTINV 0x00000200 /* destination invalidated */
200: #define PCIINTMASK_POOLINV 0x00000100 /* free desc invalidated */
201: #define PCIINTMASK_ERR_CMD 0x00000080 /* pci error fetching cmd */
202: #define PCIINTMASK_ERR_SRC 0x00000040 /* pci error fetching src */
203: #define PCIINTMASK_ERR_IN 0x00000020 /* pci error during input */
204: #define PCIINTMASK_ERR_MULTI 0x00000010 /* multibit ecc error */
205: #define PCIINTMASK_MIPSPAR 0x00000004 /* mips parity error */
206: #define PCIINTMASK_MIPSPCI 0x00000002 /* write to pciint register */
207: #define PCIINTMASK_FREE_E 0x00000001 /* free-pool empty */
208:
209: #define PCIINTSTAT_PK 0x80000000 /* pk processor idle */
210: #define PCIINTSTAT_RNGRDY 0x40000000 /* pk rng has 8 32bit words */
211: #define PCIINTSTAT_MIPSINT 0x00080000 /* mips interrupt */
212: #define PCIINTSTAT_ERR_OUT 0x00010000 /* err: outbound dma */
213: #define PCIINTSTAT_ERR_FREE 0x00008000 /* err: free descriptor */
214: #define PCIINTSTAT_ERR_DEST 0x00004000 /* err: dest descriptor */
215: #define PCIINTSTAT_ERR_RES 0x00002000 /* err: result cycle */
216: #define PCIINTSTAT_ERR_RESP 0x00001000 /* err: post address cycle */
217: #define PCIINTSTAT_DESCOVF 0x00000800 /* descriptor overflow */
218: #define PCIINTSTAT_RESDONE 0x00000400 /* result done */
219: #define PCIINTSTAT_DESTINV 0x00000200 /* destination invalidated */
220: #define PCIINTSTAT_POOLINV 0x00000100 /* free desc invalidated */
221: #define PCIINTSTAT_ERR_CMD 0x00000080 /* pci error fetching cmd */
222: #define PCIINTSTAT_ERR_SRC 0x00000040 /* pci error fetching src */
223: #define PCIINTSTAT_ERR_IN 0x00000020 /* pci error during input */
224: #define PCIINTSTAT_ERR_MULTI 0x00000010 /* multibit ecc error */
225: #define PCIINTSTAT_MIPSPAR 0x00000004 /* mips parity error */
226: #define PCIINTSTAT_MIPSPCI 0x00000002 /* write to pciint register */
227: #define PCIINTSTAT_FREE_E 0x00000001 /* free-pool empty */
228:
229: #define NOFN_PK_WIN_0 0x0000 /* big endian byte and words */
230: #define NOFN_PK_WIN_1 0x2000 /* big endian byte, little endian words */
231: #define NOFN_PK_WIN_2 0x4000 /* little endian byte and words */
232: #define NOFN_PK_WIN_3 0x6000 /* little endian byte, big endian words */
233:
234: #define NOFN_PK_REGADDR(win,r,i) \
235: ((win) | (((r) & 0xf) << 7) | (((i) & 0x1f) << 2))
236:
237: #define NOFN_PK_LENADDR(r) (0x1000 + ((r) << 2))
238: #define NOFN_PK_LENMASK 0x000007ff /* mask of length bits */
239:
240: #define NOFN_PK_RNGFIFO_BEGIN 0x1080
241: #define NOFN_PK_RNGFIFO_END 0x10bc
242: #define NOFN_PK_INSTR_BEGIN 0x1100
243: #define NOFN_PK_INSTR_END 0x12fc
244:
245: #define NOFN_PK_CR 0x1fd4 /* command */
246: #define NOFN_PK_SR 0x1fd8 /* status */
247: #define NOFN_PK_IER 0x1fdc /* interrupt enable */
248: #define NOFN_PK_RNC 0x1fe0 /* random number config */
249: #define NOFN_PK_CFG1 0x1fe4 /* config1 */
250: #define NOFN_PK_CFG2 0x1fe8 /* config2 */
251: #define NOFN_PK_CHIPID 0x1fec /* chipid */
252: #define NOFN_PK_SCR 0x1ff0 /* stack content */
253:
254: #define PK_CR_OFFSET_M 0x000001fc /* instruction offset mask */
255: #define PK_CR_OFFSET_S 2 /* instruction offset shift */
256:
257: #define PK_SR_DONE 0x00008000 /* proc is idle */
258: #define PK_SR_RRDY 0x00004000 /* random number ready */
259: #define PK_SR_UFLOW 0x00001000 /* random number underflow */
260: #define PK_SR_CARRY 0x00000008 /* alu carry bit */
261:
262: #define PK_IER_DONE 0x00008000 /* intr when alu is idle */
263: #define PK_IER_RRDY 0x00004000 /* intr when rng ready */
264:
265: #define PK_RNC_FST_SCALER 0x00000f00 /* first prescaler */
266: #define PK_RNC_OUT_SCALER 0x00000080 /* output prescaler */
267:
268: #define PK_CFG1_RESET 0x00000001 /* reset pk unit */
269:
270: #define PK_CFG2_ALU_ENA 0x00000002 /* enable alu */
271: #define PK_CFG2_RNG_ENA 0x00000001 /* enable rng */
272:
273: /* alu registers are 1024 bits wide, but must be addressed by word. */
274: union nofn_pk_reg {
275: u_int8_t b[128];
276: u_int32_t w[32];
277: };
278:
279: #define PK_OP_DONE 0x80000000 /* end of program */
280: #define PK_OPCODE_MASK 0x7c000000 /* opcode mask */
281: #define PK_OPCODE_MODEXP 0x00000000 /* modular exponentiation */
282: #define PK_OPCODE_MODMUL 0x04000000 /* modular multiplication */
283: #define PK_OPCODE_MODRED 0x08000000 /* modular reduction */
284: #define PK_OPCODE_MODADD 0x0c000000 /* modular addition */
285: #define PK_OPCODE_MODSUB 0x10000000 /* modular subtraction */
286: #define PK_OPCODE_ADD 0x14000000 /* addition */
287: #define PK_OPCODE_SUB 0x18000000 /* subtraction */
288: #define PK_OPCODE_ADDC 0x1c000000 /* addition with carry */
289: #define PK_OPCODE_SUBC 0x20000000 /* subtraction with carry */
290: #define PK_OPCODE_MULT 0x24000000 /* 2048bit multiplication */
291: #define PK_OPCODE_SR 0x28000000 /* shift right */
292: #define PK_OPCODE_SL 0x2c000000 /* shift left */
293: #define PK_OPCODE_INC 0x30000000 /* increment */
294: #define PK_OPCODE_DEC 0x34000000 /* decrement */
295: #define PK_OPCODE_TAG 0x38000000 /* set length tag */
296: #define PK_OPCODE_BRANCH 0x3c000000 /* jump to insn */
297: #define PK_OPCODE_CALL 0x40000000 /* push addr and jump */
298: #define PK_OPCODE_RETURN 0x44000000 /* pop addr and return */
299:
300: #define PK_OP_RD_SHIFT 21
301: #define PK_OP_RA_SHIFT 16
302: #define PK_OP_RB_SHIFT 11
303: #define PK_OP_RM_SHIFT 6
304: #define PK_OP_R_MASK 0x1f
305: #define PK_OP_LEN_MASK 0xffff
306:
307: #define NOFN_PK_INSTR(done,op,rd,ra,rb,rm) \
308: ((done) | (op) | \
309: (((rd) & PK_OP_R_MASK) << PK_OP_RD_SHIFT) | \
310: (((ra) & PK_OP_R_MASK) << PK_OP_RA_SHIFT) | \
311: (((rb) & PK_OP_R_MASK) << PK_OP_RB_SHIFT) | \
312: (((rm) & PK_OP_R_MASK) << PK_OP_RM_SHIFT))
313:
314: /* shift left, shift right, tag */
315: #define NOFN_PK_INSTR2(done,op,rd,ra,len) \
316: ((done) | (op) | \
317: (((rd) & PK_OP_R_MASK) << PK_OP_RD_SHIFT) | \
318: (((ra) & PK_OP_R_MASK) << PK_OP_RA_SHIFT) | \
319: ((len) & PK_OP_LEN_MASK))
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