Annotation of sys/dev/pci/noctreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: noctreg.h,v 1.8 2003/06/02 19:08:58 jason Exp $ */
2:
3: /*
4: * Copyright (c) 2002 Jason L. Wright (jason@thought.net)
5: * All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: *
16: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
25: * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26: * POSSIBILITY OF SUCH DAMAGE.
27: *
28: * Effort sponsored in part by the Defense Advanced Research Projects
29: * Agency (DARPA) and Air Force Research Laboratory, Air Force
30: * Materiel Command, USAF, under agreement number F30602-01-2-0537.
31: *
32: */
33:
34: #define NOCT_BAR0 0x10 /* PCI base address */
35:
36: #define NOCT_BRDG_ENDIAN 0x0000 /* bridge endian mode */
37: #define NOCT_BRDG_TIMER_PRESET 0x0004 /* bridge timer preset */
38: #define NOCT_BRDG_STAT 0x0008 /* bridge status */
39: #define NOCT_BRDG_CTL 0x000c /* bridge control */
40: #define NOCT_BRDG_TIMR 0x0010 /* bridge timer */
41: #define NOCT_BRDG_TEST 0x0014 /* bridge test */
42: #define NOCT_BRDG_RPMR 0x0018 /* bridge read ptr mirror */
43: #define NOCT_PKH_TEST0 0x4000 /* pkh test 0 */
44: #define NOCT_PKH_TEST1 0x4004 /* pkh test 1 */
45: #define NOCT_PKH_Q_LEN 0x4008 /* pkh queue length */
46: #define NOCT_PKH_Q_PTR 0x400c /* pkh queue ptrs */
47: #define NOCT_PKH_Q_BASE_HI 0x4010 /* pkh queue base, msw */
48: #define NOCT_PKH_Q_BASE_LO 0x4014 /* pkh queue base, lsw */
49: #define NOCT_PKH_IER 0x4018 /* pkh intr enable */
50: #define NOCT_PKH_CSR 0x401c /* pkh control/status */
51: #define NOCT_PKH_SKS_DATA 0x4020 /* pkh secure key data */
52: #define NOCT_PKH_SKS_CTRL 0x4024 /* pkh secure key ctrl */
53: #define NOCT_PKH_CMDB_0 0x40e0 /* pkh command block 0 */
54: #define NOCT_PKH_CMDB_1 0x40e4 /* pkh command block 1 */
55: #define NOCT_PKH_CMDB_2 0x40e8 /* pkh command block 2 */
56: #define NOCT_PKH_CMDB_3 0x40ec /* pkh command block 3 */
57: #define NOCT_PKH_CMDB_4 0x40f0 /* pkh command block 4 */
58: #define NOCT_PKH_CMDB_5 0x40f4 /* pkh command block 5 */
59: #define NOCT_PKH_CMDB_6 0x40f8 /* pkh command block 6 */
60: #define NOCT_PKH_CMDB_7 0x40fc /* pkh command block 7 */
61: #define NOCT_PKH_BNCACHE_START 0x5000 /* pkh bignumber cache start */
62: #define NOCT_PKH_BNCACHE_END 0x5fff /* pkh bigbumber cache end */
63: #define NOCT_EA_TEST_1 0x8000 /* e/a test 1 */
64: #define NOCT_EA_TEST_0 0x8004 /* e/a test 0 */
65: #define NOCT_EA_Q_LEN 0x8008 /* e/a cmd queue len */
66: #define NOCT_EA_Q_PTR 0x800c /* e/a cmd queue ptr */
67: #define NOCT_EA_Q_BASE_HI 0x8010 /* e/a cmd queue bar 1 */
68: #define NOCT_EA_Q_BASE_LO 0x8014 /* e/a cmd queue bar 0 */
69: #define NOCT_EA_IER 0x8018 /* e/a intr enable */
70: #define NOCT_EA_CSR 0x801c /* e/a control/status */
71: #define NOCT_EA_CTX_DAT_1 0x8020 /* e/a context data 1 */
72: #define NOCT_EA_CTX_DAT_0 0x8024 /* e/a context data 0 */
73: #define NOCT_EA_CTX_ADDR 0x8028 /* e/a context address */
74: #define NOCT_EA_SDRAM_CFG 0x802c /* e/a sdram config */
75: #define NOCT_RNG_TOD 0xc000 /* rng time of day */
76: #define NOCT_RNG_TOD_SCALE 0xc008 /* rng pre-scale */
77: #define NOCT_RNG_TOD_READ 0xc010 /* rng time of day (read) */
78: #define NOCT_RNG_X917_KEY1 0xc018 /* rng x9.17 key 1 */
79: #define NOCT_RNG_X917_KEY2 0xc020 /* rng x9.17 key 2 */
80: #define NOCT_RNG_HOSTSEED 0xc028 /* rng host seed */
81: #define NOCT_RNG_SAMPBIAS 0xc030 /* rng intrl seed gen/bias */
82: #define NOCT_RNG_EXTCLK_SCALE 0xc038 /* rng extrn clock scale */
83: #define NOCT_RNG_WRITE 0xc040 /* rng write pointer */
84: #define NOCT_RNG_SEEDSAMP 0xc048 /* rng seed sample */
85: #define NOCT_RNG_LFSRDIAG 0xc050 /* rng lfsr diagnostics */
86: #define NOCT_RNG_LFSRHIST_1 0xc058 /* rng lfsr history 1 */
87: #define NOCT_RNG_LFSRHIST_2 0xc060 /* rng lfsr history 2 */
88: #define NOCT_RNG_LFSRHIST_3 0xc068 /* rng lfsr history 3 */
89: #define NOCT_RNG_LFSRHIST_4 0xc070 /* rng lfsr history 4 */
90: #define NOCT_RNG_CTL 0xc078 /* rng control */
91: #define NOCT_RNG_TEST_1 0xd000 /* rng test 1 */
92: #define NOCT_RNG_TEST_0 0xd004 /* rng test 0 */
93: #define NOCT_RNG_Q_LEN 0xd008 /* rng queue length */
94: #define NOCT_RNG_Q_PTR 0xd00c /* rng queue pointer */
95: #define NOCT_RNG_Q_BASE_HI 0xd010 /* rng bar1 */
96: #define NOCT_RNG_Q_BASE_LO 0xd014 /* rng bar0 */
97: #define NOCT_RNG_CSR 0xd018 /* rng control/status */
98:
99: /* NOCT_BRDG_STAT */
100: #define BRDGSTS_PKP_INT 0x80000000 /* pkp interrupt */
101: #define BRDGSTS_CCH_INT 0x40000000 /* cch interrupt */
102: #define BRDGSTS_RNG_INT 0x20000000 /* rng interrupt */
103: #define BRDGSTS_BRG_INT 0x10000000 /* bridge interrupt */
104: #define BRDGSTS_TMR_INT 0x08000000 /* timer interrupt */
105: #define BRDGSTS_CCH_ENA 0x01000000 /* mirror from e/a */
106: #define BRDGSTS_CCH_BSY 0x00800000 /* mirror from e/a */
107: #define BRDGSTS_CCH_ERR 0x00400000 /* mirror from e/a */
108: #define BRDGSTS_CCH_RD_PEND 0x00200000 /* mirror from e/a */
109: #define BRDGSTS_CCH_WR_PEND 0x00100000 /* mirror from e/a */
110: #define BRDGSTS_PKH_ENA 0x00080000 /* mirror from pkh */
111: #define BRDGSTS_PKH_BSY 0x00040000 /* mirror from pkh */
112: #define BRDGSTS_PKH_ERR 0x00020000 /* mirror from pkh */
113: #define BRDGSTS_PKH_SKS 0x00010000 /* mirror from pkh */
114: #define BRDGSTS_HRESP_ERR 0x00002000 /* AHB slave HRESP error */
115: #define BRDGSTS_HBURST_ERR 0x00001000 /* ccm, illegal burst */
116: #define BRDGSTS_HSIZE_ERR 0x00000800 /* ccm, illegal size */
117: #define BRDGSTS_PCIACC_ERR 0x00000400 /* pci access error */
118: #define BRDGSTS_RSVMEM_ERR 0x00000200 /* reserved access */
119: #define BRDGSTS_TRCVFIFO_PERR 0x00000100 /* CS6464AF parity error */
120: #define BRDGSTS_PCIPERR 0x00000080 /* host parity error */
121:
122: /* NOCT_BRDG_CTL */
123: #define BRDGCTL_PKIRQ_ENA 0x80000000 /* pkh interrupt enable */
124: #define BRDGCTL_EAIRQ_ENA 0x40000000 /* ea interrupt enable */
125: #define BRDGCTL_RNIRQ_ENA 0x20000000 /* rng interrupt enable */
126: #define BRDGCTL_BIRQ_ENA 0x10000000 /* bridge interrupt enable */
127: #define BRDGCTL_TIRQ_ENA 0x08000000 /* timer interrupt enable */
128: #define BRDGCTL_TIMER_ENA 0x00000001 /* enable timer */
129:
130: /* NOCT_PKH_Q_LEN */
131: #define PKHQLEN_MASK 0x0000000f /* queue length, 2^n */
132:
133: /* NOCT_PKH_Q_PTR */
134: #define PKHQPTR_READ_M 0x7fff0000 /* read mask */
135: #define PKHQPTR_READ_S 16 /* read shift */
136: #define PKHQPTR_WRITE_M 0x00007fff /* write mask */
137: #define PKHQPTR_WRITE_S 0 /* write shift */
138:
139: /* NOCT_PKH_IER */
140: #define PKHIER_CMDSI 0x00020000 /* cmd successful, SI */
141: #define PKHIER_SKSWR 0x00010000 /* sks write op done */
142: #define PKHIER_SKSOFF 0x00008000 /* sks offset error */
143: #define PKHIER_PKHLEN 0x00004000 /* invalid data length */
144: #define PKHIER_PKHOPCODE 0x00002000 /* invalid opcode */
145: #define PKHIER_BADQBASE 0x00001000 /* base queue base */
146: #define PKHIER_LOADERR 0x00000800 /* bus error during load */
147: #define PKHIER_STOREERR 0x00000400 /* bus error during store */
148: #define PKHIER_CMDERR 0x00000200 /* bus error during cmd */
149: #define PKHIER_ILL 0x00000100 /* illegal access */
150: #define PKHIER_PKERESV 0x00000080 /* pke reserved */
151: #define PKHIER_PKEWDT 0x00000040 /* pke mul inv watchdog */
152: #define PKHIER_PKENOTPRIME 0x00000020 /* pke not relatively prime */
153: #define PKHIER_PKE_B 0x00000010 /* pke bad 'b' error */
154: #define PKHIER_PKE_A 0x00000008 /* pke bad 'a' error */
155: #define PKHIER_PKE_M 0x00000004 /* pke bad 'm' error */
156: #define PKHIER_PKE_R 0x00000002 /* pke bad 'r' error */
157: #define PKHIER_PKEOPCODE 0x00000001 /* pke bad opcode */
158:
159: /* NOCT_PKH_CSR */
160: #define PKHCSR_PKH_ENA 0x80000000 /* enable pkh */
161: #define PKHCSR_PKH_BUSY 0x40000000 /* pkh busy */
162: #define PKHCSR_PKE_GO 0x20000000 /* pke go input */
163: #define PKHCSR_PKE_BUSY 0x10000000 /* pke busy output */
164: #define PKHCSR_LINENO 0x0f000000 /* pke error opcode */
165: #define PKHCSR_CMDSI 0x00020000 /* cmd successful, SI */
166: #define PKHCSR_SKSWR 0x00010000 /* sks write op done */
167: #define PKHCSR_SKSOFF 0x00008000 /* sks offset error */
168: #define PKHCSR_PKHLEN 0x00004000 /* invalid data length */
169: #define PKHCSR_PKHOPCODE 0x00002000 /* invalid opcode */
170: #define PKHCSR_BADQBASE 0x00001000 /* base queue base */
171: #define PKHCSR_LOADERR 0x00000800 /* bus error during load */
172: #define PKHCSR_STOREERR 0x00000400 /* bus error during store */
173: #define PKHCSR_CMDERR 0x00000200 /* bus error during cmd */
174: #define PKHCSR_ILL 0x00000100 /* illegal access */
175: #define PKHCSR_PKERESV 0x00000080 /* pke reserved */
176: #define PKHCSR_PKEWDT 0x00000040 /* pke mul inv watchdog */
177: #define PKHCSR_PKENOTPRIME 0x00000020 /* pke not relatively prime */
178: #define PKHCSR_PKE_B 0x00000010 /* pke bad 'b' error */
179: #define PKHCSR_PKE_A 0x00000008 /* pke bad 'a' error */
180: #define PKHCSR_PKE_M 0x00000004 /* pke bad 'm' error */
181: #define PKHCSR_PKE_R 0x00000002 /* pke bad 'r' error */
182: #define PKHCSR_PKEOPCODE 0x00000001 /* pke bad opcode */
183:
184: /* NOCT_PKH_SKS_CTRL */
185: #define PKHSKS_GO 0x80000000 /* pkhsks busy */
186: #define PKHSKS_PROMERR 0x40000000 /* prom protocol error */
187: #define PKHSKS_ACCERR 0x20000000 /* access error */
188: #define PKHSKS_LOCMASK 0x00003000 /* location mask: */
189: #define PKHSKS_LOC_FROMPROM 0x00002000
190: #define PKHSKS_LOC_CACHEONLY 0x00001000
191: #define PKHSKS_ADDR 0x00000fff /* address mask */
192:
193: /*
194: * public key structures
195: */
196: /* opcodes/flags */
197: #define PKH_OP_CODE_MASK 0xf0000000 /* opcode mask */
198: #define PKH_OP_CODE_MOD 0x00000000 /* a mod m */
199: #define PKH_OP_CODE_RMOD 0x10000000 /* R mod m */
200: #define PKH_OP_CODE_ADD 0x20000000 /* (a + b) mod m */
201: #define PKH_OP_CODE_SUB 0x30000000 /* (a - b) mod m */
202: #define PKH_OP_CODE_ADDINV 0x40000000 /* -a mod m */
203: #define PKH_OP_CODE_MUL 0x50000000 /* (a * b) mod m */
204: #define PKH_OP_CODE_MULINV 0x60000000 /* 1/a mod m */
205: #define PKH_OP_CODE_EXP 0x70000000 /* g^e mod m */
206: #define PKH_OP_CODE_LOAD 0x80000000 /* load bn cache */
207: #define PKH_OP_CODE_STORE 0x90000000 /* store bn cache */
208: #define PKH_OP_CODE_RSAPRIV 0xa0000000 /* rsa private key op */
209: #define PKH_OP_CODE_DSASIGN 0xb0000000 /* dsa sign op */
210: #define PKH_OP_CODE_NOP 0xf0000000 /* no-op */
211: #define PKH_OP_SI 0x08000000 /* set interrupt */
212:
213: /* pkh arithmetic commands */
214: struct noct_pkh_cmd_arith {
215: volatile u_int32_t op; /* opcode/si, 0x0 - 0x7 */
216: volatile u_int32_t r; /* r offset */
217: volatile u_int32_t m; /* m length, m offset */
218: volatile u_int32_t a; /* a length, a offset */
219: volatile u_int32_t b; /* b length, b offset */
220: volatile u_int32_t c; /* c offset */
221: volatile u_int32_t unused[2]; /* reserved */
222: };
223:
224: /* pkh load/store bn cache commands */
225: struct noct_pkh_cmd_cache {
226: volatile u_int32_t op; /* opcode/si, 0x8-0x9 */
227: volatile u_int32_t r; /* r offset */
228: volatile u_int32_t addrhi; /* host address, msw */
229: volatile u_int32_t addrlo; /* host address, lsw */
230: volatile u_int32_t len; /* data length (0-4096) */
231: volatile u_int32_t unused[3]; /* reserved */
232: };
233:
234: /* pkh rsa private command */
235: struct noct_pkh_cmd_rsapriv {
236: volatile u_int32_t op; /* opcode/si, 0xa */
237: volatile u_int32_t par; /* n, keylen, sksoffset */
238: volatile u_int32_t unused[6]; /* reserved */
239: };
240:
241: /* pkh dsa sign command */
242: struct noct_pkh_cmd_dsasign {
243: volatile u_int32_t op; /* opcode/si, 0xb */
244: volatile u_int32_t par; /* n, keylen, sksoffset */
245: volatile u_int32_t unused[6]; /* reserved */
246: };
247:
248: /* pkh nop command */
249: struct noct_pkh_cmd_nop {
250: volatile u_int32_t op; /* opcode/si, 0xf */
251: volatile u_int32_t unused[7]; /* reserved */
252: };
253:
254: /* pkh generic command */
255: union noct_pkh_cmd {
256: struct noct_pkh_cmd_arith arith;
257: struct noct_pkh_cmd_cache cache;
258: struct noct_pkh_cmd_rsapriv rsapriv;
259: struct noct_pkh_cmd_dsasign dsasign;
260: struct noct_pkh_cmd_nop nop;
261: };
262:
263: /* NOCT_EA_Q_LEN */
264: #define EAQLEN_MASK 0x0000000f /* queue length, 2^n */
265:
266: /* NOCT_EA_Q_PTR */
267: #define EAQPTR_READ_M 0x7fff0000 /* read mask */
268: #define EAQPTR_READ_S 16 /* read shift */
269: #define EAQPTR_WRITE_M 0x00007fff /* write mask */
270: #define EAQPTR_WRITE_S 0 /* write shift */
271:
272: /* NOCT_EA_IER */
273: #define EAIER_QALIGN 0x00008000 /* queue alignment */
274: #define EAIER_CMDCMPL 0x00004000 /* command complete */
275: #define EAIER_OPERR 0x00002000 /* opcode error */
276: #define EAIER_CMDREAD 0x00001000 /* command read error */
277: #define EAIER_CMDWRITE 0x00000800 /* command write error */
278: #define EAIER_DATAREAD 0x00000400 /* data read error */
279: #define EAIER_DATAWRITE 0x00000200 /* data write error */
280: #define EAIER_INTRNLLEN 0x00000100 /* internal data length err */
281: #define EAIER_EXTRNLLEN 0x00000080 /* external data length err */
282: #define EAIER_DESBLOCK 0x00000040 /* des block size error */
283: #define EAIER_DESKEY 0x00000020 /* des key error */
284: #define EAIER_ILL 0x00000001 /* illegal access */
285:
286: /* NOCT_EA_CSR */
287: #define EACSR_ENABLE 0x80000000 /* e/a enable */
288: #define EACSR_BUSY 0x40000000 /* e/a busy */
289: #define EACSR_QALIGN 0x00008000 /* queue alignment */
290: #define EACSR_CMDCMPL 0x00004000 /* command complete */
291: #define EACSR_OPERR 0x00002000 /* opcode error */
292: #define EACSR_CMDREAD 0x00001000 /* command read error */
293: #define EACSR_CMDWRITE 0x00000800 /* command write error */
294: #define EACSR_DATAREAD 0x00000400 /* data read error */
295: #define EACSR_DATAWRITE 0x00000200 /* data write error */
296: #define EACSR_INTRNLLEN 0x00000100 /* internal data length err */
297: #define EACSR_EXTRNLLEN 0x00000080 /* external data length err */
298: #define EACSR_DESBLOCK 0x00000040 /* des block size error */
299: #define EACSR_DESKEY 0x00000020 /* des key error */
300: #define EACSR_ILL 0x00000001 /* illegal access */
301:
302: /* NOCT_EA_CTX_ADDR */
303: #define EACTXADDR_READPEND 0x80000000 /* read pending/start */
304: #define EACTXADDR_WRITEPEND 0x40000000 /* write pending/start */
305: #define EACTXADDR_MASK 0x00ffffff /* address mask */
306:
307: /* NOCT_EA_SDRAM_CFG */
308: #define EASDRC_8KREFRESH 0x00000080 /* 8K refreshes/64ms */
309: #define EASDRC_FREQ 0x0000003f /* in MHz */
310:
311: /* NOCT_RNG_CTL */
312: #define RNGCTL_RNG_ENA 0x80000000 /* rng enable */
313: #define RNGCTL_TOD_ENA 0x40000000 /* enable tod counter */
314: #define RNGCTL_EXTCLK_ENA 0x20000000 /* external clock enable */
315: #define RNGCTL_DIAG 0x10000000 /* diagnostic mode */
316: #define RNGCTL_BUFSRC_M 0x0c000000 /* buffer source: */
317: #define RNGCTL_BUFSRC_X917 0x00000000 /* X9.17 expander */
318: #define RNGCTL_BUFSRC_SEED 0x04000000 /* seed generator */
319: #define RNGCTL_BUFSRC_HOST 0x08000000 /* host data */
320: #define RNGCTL_SEEDSRC_M 0x03000000 /* seed source: */
321: #define RNGCTL_SEEDSRC_INT 0x00000000 /* internal seed generator */
322: #define RNGCTL_SEEDSRC_EXT 0x01000000 /* external seed generator */
323: #define RNGCTL_SEEDSRC_HOST 0x02000000 /* host seed */
324: #define RNGCTL_SEED_ERR 0x00008000 /* seed error */
325: #define RNGCTL_X917_ERR 0x00004000 /* X9.17 error */
326: #define RNGCTL_KEY1PAR_ERR 0x00002000 /* key 1 parity error */
327: #define RNGCTL_KEY2PAR_ERR 0x00001000 /* key 2 parity error */
328: #define RNGCTL_HOSTSEEDVALID 0x00000400 /* host seed not consumed */
329: #define RNGCTL_BUF_RDY 0x00000200 /* buffer ready for write */
330: #define RNGCTL_ITERCNT 0x000000ff /* iteration count */
331:
332: /* NOCT_RNG_CSR */
333: #define RNGCSR_XFER_ENABLE 0x80000000 /* enable xfer queue */
334: #define RNGCSR_XFER_BUSY 0x40000000 /* xfer in progress */
335: #define RNGCSR_ERR_KEY 0x00800000 /* key error */
336: #define RNGCSR_ERR_BUS 0x00400000 /* pci bus error */
337: #define RNGCSR_ERR_DUP 0x00200000 /* duplicate block generated */
338: #define RNGCSR_ERR_ACCESS 0x00100000 /* access error */
339: #define RNGCSR_INT_KEY 0x00080000 /* intr ena: key error */
340: #define RNGCSR_INT_BUS 0x00040000 /* intr ena: pci error */
341: #define RNGCSR_INT_DUP 0x00020000 /* intr ena: dup error */
342: #define RNGCSR_INT_ACCESS 0x00010000 /* intr ena: access error */
343:
344: /* NOCT_RNG_Q_PTR */
345: #define RNGQPTR_READ_M 0x00007fff /* read mask */
346: #define RNGQPTR_READ_S 0 /* read shift */
347: #define RNGQPTR_WRITE_M 0x7fff0000 /* write mask */
348: #define RNGQPTR_WRITE_S 16 /* write shift */
349:
350: #define EA_CMD_WORDS 32
351: struct noct_ea_cmd {
352: volatile u_int32_t buf[EA_CMD_WORDS];
353: };
354:
355:
356: #define EA_0_CP 0x80000000 /* context block */
357: #define EA_0_SI 0x40000000 /* set interrupt */
358: #define EA_0_CTXIDX 0x0003ffff /* context index */
359:
360: #define EA_1_OPCODE 0xff000000 /* opcode */
361: #define EA_1_ITERCNT 0x000f0000 /* iteration count */
362: #define EA_1_DATALEN 0x0000ffff /* data length (bytes) */
363:
364: #define EA_OP_NOP 0x00000000 /* nop */
365: #define EA_OP_WCTX 0x01000000 /* write context mem */
366: #define EA_OP_RCTX 0x02000000 /* read context mem */
367: #define EA_OP_3DESCBCE 0x03000000 /* 3DES, CBC, encrypt */
368: #define EA_OP_3DESCBCD 0x04000000 /* 3DES, CBC, decrypt */
369: #define EA_OP_ARC4 0x05000000 /* ARC4 transform */
370: #define EA_OP_MD5 0x10000000 /* simple MD5 hash */
371: #define EA_OP_MD5_APP 0x11000000 /* MD5 hash w/append */
372: #define EA_OP_MD5_CMDIV 0x12000000 /* MD5 hash, IV from cmd */
373: #define EA_OP_MD5_LSTIV 0x13000000 /* MD5 hash, IV from last */
374: #define EA_OP_MD5_LSTCMD 0x14000000 /* MD5 hashlast;iv from cmd */
375: #define EA_OP_MD5_LSTLST 0x15000000 /* MD5 hashlast;iv from last */
376: #define EA_OP_MD5_KEYMAT 0x16000000 /* MD5 KEYMAT expansion */
377: #define EA_OP_MD5_SKEYID 0x17000000 /* MD5 SKEYID expansion */
378: #define EA_OP_MD5_IKEKEY 0x18000000 /* MD5 IKE KEYMAT */
379: #define EA_OP_SHA1 0x20000000 /* simple SHA1 hash */
380: #define EA_OP_SHA1_APP 0x21000000 /* SHA1 hash w/append */
381: #define EA_OP_SHA1_CMDIV 0x22000000 /* SHA1 hash, IV from cmd */
382: #define EA_OP_SHA1_LSTIV 0x23000000 /* SHA1 hash, IV from last */
383: #define EA_OP_SHA1_LSTCMD 0x24000000 /* SHA1 hashlast;iv from cmd */
384: #define EA_OP_SHA1_LSTLST 0x25000000 /* SHA1 hashlast;iv from lst */
385: #define EA_OP_SHA1_KEYMAT 0x26000000 /* SHA1 KEYMAT expansion */
386: #define EA_OP_SHA1_SKEYID 0x27000000 /* SHA1 SKEYID expansion */
387: #define EA_OP_SHA1_IKEKEY 0x28000000 /* SHA1 IKE KEYMAT */
388: #define EA_OP_MASTER_HASH 0x30000000 /* master secret hash */
389: #define EA_OP_NULL_NULL 0x80000000 /* packet level null/null */
390: #define EA_OP_SSL3_ARC4_MD5_E 0x81000000 /* ssl 3.0 arc4/md5 enc */
391: #define EA_OP_SSL3_DES_MD5_E 0x82000000 /* ssl 3.0 des/md5 enc */
392: #define EA_OP_SSL3_ARC4_SHA1_E 0x83000000 /* ssl 3.0 arc4/sha1 enc */
393: #define EA_OP_SSL3_DES_SHA1_E 0x84000000 /* ssl 3.0 des/sha1 enc */
394: #define EA_OP_SSL3_ARC4_MD5_D 0x91000000 /* ssl 3.0 arc4/md5 dec */
395: #define EA_OP_SSL3_DES_MD5_D 0x92000000 /* ssl 3.0 des/md5 dec */
396: #define EA_OP_SSL3_ARC4_SHA1_D 0x93000000 /* ssl 3.0 arc4/sha1 dec */
397: #define EA_OP_SSL3_DES_SHA1_D 0x94000000 /* ssl 3.0 des/sha1 dec */
398: #define EA_OP_TLS1_ARC4_MD5_E 0xa1000000 /* tls 1.0 arc4/md5 enc */
399: #define EA_OP_TLS1_DES_MD5_E 0xa2000000 /* tls 1.0 des/md5 enc */
400: #define EA_OP_TLS1_ARC4_SHA1_E 0xa3000000 /* tls 1.0 arc4/sha1 enc */
401: #define EA_OP_TLS1_DES_SHA1_E 0xa4000000 /* tls 1.0 des/sha1 enc */
402: #define EA_OP_TLS1_ARC4_MD5_D 0xb1000000 /* tls 1.0 arc4/md5 dec */
403: #define EA_OP_TLS1_DES_MD5_D 0xb2000000 /* tls 1.0 des/md5 dec */
404: #define EA_OP_TLS1_ARC4_SHA1_D 0xb3000000 /* tls 1.0 arc4/sha1 dec */
405: #define EA_OP_TLS1_DES_SHA1_D 0xb4000000 /* tls 1.0 des/sha1 dec */
406: #define EA_OP_IPS_DES_MD5_E 0xc1000000 /* ipsec des/md5 enc */
407: #define EA_OP_IPS_DES_SHA1_E 0xc2000000 /* ipsec des/sha1 enc */
408: #define EA_OP_IPS_DES_MD5_D 0xd1000000 /* ipsec des/md5 dec */
409: #define EA_OP_IPS_DES_SHA1_D 0xd2000000 /* ipsec des/sha1 dec */
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