Annotation of sys/dev/pci/musyccreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: musyccreg.h,v 1.3 2005/08/27 12:53:17 claudio Exp $ */
2:
3: /*
4: * Copyright (c) 2004,2005 Internet Business Solutions AG, Zurich, Switzerland
5: * Written by: Claudio Jeker <jeker@accoom.net>
6: *
7: * Permission to use, copy, modify, and distribute this software for any
8: * purpose with or without fee is hereby granted, provided that the above
9: * copyright notice and this permission notice appear in all copies.
10: *
11: * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12: * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13: * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14: * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15: * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16: * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17: * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18: */
19: #ifndef __MUSYCCREG_H__
20: #define __MUSYCCREG_H__
21:
22: #define MUSYCC_PCI_BAR 0x10 /* offset of Base Address Register */
23:
24: /* Group Base Pointer -- per Group unique */
25: #define MUSYCC_GROUPBASE(x) (0x0800 * (x))
26: /* Dual Address Cycle Base Pointer */
27: #define MUSYCC_DACB_PTR 0x0004
28: /* Service Request Descriptor -- per Group unique */
29: #define MUSYCC_SERREQ(x) (0x0008 + 0x0800 * (x))
30: /* Interrupt Status Descriptor */
31: #define MUSYCC_INTRSTATUS 0x000c
32: #define MUSYCC_INTCNT_MASK 0x00007fff
33: #define MUSYCC_INTFULL 0x00008000
34: #define MUSYCC_NEXTINT_GET(x) (((x) >> 16) & 0x7fff)
35: #define MUSYCC_NEXTINT_SET(x) (((x) & 0x7fff) << 16)
36:
37: /* Global Configuration Descriptor */
38: #define MUSYCC_GLOBALCONF 0x0600
39: /* Interrupt Queue Descriptor */
40: #define MUSYCC_INTQPTR 0x0604
41: #define MUSYCC_INTQLEN 0x0608
42:
43: /* group structure [page 5-6], this puppy needs to be 2k aligned */
44: struct musycc_grpdesc {
45: u_int32_t tx_headp[32]; /* transmit head ptr */
46: u_int32_t tx_msgp[32]; /* transmit msg ptr */
47: u_int32_t rx_headp[32]; /* receive head ptr */
48: u_int32_t rx_msgp[32]; /* receive msg ptr */
49: u_int8_t tx_tsmap[128]; /* transmit timeslot map */
50: u_int8_t tx_submap[256]; /* transmit sub channel map */
51: u_int32_t tx_cconf[32]; /* transmit channel config */
52: u_int8_t rx_tsmap[128]; /* receive timeslot map */
53: u_int8_t rx_submap[256]; /* receive sub channel map */
54: u_int32_t rx_cconf[32]; /* receive channel config */
55: u_int32_t global_conf; /* global config */
56: u_int32_t int_queuep; /* interrupt queue ptr */
57: u_int32_t int_queuelen; /* interrupt queue len */
58: u_int32_t group_conf; /* group config */
59: u_int32_t memprot; /* memory protection */
60: u_int32_t msglen_conf; /* message length config */
61: u_int32_t port_conf; /* serial port config */
62: };
63:
64: /* Global Configuration Descriptor [page 5-10] */
65: #define MUSYCC_CONF_PORTMAP 0x00000003 /* group -> port mapping */
66: #define MUSYCC_CONF_INTB 0x00000004 /* if set INTB is disabled */
67: #define MUSYCC_CONF_INTA 0x00000008 /* if set INTA is disabled */
68: #define MUSYCC_CONF_ELAPSE_GET(x) \
69: (((x) >> 4) & 0x7) /* get elapse value */
70: #define MUSYCC_CONF_ELAPSE_SET(x) \
71: ((x & 0x7) << 4) /* set elapse value */
72: #define MUSYCC_CONF_ALAPSE_GET(x) \
73: (((x) >> 8) & 0x3) /* get alapse value */
74: #define MUSYCC_CONF_ALAPSE_SET(x) \
75: ((x & 0x3) << 8) /* set alapse value */
76: #define MUSYCC_CONF_MPUSEL 0x00000400 /* EBUS mode, 1 = intel style */
77: #define MUSYCC_CONF_ECKEN 0x00000800 /* EBUS clock enable */
78: #define MUSYCC_CONF_BLAPSE_GET(x) \
79: (((x) >> 12) & 0x7) /* get blapse value */
80: #define MUSYCC_CONF_BLAPSE_SET(x) \
81: ((x & 0x7) << 12) /* set blapse value */
82:
83: /* Interrupt Descriptor [page 5-41] */
84: #define MUSYCC_INTD_BLEN 0x00001fff /* size of data on EOB & EOM */
85: #define MUSYCC_INTD_ILOST 0x00008000 /* Interrupt Lost */
86: #define MUSYCC_INTD_DIR 0x80000000 /* transmit specific int */
87: #define MUSYCC_INTD_GRP(x) \
88: ((((x) >> 29) & 0x3) | (((x) >> 12) & 0x4)) /* Group Number [0-7] */
89: #define MUSYCC_INTD_CHAN(x) \
90: (((x) >> 24) & 0x1f) /* Channel Number [0-31] */
91: #define MUSYCC_INTD_EVENT(x) \
92: (((x) >> 20) & 0xf) /* Event that caused the int */
93: #define MUSYCC_INTD_ERROR(x) \
94: (((x) >> 16) & 0xf) /* Error that caused the int */
95:
96: /* possible Interrupt Events */
97: #define MUSYCC_INTEV_NONE 0 /* No Event to report */
98: #define MUSYCC_INTEV_SACK 1 /* Service Request Ack */
99: #define MUSYCC_INTEV_EOB 2 /* End of Buffer */
100: #define MUSYCC_INTEV_EOM 3 /* End of Message */
101: #define MUSYCC_INTEV_EOP 4 /* End of Padfill */
102: #define MUSYCC_INTEV_CHABT 5 /* Change to Abort Code */
103: #define MUSYCC_INTEV_CHIC 6 /* Change to Idle Code */
104: #define MUSYCC_INTEV_FREC 7 /* Frame Recovery */
105: #define MUSYCC_INTEV_SINC 8 /* SS7 SUERM Octet Count inc */
106: #define MUSYCC_INTEV_SDEC 9 /* SS7 SUERM Octet Count dec */
107: #define MUSYCC_INTEV_SFILT 10 /* SS7 Filtered Message */
108:
109: /* possible Interrupt Errors */
110: #define MUSYCC_INTERR_NONE 0 /* No Error to report */
111: #define MUSYCC_INTERR_BUFF 1 /* Buffer Error */
112: #define MUSYCC_INTERR_COFA 2 /* Change of Frame Alignment */
113: #define MUSYCC_INTERR_ONR 3 /* Owner-Bit Error */
114: #define MUSYCC_INTERR_PROT 4 /* Mem Protection Violation */
115: #define MUSYCC_INTERR_OOF 8 /* Out of Frame */
116: #define MUSYCC_INTERR_FCS 9 /* Frame Check Sequence Error */
117: #define MUSYCC_INTERR_ALIGN 10 /* Octet Alignment Error */
118: #define MUSYCC_INTERR_ABT 11 /* Abort Termination */
119: #define MUSYCC_INTERR_LNG 12 /* Long Message */
120: #define MUSYCC_INTERR_SHT 13 /* Short Message */
121: #define MUSYCC_INTERR_SUERR 14 /* SS7 Signal Unit Error */
122: #define MUSYCC_INTERR_PERR 15 /* PCI Bus Parity Error */
123:
124: /* Service Request Descriptor [page 5-14] */
125: #define MUSYCC_SREQ_MASK 0x001f /* Generic SREQ/Channel Mask */
126: #define MUSYCC_SREQ_CHSET(x) \
127: ((x) & MUSYCC_SREQ_MASK) /* shortcut */
128: #define MUSYCC_SREQ_TXDIR 0x0020 /* Transmit Direction */
129: #define MUSYCC_SREQ_SET(x) \
130: (((x) & MUSYCC_SREQ_MASK) << 8) /* Service Request */
131:
132: #define MUSYCC_SREQ_RX 0x1 /* Receive Request */
133: #define MUSYCC_SREQ_TX 0x2 /* Transmit Request */
134: #define MUSYCC_SREQ_BOTH 0x3 /* both directions */
135: #define MUSYCC_SREQ_NOWAIT 0x8
136: #define MUSYCC_SREQ_NONE 0xffffffff
137:
138: /* Group Configuration Descriptor [page 5-16] */
139: #define MUSYCC_GRCFG_RXENBL 0x0001 /* Receiver Enabled */
140: #define MUSYCC_GRCFG_TXENBL 0x0002 /* Transmitter Enabled */
141: #define MUSYCC_GRCFG_SUBDSBL 0x0004 /* Subchanneling Disabled */
142: #define MUSYCC_GRCFG_OOFABT 0x0008 /* OOF Message Processing */
143: #define MUSYCC_GRCFG_MSKOOF 0x0010 /* OOF Interrupt Disabled */
144: #define MUSYCC_GRCFG_MSKCOFA 0x0020 /* COFA Interrupt Disabled */
145: #define MUSYCC_GRCFG_MCENBL 0x0040 /* Msg Config Bits Copy */
146: #define MUSYCC_GRCFG_INHRBSD 0x0100 /* Inihibit RX Buf Stat Desc */
147: #define MUSYCC_GRCFG_INHTBSD 0x0200 /* Inihibit TX Buf Stat Desc */
148: #define MUSYCC_GRCFG_POLL16 0x0400 /* Poll at all 16 frame sync */
149: #define MUSYCC_GRCFG_POLL32 0x0800 /* Poll at all 32 frame sync */
150: #define MUSYCC_GRCFG_POLL64 0x0C00 /* Poll at all 64 frame sync */
151: #define MUSYCC_GRCFG_SFALIGN 0x8000 /* Super Frame Alignment */
152: #define MUSYCC_GRCFG_SUETMASK 0x3f0000 /* SS7 SUERR Threshold */
153:
154: /* Port Configuration Descriptor [page 5-19] */
155: #define MUSYCC_PORT_MODEMASK 0x007 /* Port Mode Mask */
156: #define MUSYCC_PORT_MODE_T1 0 /* T1 - 24 time slots */
157: #define MUSYCC_PORT_MODE_E1 1 /* E1 - 32 time slots */
158: #define MUSYCC_PORT_MODE_2E1 2 /* 2*E1 - 64 time slots */
159: #define MUSYCC_PORT_MODE_4E1 3 /* 4*E1 - 128 time slots */
160: #define MUSYCC_PORT_MODE_N64 4 /* N*64 mode */
161: #define MUSYCC_PORT_TDAT_EDGE 0x010 /* TX Data on rising Edge */
162: #define MUSYCC_PORT_TSYNC_EDGE 0x020 /* TX Frame Sync on rising E */
163: #define MUSYCC_PORT_RDAT_EDGE 0x040 /* RX Data on rising Edge */
164: #define MUSYCC_PORT_RSYNC_EDGE 0x080 /* RX Frame Sync on rising E */
165: #define MUSYCC_PORT_ROOF_EDGE 0x100 /* RX OOF on rising Edge */
166: #define MUSYCC_PORT_TRITX 0x200 /* TX Three-state disabled */
167:
168: /* Message Length Descriptor [page 5-20] */
169: #define MUSYCC_MAXFRM_MAX 4094 /* maximum message length */
170: #define MUSYCC_MAXFRM_MASK 0x0fff
171: #define MUSYCC_MAXFRM2_SHIFT 16
172:
173: /* Time Slot Descriptor [page 5-23] */
174: #define MUSYCC_TSLOT_ENABLED 0x80 /* timeslot enabled */
175: #define MUSYCC_TSLOT_56K 0x20 /* 56kbps timeslots */
176: #define MUSYCC_TSLOT_SUB 0x40 /* subchannel timeslots */
177: #define MUSYCC_TSLOT_MASK 0x1f /* channel number mask */
178: #define MUSYCC_TSLOT_CHAN(x) \
179: ((x) & MUSYCC_TSLOT_MASK) /* masked channel number */
180:
181: /* Channel Configuration Descriptor [page 5-27] */
182: #define MUSYCC_CHAN_MSKBUFF 0x00000002 /* BUFF & ONR Intr disabled */
183: #define MUSYCC_CHAN_MSKEOM 0x00000004 /* EOM Interrupt disabled */
184: #define MUSYCC_CHAN_MSKMSG 0x00000008 /* LNG, FCS, ALIGN, ABT mask */
185: #define MUSYCC_CHAN_MSKIDLE 0x00000010 /* CHABT, CHIC, SHT Intr mask */
186: #define MUSYCC_CHAN_MSKSFILT 0x00000020 /* SS7 SFILT Interrupt mask */
187: #define MUSYCC_CHAN_MSKSDEC 0x00000040 /* SS7 SDEC Interrupt mask */
188: #define MUSYCC_CHAN_MSKSINC 0x00000080 /* SS7 SINC Interrupt mask */
189: #define MUSYCC_CHAN_MSKSUERR 0x00000100 /* SS7 SUERR Interrupt mask */
190: #define MUSYCC_CHAN_FCS 0x00000200 /* FCS checksum disable */
191: #define MUSYCC_CHAN_MAXLEN1 0x00000400 /* Msg Len Max via MAXFRM1 */
192: #define MUSYCC_CHAN_MAXLEN2 0x00000800 /* Msg Len Max via MAXFRM1 */
193: #define MUSYCC_CHAN_EOPI 0x00008000 /* End of Padfill Int enable */
194: #define MUSYCC_CHAN_INV 0x00800000 /* Data Inversion */
195: #define MUSYCC_CHAN_PADJ 0x80000000 /* Pad Count Adjust enabled */
196:
197: #define MUSYCC_CHAN_PROTO_GET(x) \
198: (((x) >> 12) & 0x7) /* get line protocol */
199: #define MUSYCC_CHAN_PROTO_SET(x) \
200: ((x & 0x7) << 12) /* set line protocol */
201: #define MUSYCC_PROTO_TRANSPARENT 0 /* raw stream */
202: #define MUSYCC_PROTO_SS7HDLC 1 /* SS7 HDLC messages */
203: #define MUSYCC_PROTO_HDLC16 2 /* basic HDLC with 16 bit FCS */
204: #define MUSYCC_PROTO_HDLC32 3 /* basic HDLC with 32 bit FCS */
205:
206: #define MUSYCC_CHAN_BUFLEN_GET(x) \
207: (((x) >> 16) & 0x3f) /* get FIFO Buffer Length */
208: #define MUSYCC_CHAN_BUFLEN_SET(x) \
209: (((x) & 0x3F) << 16) /* set FIFO Buffer Length */
210: #define MUSYCC_CHAN_BUFIDX_GET(x) \
211: (((x) >> 24) & 0x3f) /* get FIFO Buffer Index */
212: #define MUSYCC_CHAN_BUFIDX_SET(x) \
213: (((x) & 0x3F) << 24) /* set FIFO Buffer Index */
214:
215:
216: /* Tx / Rx Buffer Descriptor [page 5-33] */
217: #define MUSYCC_STATUS_LEN(x) \
218: ((x) & 0x3fff) /* length of dma buffer */
219: #define MUSYCC_STATUS_REPEAT 0x00008000 /* repeat buffer */
220: #define MUSYCC_STATUS_ERROR 0x000f0000
221: #define MUSYCC_STATUS_EOBI 0x10000000 /* end of buffer interrupt */
222: #define MUSYCC_STATUS_EOM 0x20000000 /* end of message */
223: #define MUSYCC_STATUS_NOPOLL 0x40000000 /* don't poll for new descr */
224: #define MUSYCC_STATUS_OWNER 0x80000000
225:
226:
227: /*
228: * ROM data structures
229: */
230:
231: struct musycc_rom {
232: u_int16_t magic;
233: #define MUSYCC_ROM_MAGIC (htons(0xacc0))
234: u_int8_t rev; /* rev. of the card */
235: u_int8_t vers; /* version of the rom */
236: char product[64];
237: u_int8_t portmap; /* portmap config */
238: u_int8_t portmode; /* port mode e.g. 2*E1 */
239: u_int8_t numframer; /* # of sub-configs */
240: u_int8_t ledmask; /* mask for led register */
241: u_int32_t ledbase; /* base of the led register */
242: u_int32_t rfu[2]; /* RFU */
243: };
244:
245: struct musycc_rom_framer {
246: u_int32_t type;
247: u_int32_t base;
248: u_int32_t size;
249: u_int8_t gnum;
250: u_int8_t port;
251: char slot;
252: u_int8_t flags;
253: u_int32_t rfu[2]; /* RFU */
254: };
255: #endif
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