Annotation of sys/dev/pci/lofnreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: lofnreg.h,v 1.15 2003/06/02 19:08:58 jason Exp $ */
2:
3: /*
4: * Copyright (c) 2001-2002 Jason L. Wright (jason@thought.net)
5: * All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: *
16: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
25: * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26: * POSSIBILITY OF SUCH DAMAGE.
27: *
28: * Effort sponsored in part by the Defense Advanced Research Projects
29: * Agency (DARPA) and Air Force Research Laboratory, Air Force
30: * Materiel Command, USAF, under agreement number F30602-01-2-0537.
31: *
32: */
33:
34: #define LOFN_BAR0 0x0010 /* base address register */
35:
36: #define LOFN_WIN_0 0x0000 /* 0 - rev byte, norm word */
37: #define LOFN_WIN_1 0x2000 /* 1 - rev byte, rev word */
38: #define LOFN_WIN_2 0x4000 /* 2 - norm byte, norm word */
39: #define LOFN_WIN_3 0x6000 /* 3 - norm byte, rev word */
40:
41: /* Bignum registers */
42: #define LOFN_REL_DATA 0x0000 /* Data registers */
43: #define LOFN_REL_DATA_END 0x07ff
44: /* Length registers */
45: #define LOFN_REL_LEN 0x1000 /* Length tags */
46: #define LOFN_REL_LEN_REGS 0x103f
47: /* RNG FIFO space */
48: #define LOFN_REL_RNG 0x1080 /* RNG FIFO start */
49: #define LOFN_REL_RNG_END 0x10bf /* RNG FIFO end */
50: /* Instruction space */
51: #define LOFN_REL_INSTR 0x1100 /* Instructions */
52: #define LOFN_REL_INSTR_END 0x117f
53: /* Control and status registers, relative to window number */
54: #define LOFN_REL_CR 0x1fd4 /* Command */
55: #define LOFN_REL_SR 0x1fd8 /* Status */
56: #define LOFN_REL_IER 0x1fdc /* Interrupt enable */
57: #define LOFN_REL_RNC 0x1fe0 /* RNG config */
58: #define LOFN_REL_CFG1 0x1fe4 /* Config1 */
59: #define LOFN_REL_CFG2 0x1fe8 /* Config2 */
60: #define LOFN_REL_CHIPID 0x1fec /* Chip ID */
61:
62: /* Data register access */
63: #define LOFN_REG_MASK 0x0f80 /* Register number mask */
64: #define LOFN_REG_SHIFT 7
65: #define LOFN_WORD_MASK 0x007c /* Word index mask */
66: #define LOFN_WORD_SHIFT 2
67:
68: /* Command address register (LOFN_REL_CR) */
69: #define LOFN_CR_ADDR_MASK 0x0000003f /* Instruction addr offset */
70:
71: /* Status register (LOFN_REL_SR) */
72: #define LOFN_SR_CARRY 0x00000008 /* Carry from operation */
73: #define LOFN_SR_RNG_UF 0x00001000 /* RNG underflow */
74: #define LOFN_SR_RNG_RDY 0x00004000 /* RNG ready */
75: #define LOFN_SR_DONE 0x00008000 /* Operation done */
76:
77: /* Interrupt enable register (LOFN_REL_IER) */
78: #define LOFN_IER_RDY 0x00004000 /* RNG ready */
79: #define LOFN_IER_DONE 0x00008000 /* Operation done */
80:
81: /* Random number configuration (LOFN_REL_RNC) */
82: #define LOFN_RNC_OUTSCALE 0x00000080 /* Output prescalar */
83: #define LOFN_RNC_1STSCALE 0x00000f00 /* First prescalar */
84:
85: /* Config register 1 (LOFN_REL_CFG1) */
86: #define LOFN_CFG1_RESET 0x00000001 /* Reset */
87: #define LOFN_CFG1_MULTI 0x00000038 /* PLL multiple */
88: #define LOFN_CFG1_MULTI_BYP 0x00000000 /* PLL bypass */
89: #define LOFN_CFG1_MULTI_1X 0x00000008 /* 1x CLK */
90: #define LOFN_CFG1_MULTI_15X 0x00000010 /* 1.5x CLK */
91: #define LOFN_CFG1_MULTI_2X 0x00000018 /* 2x CLK */
92: #define LOFN_CFG1_MULTI_25X 0x00000020 /* 2.5x CLK */
93: #define LOFN_CFG1_MULTI_3X 0x00000028 /* 3x CLK */
94: #define LOFN_CFG1_MULTI_4X 0x00000030 /* 4x CLK */
95: #define LOFN_CFG1_CLOCK 0x00000040 /* Clock select */
96:
97: /* Config register 2 (LOFN_REL_CFG2) */
98: #define LOFN_CFG2_RNGENA 0x00000001 /* RNG enable */
99: #define LOFN_CFG2_PRCENA 0x00000002 /* Processor enable */
100:
101: /* Chip identification (LOFN_REL_CHIPID) */
102: #define LOFN_CHIPID_MASK 0x0000ffff /* Chip ID */
103:
104: #define LOFN_REGADDR(win,r,idx) \
105: ((win) | \
106: (((r) << LOFN_REG_SHIFT) & LOFN_REG_MASK) | \
107: (((idx) << LOFN_WORD_SHIFT) & LOFN_WORD_MASK))
108:
109: #define LOFN_LENADDR(win,r) \
110: ((win) | (((r) << 2) + LOFN_REL_LEN))
111:
112: #define LOFN_LENMASK 0x000007ff /* mask for length space */
113:
114: #define OP_DONE 0x80000000 /* final instruction */
115: #define OP_CODE_MASK 0x7c000000 /* opcode mask */
116: #define OP_CODE_MODEXP 0x00000000 /* modular exponentiation */
117: #define OP_CODE_MODMUL 0x04000000 /* modular multiplication */
118: #define OP_CODE_MODRED 0x08000000 /* modular reduction */
119: #define OP_CODE_MODADD 0x0c000000 /* modular addition */
120: #define OP_CODE_MODSUB 0x10000000 /* modular subtraction */
121: #define OP_CODE_ADD 0x14000000 /* addition */
122: #define OP_CODE_SUB 0x18000000 /* subtraction */
123: #define OP_CODE_ADDC 0x1c000000 /* addition with carry */
124: #define OP_CODE_SUBC 0x20000000 /* subtraction with carry */
125: #define OP_CODE_MULT 0x24000000 /* 2048bit multiplication */
126: #define OP_CODE_SR 0x28000000 /* shift right */
127: #define OP_CODE_SL 0x2c000000 /* shift left */
128: #define OP_CODE_INC 0x30000000 /* increment */
129: #define OP_CODE_DEC 0x34000000 /* decrement */
130: #define OP_CODE_TAG 0x38000000 /* set length tag */
131: #define OP_CODE_NOP 0x7c000000 /* nop */
132:
133: #define OP_RD_SHIFT 21
134: #define OP_RA_SHIFT 16
135: #define OP_RB_SHIFT 11
136: #define OP_RM_SHIFT 6
137: #define OP_R_MASK 0x1f
138: #define OP_LEN_MASK 0xffff
139:
140: #define LOFN_INSTR(done,op,rd,ra,rb,rm) \
141: ((done) | (op) | \
142: (((rd) & OP_R_MASK) << OP_RD_SHIFT) | \
143: (((ra) & OP_R_MASK) << OP_RA_SHIFT) | \
144: (((rb) & OP_R_MASK) << OP_RB_SHIFT) | \
145: (((rm) & OP_R_MASK) << OP_RM_SHIFT))
146:
147: #define LOFN_INSTR2(done,op,rd,ra,len) \
148: ((done) | (op) | \
149: (((rd) & OP_R_MASK) << OP_RD_SHIFT) | \
150: (((ra) & OP_R_MASK) << OP_RA_SHIFT) | \
151: ((len) & OP_LEN_MASK))
152:
153: /* registers are 1024 bits wide, but must be addressed by word. */
154: union lofn_reg {
155: u_int8_t b[128];
156: u_int32_t w[32];
157: };
158:
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