Annotation of sys/dev/pci/ixgb_hw.h, Revision 1.1
1.1 ! nbrk 1: /*******************************************************************************
! 2:
! 3: Copyright (c) 2001-2005, Intel Corporation
! 4: All rights reserved.
! 5:
! 6: Redistribution and use in source and binary forms, with or without
! 7: modification, are permitted provided that the following conditions are met:
! 8:
! 9: 1. Redistributions of source code must retain the above copyright notice,
! 10: this list of conditions and the following disclaimer.
! 11:
! 12: 2. Redistributions in binary form must reproduce the above copyright
! 13: notice, this list of conditions and the following disclaimer in the
! 14: documentation and/or other materials provided with the distribution.
! 15:
! 16: 3. Neither the name of the Intel Corporation nor the names of its
! 17: contributors may be used to endorse or promote products derived from
! 18: this software without specific prior written permission.
! 19:
! 20: THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
! 21: AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
! 22: IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
! 23: ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
! 24: LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
! 25: CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
! 26: SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
! 27: INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
! 28: CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
! 29: ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 30: POSSIBILITY OF SUCH DAMAGE.
! 31:
! 32: *******************************************************************************/
! 33:
! 34: /* $OpenBSD: ixgb_hw.h,v 1.1 2005/11/14 23:25:43 brad Exp $ */
! 35:
! 36: #ifndef _IXGB_HW_H_
! 37: #define _IXGB_HW_H_
! 38:
! 39: #include <dev/pci/if_ixgb_osdep.h>
! 40:
! 41: /* Enums */
! 42: typedef enum {
! 43: ixgb_mac_unknown = 0,
! 44: ixgb_82597,
! 45: ixgb_num_macs
! 46: } ixgb_mac_type;
! 47:
! 48: /* Types of physical layer modules */
! 49: typedef enum {
! 50: ixgb_phy_type_unknown = 0,
! 51: ixgb_phy_type_g6005, /* 850nm, MM fiber, XPAK transceiver */
! 52: ixgb_phy_type_g6104, /* 1310nm, SM fiber, XPAK transceiver */
! 53: ixgb_phy_type_txn17201, /* 850nm, MM fiber, XPAK transceiver */
! 54: ixgb_phy_type_txn17401 /* 1310nm, SM fiber, XENPAK transceiver */
! 55: } ixgb_phy_type;
! 56:
! 57: /* XPAK transceiver vendors, for the SR adapters */
! 58: typedef enum {
! 59: ixgb_xpak_vendor_intel,
! 60: ixgb_xpak_vendor_infineon
! 61: } ixgb_xpak_vendor;
! 62:
! 63: /* Media Types */
! 64: typedef enum {
! 65: ixgb_media_type_unknown = 0,
! 66: ixgb_media_type_fiber = 1,
! 67: ixgb_media_type_copper = 2,
! 68: ixgb_num_media_types
! 69: } ixgb_media_type;
! 70:
! 71: /* Flow Control Settings */
! 72: typedef enum {
! 73: ixgb_fc_none = 0,
! 74: ixgb_fc_rx_pause = 1,
! 75: ixgb_fc_tx_pause = 2,
! 76: ixgb_fc_full = 3,
! 77: ixgb_fc_default = 0xFF
! 78: } ixgb_fc_type;
! 79:
! 80: /* PCI bus types */
! 81: typedef enum {
! 82: ixgb_bus_type_unknown = 0,
! 83: ixgb_bus_type_pci,
! 84: ixgb_bus_type_pcix
! 85: } ixgb_bus_type;
! 86:
! 87: /* PCI bus speeds */
! 88: typedef enum {
! 89: ixgb_bus_speed_unknown = 0,
! 90: ixgb_bus_speed_33,
! 91: ixgb_bus_speed_66,
! 92: ixgb_bus_speed_100,
! 93: ixgb_bus_speed_133,
! 94: ixgb_bus_speed_reserved
! 95: } ixgb_bus_speed;
! 96:
! 97: /* PCI bus widths */
! 98: typedef enum {
! 99: ixgb_bus_width_unknown = 0,
! 100: ixgb_bus_width_32,
! 101: ixgb_bus_width_64
! 102: } ixgb_bus_width;
! 103:
! 104: #define IXGB_ETH_LENGTH_OF_ADDRESS 6
! 105:
! 106: #define IXGB_EEPROM_SIZE 64 /* Size in words */
! 107:
! 108: #define SPEED_10000 10000
! 109: #define FULL_DUPLEX 2
! 110:
! 111: #define MIN_NUMBER_OF_DESCRIPTORS 8
! 112: #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 /* 13 bits in RDLEN/TDLEN, 128B
! 113: * aligned */
! 114:
! 115: #define IXGB_DELAY_BEFORE_RESET 10 /* allow 10ms after idling
! 116: * rx/tx units */
! 117: #define IXGB_DELAY_AFTER_RESET 1 /* allow 1ms after the reset */
! 118: #define IXGB_DELAY_AFTER_EE_RESET 10 /* allow 10ms after the EEPROM
! 119: * reset */
! 120:
! 121: #define IXGB_DELAY_USECS_AFTER_LINK_RESET 13 /* allow 13 microseconds after
! 122: * the reset */
! 123: /* NOTE: this is MICROSECONDS */
! 124: #define MAX_RESET_ITERATIONS 8 /* number of iterations to get
! 125: * things right */
! 126:
! 127: /* General Registers */
! 128: #define IXGB_CTRL0 0x00000 /* Device Control Register 0 - RW */
! 129: #define IXGB_CTRL1 0x00008 /* Device Control Register 1 - RW */
! 130: #define IXGB_STATUS 0x00010 /* Device Status Register - RO */
! 131: #define IXGB_EECD 0x00018 /* EEPROM/Flash Control/Data Register - RW */
! 132: #define IXGB_MFRMS 0x00020 /* Maximum Frame Size - RW */
! 133:
! 134: /* Interrupt */
! 135: #define IXGB_ICR 0x00080 /* Interrupt Cause Read - R/clr */
! 136: #define IXGB_ICS 0x00088 /* Interrupt Cause Set - RW */
! 137: #define IXGB_IMS 0x00090 /* Interrupt Mask Set/Read - RW */
! 138: #define IXGB_IMC 0x00098 /* Interrupt Mask Clear - WO */
! 139:
! 140: /* Receive */
! 141: #define IXGB_RCTL 0x00100 /* RX Control - RW */
! 142: #define IXGB_FCRTL 0x00108 /* Flow Control Receive Threshold Low - RW */
! 143: #define IXGB_FCRTH 0x00110 /* Flow Control Receive Threshold High - RW */
! 144: #define IXGB_RDBAL 0x00118 /* RX Descriptor Base Low - RW */
! 145: #define IXGB_RDBAH 0x0011C /* RX Descriptor Base High - RW */
! 146: #define IXGB_RDLEN 0x00120 /* RX Descriptor Length - RW */
! 147: #define IXGB_RDH 0x00128 /* RX Descriptor Head - RW */
! 148: #define IXGB_RDT 0x00130 /* RX Descriptor Tail - RW */
! 149: #define IXGB_RDTR 0x00138 /* RX Delay Timer Ring - RW */
! 150: #define IXGB_RXDCTL 0x00140 /* Receive Descriptor Control - RW */
! 151: #define IXGB_RAIDC 0x00148 /* Receive Adaptive Interrupt Delay Ctrl RW */
! 152: #define IXGB_RXCSUM 0x00158 /* Receive Checksum Control - RW */
! 153: #define IXGB_RA 0x00180 /* Receive Address Array Base - RW */
! 154: #define IXGB_RAL 0x00180 /* Receive Address Low [0:15] - RW */
! 155: #define IXGB_RAH 0x00184 /* Receive Address High [0:15] - RW */
! 156: #define IXGB_MTA 0x00200 /* Multicast Table Array [0:127] - RW */
! 157: #define IXGB_VFTA 0x00400 /* VLAN Filter Table Array [0:127] - RW */
! 158: #define IXGB_REQ_RX_DESCRIPTOR_MULTIPLE 8
! 159:
! 160: /* Transmit */
! 161: #define IXGB_TCTL 0x00600 /* TX Control - RW */
! 162: #define IXGB_TDBAL 0x00608 /* TX Descriptor Base Low - RW */
! 163: #define IXGB_TDBAH 0x0060C /* TX Descriptor Base High - RW */
! 164: #define IXGB_TDLEN 0x00610 /* TX Descriptor Length - RW */
! 165: #define IXGB_TDH 0x00618 /* TX Descriptor Head - RW */
! 166: #define IXGB_TDT 0x00620 /* TX Descriptor Tail - RW */
! 167: #define IXGB_TIDV 0x00628 /* TX Interrupt Delay Value - RW */
! 168: #define IXGB_TXDCTL 0x00630 /* Transmit Descriptor Control - RW */
! 169: #define IXGB_TSPMT 0x00638 /* TCP Segmentation PAD & Min Threshold - RW */
! 170: #define IXGB_PAP 0x00640 /* Pause and Pace - RW */
! 171: #define IXGB_REQ_TX_DESCRIPTOR_MULTIPLE 8
! 172:
! 173: /* Physical */
! 174: #define IXGB_PCSC1 0x00700 /* PCS Control 1 - RW */
! 175: #define IXGB_PCSC2 0x00708 /* PCS Control 2 - RW */
! 176: #define IXGB_PCSS1 0x00710 /* PCS Status 1 - RO */
! 177: #define IXGB_PCSS2 0x00718 /* PCS Status 2 - RO */
! 178: #define IXGB_XPCSS 0x00720 /* 10GBASE-X PCS Status (or XGXS Lane Status) -
! 179: * RO */
! 180: #define IXGB_UCCR 0x00728 /* Unilink Circuit Control Register */
! 181: #define IXGB_XPCSTC 0x00730 /* 10GBASE-X PCS Test Control */
! 182: #define IXGB_MACA 0x00738 /* MDI Autoscan Command and Address - RW */
! 183: #define IXGB_APAE 0x00740 /* Autoscan PHY Address Enable - RW */
! 184: #define IXGB_ARD 0x00748 /* Autoscan Read Data - RO */
! 185: #define IXGB_AIS 0x00750 /* Autoscan Interrupt Status - RO */
! 186: #define IXGB_MSCA 0x00758 /* MDI Single Command and Address - RW */
! 187: #define IXGB_MSRWD 0x00760 /* MDI Single Read and Write Data - RW, RO */
! 188:
! 189: /* Wake-up */
! 190: #define IXGB_WUFC 0x00808 /* Wake Up Filter Control - RW */
! 191: #define IXGB_WUS 0x00810 /* Wake Up Status - RO */
! 192: #define IXGB_FFLT 0x01000 /* Flexible Filter Length Table - RW */
! 193: #define IXGB_FFMT 0x01020 /* Flexible Filter Mask Table - RW */
! 194: #define IXGB_FTVT 0x01420 /* Flexible Filter Value Table - RW */
! 195:
! 196: /* Statistics */
! 197: #define IXGB_TPRL 0x02000 /* Total Packets Received (Low) */
! 198: #define IXGB_TPRH 0x02004 /* Total Packets Received (High) */
! 199: #define IXGB_GPRCL 0x02008 /* Good Packets Received Count (Low) */
! 200: #define IXGB_GPRCH 0x0200C /* Good Packets Received Count (High) */
! 201: #define IXGB_BPRCL 0x02010 /* Broadcast Packets Received Count (Low) */
! 202: #define IXGB_BPRCH 0x02014 /* Broadcast Packets Received Count (High) */
! 203: #define IXGB_MPRCL 0x02018 /* Multicast Packets Received Count (Low) */
! 204: #define IXGB_MPRCH 0x0201C /* Multicast Packets Received Count (High) */
! 205: #define IXGB_UPRCL 0x02020 /* Unicast Packets Received Count (Low) */
! 206: #define IXGB_UPRCH 0x02024 /* Unicast Packets Received Count (High) */
! 207: #define IXGB_VPRCL 0x02028 /* VLAN Packets Received Count (Low) */
! 208: #define IXGB_VPRCH 0x0202C /* VLAN Packets Received Count (High) */
! 209: #define IXGB_JPRCL 0x02030 /* Jumbo Packets Received Count (Low) */
! 210: #define IXGB_JPRCH 0x02034 /* Jumbo Packets Received Count (High) */
! 211: #define IXGB_GORCL 0x02038 /* Good Octets Received Count (Low) */
! 212: #define IXGB_GORCH 0x0203C /* Good Octets Received Count (High) */
! 213: #define IXGB_TORL 0x02040 /* Total Octets Received (Low) */
! 214: #define IXGB_TORH 0x02044 /* Total Octets Received (High) */
! 215: #define IXGB_RNBC 0x02048 /* Receive No Buffers Count */
! 216: #define IXGB_RUC 0x02050 /* Receive Undersize Count */
! 217: #define IXGB_ROC 0x02058 /* Receive Oversize Count */
! 218: #define IXGB_RLEC 0x02060 /* Receive Length Error Count */
! 219: #define IXGB_CRCERRS 0x02068 /* CRC Error Count */
! 220: #define IXGB_ICBC 0x02070 /* Illegal control byte in mid-packet Count */
! 221: #define IXGB_ECBC 0x02078 /* Error Control byte in mid-packet Count */
! 222: #define IXGB_MPC 0x02080 /* Missed Packets Count */
! 223: #define IXGB_TPTL 0x02100 /* Total Packets Transmitted (Low) */
! 224: #define IXGB_TPTH 0x02104 /* Total Packets Transmitted (High) */
! 225: #define IXGB_GPTCL 0x02108 /* Good Packets Transmitted Count (Low) */
! 226: #define IXGB_GPTCH 0x0210C /* Good Packets Transmitted Count (High) */
! 227: #define IXGB_BPTCL 0x02110 /* Broadcast Packets Transmitted Count (Low) */
! 228: #define IXGB_BPTCH 0x02114 /* Broadcast Packets Transmitted Count (High) */
! 229: #define IXGB_MPTCL 0x02118 /* Multicast Packets Transmitted Count (Low) */
! 230: #define IXGB_MPTCH 0x0211C /* Multicast Packets Transmitted Count (High) */
! 231: #define IXGB_UPTCL 0x02120 /* Unicast Packets Transmitted Count (Low) */
! 232: #define IXGB_UPTCH 0x02124 /* Unicast Packets Transmitted Count (High) */
! 233: #define IXGB_VPTCL 0x02128 /* VLAN Packets Transmitted Count (Low) */
! 234: #define IXGB_VPTCH 0x0212C /* VLAN Packets Transmitted Count (High) */
! 235: #define IXGB_JPTCL 0x02130 /* Jumbo Packets Transmitted Count (Low) */
! 236: #define IXGB_JPTCH 0x02134 /* Jumbo Packets Transmitted Count (High) */
! 237: #define IXGB_GOTCL 0x02138 /* Good Octets Transmitted Count (Low) */
! 238: #define IXGB_GOTCH 0x0213C /* Good Octets Transmitted Count (High) */
! 239: #define IXGB_TOTL 0x02140 /* Total Octets Transmitted Count (Low) */
! 240: #define IXGB_TOTH 0x02144 /* Total Octets Transmitted Count (High) */
! 241: #define IXGB_DC 0x02148 /* Defer Count */
! 242: #define IXGB_PLT64C 0x02150 /* Packet Transmitted was < 64 bytes Count */
! 243: #define IXGB_TSCTC 0x02170 /* TCP Segmentation Context Transmitted Count */
! 244: #define IXGB_TSCTFC 0x02178 /* TCP Segmentation Context Tx Fail Count */
! 245: #define IXGB_IBIC 0x02180 /* Illegal byte during Idle stream count */
! 246: #define IXGB_RFC 0x02188 /* Remote Fault Count */
! 247: #define IXGB_LFC 0x02190 /* Local Fault Count */
! 248: #define IXGB_PFRC 0x02198 /* Pause Frame Receive Count */
! 249: #define IXGB_PFTC 0x021A0 /* Pause Frame Transmit Count */
! 250: #define IXGB_MCFRC 0x021A8 /* MAC Control Frames (non-Pause) Received
! 251: * Count */
! 252: #define IXGB_MCFTC 0x021B0 /* MAC Control Frames (non-Pause) Transmitted
! 253: * Count */
! 254: #define IXGB_XONRXC 0x021B8 /* XON Received Count */
! 255: #define IXGB_XONTXC 0x021C0 /* XON Transmitted Count */
! 256: #define IXGB_XOFFRXC 0x021C8 /* XOFF Received Count */
! 257: #define IXGB_XOFFTXC 0x021D0 /* XOFF Transmitted Count */
! 258: #define IXGB_RJC 0x021D8 /* Receive Jabber Count */
! 259:
! 260:
! 261: /* CTRL0 Bit Masks */
! 262: #define IXGB_CTRL0_LRST 0x00000008
! 263: #define IXGB_CTRL0_JFE 0x00000010
! 264: #define IXGB_CTRL0_XLE 0x00000020
! 265: #define IXGB_CTRL0_MDCS 0x00000040
! 266: #define IXGB_CTRL0_CMDC 0x00000080
! 267: #define IXGB_CTRL0_SDP0 0x00040000
! 268: #define IXGB_CTRL0_SDP1 0x00080000
! 269: #define IXGB_CTRL0_SDP2 0x00100000
! 270: #define IXGB_CTRL0_SDP3 0x00200000
! 271: #define IXGB_CTRL0_SDP0_DIR 0x00400000
! 272: #define IXGB_CTRL0_SDP1_DIR 0x00800000
! 273: #define IXGB_CTRL0_SDP2_DIR 0x01000000
! 274: #define IXGB_CTRL0_SDP3_DIR 0x02000000
! 275: #define IXGB_CTRL0_RST 0x04000000
! 276: #define IXGB_CTRL0_RPE 0x08000000
! 277: #define IXGB_CTRL0_TPE 0x10000000
! 278: #define IXGB_CTRL0_VME 0x40000000
! 279:
! 280: /* CTRL1 Bit Masks */
! 281: #define IXGB_CTRL1_GPI0_EN 0x00000001
! 282: #define IXGB_CTRL1_GPI1_EN 0x00000002
! 283: #define IXGB_CTRL1_GPI2_EN 0x00000004
! 284: #define IXGB_CTRL1_GPI3_EN 0x00000008
! 285: #define IXGB_CTRL1_SDP4 0x00000010
! 286: #define IXGB_CTRL1_SDP5 0x00000020
! 287: #define IXGB_CTRL1_SDP6 0x00000040
! 288: #define IXGB_CTRL1_SDP7 0x00000080
! 289: #define IXGB_CTRL1_SDP4_DIR 0x00000100
! 290: #define IXGB_CTRL1_SDP5_DIR 0x00000200
! 291: #define IXGB_CTRL1_SDP6_DIR 0x00000400
! 292: #define IXGB_CTRL1_SDP7_DIR 0x00000800
! 293: #define IXGB_CTRL1_EE_RST 0x00002000
! 294: #define IXGB_CTRL1_RO_DIS 0x00020000
! 295: #define IXGB_CTRL1_PCIXHM_MASK 0x00C00000
! 296: #define IXGB_CTRL1_PCIXHM_1_2 0x00000000
! 297: #define IXGB_CTRL1_PCIXHM_5_8 0x00400000
! 298: #define IXGB_CTRL1_PCIXHM_3_4 0x00800000
! 299: #define IXGB_CTRL1_PCIXHM_7_8 0x00C00000
! 300:
! 301: /* STATUS Bit Masks */
! 302: #define IXGB_STATUS_LU 0x00000002
! 303: #define IXGB_STATUS_AIP 0x00000004
! 304: #define IXGB_STATUS_TXOFF 0x00000010
! 305: #define IXGB_STATUS_XAUIME 0x00000020
! 306: #define IXGB_STATUS_RES 0x00000040
! 307: #define IXGB_STATUS_RIS 0x00000080
! 308: #define IXGB_STATUS_RIE 0x00000100
! 309: #define IXGB_STATUS_RLF 0x00000200
! 310: #define IXGB_STATUS_RRF 0x00000400
! 311: #define IXGB_STATUS_PCI_SPD 0x00000800
! 312: #define IXGB_STATUS_BUS64 0x00001000
! 313: #define IXGB_STATUS_PCIX_MODE 0x00002000
! 314: #define IXGB_STATUS_PCIX_SPD_MASK 0x0000C000
! 315: #define IXGB_STATUS_PCIX_SPD_66 0x00000000
! 316: #define IXGB_STATUS_PCIX_SPD_100 0x00004000
! 317: #define IXGB_STATUS_PCIX_SPD_133 0x00008000
! 318: #define IXGB_STATUS_REV_ID_MASK 0x000F0000
! 319: #define IXGB_STATUS_REV_ID_SHIFT 16
! 320:
! 321: /* EECD Bit Masks */
! 322: #define IXGB_EECD_SK 0x00000001
! 323: #define IXGB_EECD_CS 0x00000002
! 324: #define IXGB_EECD_DI 0x00000004
! 325: #define IXGB_EECD_DO 0x00000008
! 326: #define IXGB_EECD_FWE_MASK 0x00000030
! 327: #define IXGB_EECD_FWE_DIS 0x00000010
! 328: #define IXGB_EECD_FWE_EN 0x00000020
! 329:
! 330: /* MFRMS */
! 331: #define IXGB_MFRMS_SHIFT 16
! 332:
! 333: /* Interrupt Register Bit Masks (used for ICR, ICS, IMS, and IMC) */
! 334: #define IXGB_INT_TXDW 0x00000001
! 335: #define IXGB_INT_TXQE 0x00000002
! 336: #define IXGB_INT_LSC 0x00000004
! 337: #define IXGB_INT_RXSEQ 0x00000008
! 338: #define IXGB_INT_RXDMT0 0x00000010
! 339: #define IXGB_INT_RXO 0x00000040
! 340: #define IXGB_INT_RXT0 0x00000080
! 341: #define IXGB_INT_AUTOSCAN 0x00000200
! 342: #define IXGB_INT_GPI0 0x00000800
! 343: #define IXGB_INT_GPI1 0x00001000
! 344: #define IXGB_INT_GPI2 0x00002000
! 345: #define IXGB_INT_GPI3 0x00004000
! 346:
! 347: /* RCTL Bit Masks */
! 348: #define IXGB_RCTL_RXEN 0x00000002
! 349: #define IXGB_RCTL_SBP 0x00000004
! 350: #define IXGB_RCTL_UPE 0x00000008
! 351: #define IXGB_RCTL_MPE 0x00000010
! 352: #define IXGB_RCTL_RDMTS_MASK 0x00000300
! 353: #define IXGB_RCTL_RDMTS_1_2 0x00000000
! 354: #define IXGB_RCTL_RDMTS_1_4 0x00000100
! 355: #define IXGB_RCTL_RDMTS_1_8 0x00000200
! 356: #define IXGB_RCTL_MO_MASK 0x00003000
! 357: #define IXGB_RCTL_MO_47_36 0x00000000
! 358: #define IXGB_RCTL_MO_46_35 0x00001000
! 359: #define IXGB_RCTL_MO_45_34 0x00002000
! 360: #define IXGB_RCTL_MO_43_32 0x00003000
! 361: #define IXGB_RCTL_MO_SHIFT 12
! 362: #define IXGB_RCTL_BAM 0x00008000
! 363: #define IXGB_RCTL_BSIZE_MASK 0x00030000
! 364: #define IXGB_RCTL_BSIZE_2048 0x00000000
! 365: #define IXGB_RCTL_BSIZE_4096 0x00010000
! 366: #define IXGB_RCTL_BSIZE_8192 0x00020000
! 367: #define IXGB_RCTL_BSIZE_16384 0x00030000
! 368: #define IXGB_RCTL_VFE 0x00040000
! 369: #define IXGB_RCTL_CFIEN 0x00080000
! 370: #define IXGB_RCTL_CFI 0x00100000
! 371: #define IXGB_RCTL_RPDA_MASK 0x00600000
! 372: #define IXGB_RCTL_RPDA_MC_MAC 0x00000000
! 373: #define IXGB_RCTL_MC_ONLY 0x00400000
! 374: #define IXGB_RCTL_CFF 0x00800000
! 375: #define IXGB_RCTL_SECRC 0x04000000
! 376: #define IXGB_RDT_FPDB 0x80000000
! 377:
! 378: #define IXGB_RCTL_IDLE_RX_UNIT 0
! 379:
! 380: /* FCRTL Bit Masks */
! 381: #define IXGB_FCRTL_XONE 0x80000000
! 382:
! 383: /* RXDCTL Bit Masks */
! 384: #define IXGB_RXDCTL_PTHRESH_MASK 0x000001FF
! 385: #define IXGB_RXDCTL_PTHRESH_SHIFT 0
! 386: #define IXGB_RXDCTL_HTHRESH_MASK 0x0003FE00
! 387: #define IXGB_RXDCTL_HTHRESH_SHIFT 9
! 388: #define IXGB_RXDCTL_WTHRESH_MASK 0x07FC0000
! 389: #define IXGB_RXDCTL_WTHRESH_SHIFT 18
! 390:
! 391: /* RAIDC Bit Masks */
! 392: #define IXGB_RAIDC_HIGHTHRS_MASK 0x0000003F
! 393: #define IXGB_RAIDC_DELAY_MASK 0x000FF800
! 394: #define IXGB_RAIDC_DELAY_SHIFT 11
! 395: #define IXGB_RAIDC_POLL_MASK 0x1FF00000
! 396: #define IXGB_RAIDC_POLL_SHIFT 20
! 397: #define IXGB_RAIDC_RXT_GATE 0x40000000
! 398: #define IXGB_RAIDC_EN 0x80000000
! 399:
! 400: #define IXGB_RAIDC_POLL_1000_INTERRUPTS_PER_SECOND 1220
! 401: #define IXGB_RAIDC_POLL_5000_INTERRUPTS_PER_SECOND 244
! 402: #define IXGB_RAIDC_POLL_10000_INTERRUPTS_PER_SECOND 122
! 403: #define IXGB_RAIDC_POLL_20000_INTERRUPTS_PER_SECOND 61
! 404:
! 405: /* RXCSUM Bit Masks */
! 406: #define IXGB_RXCSUM_IPOFL 0x00000100
! 407: #define IXGB_RXCSUM_TUOFL 0x00000200
! 408:
! 409: /* RAH Bit Masks */
! 410: #define IXGB_RAH_ASEL_MASK 0x00030000
! 411: #define IXGB_RAH_ASEL_DEST 0x00000000
! 412: #define IXGB_RAH_ASEL_SRC 0x00010000
! 413: #define IXGB_RAH_AV 0x80000000
! 414:
! 415: /* TCTL Bit Masks */
! 416: #define IXGB_TCTL_TCE 0x00000001
! 417: #define IXGB_TCTL_TXEN 0x00000002
! 418: #define IXGB_TCTL_TPDE 0x00000004
! 419:
! 420: #define IXGB_TCTL_IDLE_TX_UNIT 0
! 421:
! 422: /* TXDCTL Bit Masks */
! 423: #define IXGB_TXDCTL_PTHRESH_MASK 0x0000007F
! 424: #define IXGB_TXDCTL_HTHRESH_MASK 0x00007F00
! 425: #define IXGB_TXDCTL_HTHRESH_SHIFT 8
! 426: #define IXGB_TXDCTL_WTHRESH_MASK 0x007F0000
! 427: #define IXGB_TXDCTL_WTHRESH_SHIFT 16
! 428:
! 429: /* TSPMT Bit Masks */
! 430: #define IXGB_TSPMT_TSMT_MASK 0x0000FFFF
! 431: #define IXGB_TSPMT_TSPBP_MASK 0xFFFF0000
! 432: #define IXGB_TSPMT_TSPBP_SHIFT 16
! 433:
! 434: /* PAP Bit Masks */
! 435: #define IXGB_PAP_TXPC_MASK 0x0000FFFF
! 436: #define IXGB_PAP_TXPV_MASK 0x000F0000
! 437: #define IXGB_PAP_TXPV_10G 0x00000000
! 438: #define IXGB_PAP_TXPV_1G 0x00010000
! 439: #define IXGB_PAP_TXPV_2G 0x00020000
! 440: #define IXGB_PAP_TXPV_3G 0x00030000
! 441: #define IXGB_PAP_TXPV_4G 0x00040000
! 442: #define IXGB_PAP_TXPV_5G 0x00050000
! 443: #define IXGB_PAP_TXPV_6G 0x00060000
! 444: #define IXGB_PAP_TXPV_7G 0x00070000
! 445: #define IXGB_PAP_TXPV_8G 0x00080000
! 446: #define IXGB_PAP_TXPV_9G 0x00090000
! 447: #define IXGB_PAP_TXPV_WAN 0x000F0000
! 448:
! 449: /* PCSC1 Bit Masks */
! 450: #define IXGB_PCSC1_LOOPBACK 0x00004000
! 451:
! 452: /* PCSC2 Bit Masks */
! 453: #define IXGB_PCSC2_PCS_TYPE_MASK 0x00000003
! 454: #define IXGB_PCSC2_PCS_TYPE_10GBX 0x00000001
! 455:
! 456: /* PCSS1 Bit Masks */
! 457: #define IXGB_PCSS1_LOCAL_FAULT 0x00000080
! 458: #define IXGB_PCSS1_RX_LINK_STATUS 0x00000004
! 459:
! 460: /* PCSS2 Bit Masks */
! 461: #define IXGB_PCSS2_DEV_PRES_MASK 0x0000C000
! 462: #define IXGB_PCSS2_DEV_PRES 0x00004000
! 463: #define IXGB_PCSS2_TX_LF 0x00000800
! 464: #define IXGB_PCSS2_RX_LF 0x00000400
! 465: #define IXGB_PCSS2_10GBW 0x00000004
! 466: #define IXGB_PCSS2_10GBX 0x00000002
! 467: #define IXGB_PCSS2_10GBR 0x00000001
! 468:
! 469: /* XPCSS Bit Masks */
! 470: #define IXGB_XPCSS_ALIGN_STATUS 0x00001000
! 471: #define IXGB_XPCSS_PATTERN_TEST 0x00000800
! 472: #define IXGB_XPCSS_LANE_3_SYNC 0x00000008
! 473: #define IXGB_XPCSS_LANE_2_SYNC 0x00000004
! 474: #define IXGB_XPCSS_LANE_1_SYNC 0x00000002
! 475: #define IXGB_XPCSS_LANE_0_SYNC 0x00000001
! 476:
! 477: /* XPCSTC Bit Masks */
! 478: #define IXGB_XPCSTC_BERT_TRIG 0x00200000
! 479: #define IXGB_XPCSTC_BERT_SST 0x00100000
! 480: #define IXGB_XPCSTC_BERT_PSZ_MASK 0x000C0000
! 481: #define IXGB_XPCSTC_BERT_PSZ_SHIFT 17
! 482: #define IXGB_XPCSTC_BERT_PSZ_INF 0x00000003
! 483: #define IXGB_XPCSTC_BERT_PSZ_68 0x00000001
! 484: #define IXGB_XPCSTC_BERT_PSZ_1028 0x00000000
! 485:
! 486: /* MSCA bit Masks */
! 487:
! 488: /* New Protocol Address */
! 489: #define IXGB_MSCA_NP_ADDR_MASK 0x0000FFFF
! 490: #define IXGB_MSCA_NP_ADDR_SHIFT 0
! 491:
! 492: /* Either Device Type or Register Address,depending on ST_CODE */
! 493: #define IXGB_MSCA_DEV_TYPE_MASK 0x001F0000
! 494: #define IXGB_MSCA_DEV_TYPE_SHIFT 16
! 495: #define IXGB_MSCA_PHY_ADDR_MASK 0x03E00000
! 496: #define IXGB_MSCA_PHY_ADDR_SHIFT 21
! 497: #define IXGB_MSCA_OP_CODE_MASK 0x0C000000
! 498:
! 499: /* OP_CODE == 00, Address cycle, New Protocol */
! 500:
! 501: /* OP_CODE == 01, Write operation */
! 502:
! 503: /* OP_CODE == 10, Read operation */
! 504:
! 505: /* OP_CODE == 11, Read, auto increment, New Protocol */
! 506: #define IXGB_MSCA_ADDR_CYCLE 0x00000000
! 507: #define IXGB_MSCA_WRITE 0x04000000
! 508: #define IXGB_MSCA_READ 0x08000000
! 509: #define IXGB_MSCA_READ_AUTOINC 0x0C000000
! 510: #define IXGB_MSCA_OP_CODE_SHIFT 26
! 511: #define IXGB_MSCA_ST_CODE_MASK 0x30000000
! 512:
! 513: /* ST_CODE == 00, New Protocol */
! 514:
! 515: /* ST_CODE == 01, Old Protocol */
! 516: #define IXGB_MSCA_NEW_PROTOCOL 0x00000000
! 517: #define IXGB_MSCA_OLD_PROTOCOL 0x10000000
! 518: #define IXGB_MSCA_ST_CODE_SHIFT 28
! 519:
! 520: /* Initiate command, self-clearing when command completes */
! 521: #define IXGB_MSCA_MDI_COMMAND 0x40000000
! 522:
! 523: /*MDI In Progress Enable. */
! 524: #define IXGB_MSCA_MDI_IN_PROG_EN 0x80000000
! 525:
! 526: /* MSRWD bit masks */
! 527: #define IXGB_MSRWD_WRITE_DATA_MASK 0x0000FFFF
! 528: #define IXGB_MSRWD_WRITE_DATA_SHIFT 0
! 529: #define IXGB_MSRWD_READ_DATA_MASK 0xFFFF0000
! 530: #define IXGB_MSRWD_READ_DATA_SHIFT 16
! 531:
! 532: /* Definitions for the optics devices on the MDIO bus. */
! 533: #define IXGB_PHY_ADDRESS 0x0 /* Single PHY, multiple "Devices" */
! 534:
! 535: /* Standard five-bit Device IDs. See IEEE 802.3ae, clause 45 */
! 536: #define MDIO_PMA_PMD_DID 0x01
! 537: #define MDIO_WIS_DID 0x02
! 538: #define MDIO_PCS_DID 0x03
! 539: #define MDIO_XGXS_DID 0x04
! 540:
! 541: /* Standard PMA/PMD registers and bit definitions. */
! 542:
! 543: /* Note: This is a very limited set of definitions, */
! 544:
! 545: /* only implemented features are defined. */
! 546: #define MDIO_PMA_PMD_CR1 0x0000
! 547: #define MDIO_PMA_PMD_CR1_RESET 0x8000
! 548:
! 549: #define MDIO_PMA_PMD_XPAK_VENDOR_NAME 0x803A /* XPAK/XENPAK devices
! 550: * only */
! 551:
! 552: /* Vendor-specific MDIO registers */
! 553: #define G6XXX_PMA_PMD_VS1 0xC001 /* Vendor-specific
! 554: * register */
! 555: #define G6XXX_XGXS_XAUI_VS2 0x18 /* Vendor-specific
! 556: * register */
! 557:
! 558: #define G6XXX_PMA_PMD_VS1_PLL_RESET 0x80
! 559: #define G6XXX_PMA_PMD_VS1_REMOVE_PLL_RESET 0x00
! 560: #define G6XXX_XGXS_XAUI_VS2_INPUT_MASK 0x0F /* XAUI lanes
! 561: * synchronized */
! 562:
! 563: /* Layout of a single receive descriptor. The controller assumes that this
! 564: * structure is packed into 16 bytes, which is a safe assumption with most
! 565: * compilers. However, some compilers may insert padding between the fields,
! 566: * in which case the structure must be packed in some compiler-specific
! 567: * manner. */
! 568: struct ixgb_rx_desc {
! 569: uint64_t buff_addr;
! 570: uint16_t length;
! 571: uint16_t reserved;
! 572: uint8_t status;
! 573: uint8_t errors;
! 574: uint16_t special;
! 575: };
! 576:
! 577: #define IXGB_RX_DESC_STATUS_DD 0x01
! 578: #define IXGB_RX_DESC_STATUS_EOP 0x02
! 579: #define IXGB_RX_DESC_STATUS_IXSM 0x04
! 580: #define IXGB_RX_DESC_STATUS_VP 0x08
! 581: #define IXGB_RX_DESC_STATUS_TCPCS 0x20
! 582: #define IXGB_RX_DESC_STATUS_IPCS 0x40
! 583: #define IXGB_RX_DESC_STATUS_PIF 0x80
! 584:
! 585: #define IXGB_RX_DESC_ERRORS_CE 0x01
! 586: #define IXGB_RX_DESC_ERRORS_SE 0x02
! 587: #define IXGB_RX_DESC_ERRORS_P 0x08
! 588: #define IXGB_RX_DESC_ERRORS_TCPE 0x20
! 589: #define IXGB_RX_DESC_ERRORS_IPE 0x40
! 590: #define IXGB_RX_DESC_ERRORS_RXE 0x80
! 591:
! 592: #define IXGB_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
! 593: #define IXGB_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
! 594: #define IXGB_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16
! 595: */
! 596:
! 597: /* Layout of a single transmit descriptor. The controller assumes that this
! 598: * structure is packed into 16 bytes, which is a safe assumption with most
! 599: * compilers. However, some compilers may insert padding between the fields,
! 600: * in which case the structure must be packed in some compiler-specific
! 601: * manner. */
! 602: struct ixgb_tx_desc {
! 603: uint64_t buff_addr;
! 604: uint32_t cmd_type_len;
! 605: uint8_t status;
! 606: uint8_t popts;
! 607: uint16_t vlan;
! 608: };
! 609:
! 610: #define IXGB_TX_DESC_LENGTH_MASK 0x000FFFFF
! 611: #define IXGB_TX_DESC_TYPE_MASK 0x00F00000
! 612: #define IXGB_TX_DESC_TYPE_SHIFT 20
! 613: #define IXGB_TX_DESC_CMD_MASK 0xFF000000
! 614: #define IXGB_TX_DESC_CMD_SHIFT 24
! 615: #define IXGB_TX_DESC_CMD_EOP 0x01000000
! 616: #define IXGB_TX_DESC_CMD_TSE 0x04000000
! 617: #define IXGB_TX_DESC_CMD_RS 0x08000000
! 618: #define IXGB_TX_DESC_CMD_VLE 0x40000000
! 619: #define IXGB_TX_DESC_CMD_IDE 0x80000000
! 620:
! 621: #define IXGB_TX_DESC_TYPE 0x00100000
! 622:
! 623: #define IXGB_TX_DESC_STATUS_DD 0x01
! 624:
! 625: #define IXGB_TX_DESC_POPTS_IXSM 0x01
! 626: #define IXGB_TX_DESC_POPTS_TXSM 0x02
! 627: /* Priority is in upper 3 of 16 */
! 628: #define IXGB_TX_DESC_SPECIAL_PRI_SHIFT IXGB_RX_DESC_SPECIAL_PRI_SHIFT
! 629:
! 630: struct ixgb_context_desc {
! 631: uint8_t ipcss;
! 632: uint8_t ipcso;
! 633: uint16_t ipcse;
! 634: uint8_t tucss;
! 635: uint8_t tucso;
! 636: uint16_t tucse;
! 637: uint32_t cmd_type_len;
! 638: uint8_t status;
! 639: uint8_t hdr_len;
! 640: uint16_t mss;
! 641: };
! 642:
! 643: #define IXGB_CONTEXT_DESC_CMD_TCP 0x01000000
! 644: #define IXGB_CONTEXT_DESC_CMD_IP 0x02000000
! 645: #define IXGB_CONTEXT_DESC_CMD_TSE 0x04000000
! 646: #define IXGB_CONTEXT_DESC_CMD_RS 0x08000000
! 647: #define IXGB_CONTEXT_DESC_CMD_IDE 0x80000000
! 648:
! 649: #define IXGB_CONTEXT_DESC_TYPE 0x00000000
! 650:
! 651: #define IXGB_CONTEXT_DESC_STATUS_DD 0x01
! 652:
! 653: /* Filters */
! 654: #define IXGB_RAR_ENTRIES 3 /* Number of entries in Rx Address array */
! 655: #define IXGB_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
! 656: #define IXGB_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
! 657:
! 658: #define IXGB_MEMORY_REGISTER_BASE_ADDRESS 0
! 659: #define ENET_HEADER_SIZE 14
! 660: #define ENET_FCS_LENGTH 4
! 661: #define IXGB_MAX_NUM_MULTICAST_ADDRESSES 128
! 662: #define IXGB_MIN_ENET_FRAME_SIZE_WITHOUT_FCS 60
! 663: #define IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS 1514
! 664: #define IXGB_MAX_JUMBO_FRAME_SIZE 0x3F00
! 665:
! 666: /* Phy Addresses */
! 667: #define IXGB_OPTICAL_PHY_ADDR 0x0 /* Optical Module phy address */
! 668: #define IXGB_XAUII_PHY_ADDR 0x1 /* Xauii transceiver phy address */
! 669: #define IXGB_DIAG_PHY_ADDR 0x1F /* Diagnostic Device phy address */
! 670:
! 671: /* This structure takes a 64k flash and maps it for identification commands */
! 672: struct ixgb_flash_buffer {
! 673: uint8_t manufacturer_id;
! 674: uint8_t device_id;
! 675: uint8_t filler1[0x2AA8];
! 676: uint8_t cmd2;
! 677: uint8_t filler2[0x2AAA];
! 678: uint8_t cmd1;
! 679: uint8_t filler3[0xAAAA];
! 680: };
! 681:
! 682: /*
! 683: * This is a little-endian specific check.
! 684: */
! 685: #define IS_MULTICAST(Address) \
! 686: (boolean_t)(((uint8_t *)(Address))[0] & ((uint8_t)0x01))
! 687:
! 688: /*
! 689: * Check whether an address is broadcast.
! 690: */
! 691: #define IS_BROADCAST(Address) \
! 692: ((((uint8_t *)(Address))[0] == ((uint8_t)0xff)) && (((uint8_t *)(Address))[1] == ((uint8_t)0xff)))
! 693:
! 694: /* Flow control parameters */
! 695: struct ixgb_fc {
! 696: uint32_t high_water; /* Flow Control High-water */
! 697: uint32_t low_water; /* Flow Control Low-water */
! 698: uint16_t pause_time; /* Flow Control Pause timer */
! 699: boolean_t send_xon; /* Flow control send XON */
! 700: ixgb_fc_type type; /* Type of flow control */
! 701: };
! 702:
! 703: /* The historical defaults for the flow control values are given below. */
! 704: #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
! 705: #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
! 706: #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
! 707:
! 708: /* Phy definitions */
! 709: #define IXGB_MAX_PHY_REG_ADDRESS 0xFFFF
! 710: #define IXGB_MAX_PHY_ADDRESS 31
! 711: #define IXGB_MAX_PHY_DEV_TYPE 31
! 712:
! 713: /* Bus parameters */
! 714: struct ixgb_bus {
! 715: ixgb_bus_speed speed;
! 716: ixgb_bus_width width;
! 717: ixgb_bus_type type;
! 718: };
! 719:
! 720: struct ixgb_hw {
! 721: uint8_t *hw_addr; /* Base Address of the hardware */
! 722: void *back; /* Pointer to OS-dependent struct */
! 723: struct ixgb_fc fc; /* Flow control parameters */
! 724: struct ixgb_bus bus; /* Bus parameters */
! 725: uint32_t phy_id; /* Phy Identifier */
! 726: uint32_t phy_addr; /* XGMII address of Phy */
! 727: ixgb_mac_type mac_type; /* Identifier for MAC controller */
! 728: ixgb_phy_type phy_type; /* Transceiver/phy identifier */
! 729: uint32_t max_frame_size; /* Maximum frame size supported */
! 730: uint32_t mc_filter_type; /* Multicast filter hash type */
! 731: uint32_t num_mc_addrs; /* Number of current Multicast addrs */
! 732: /* Individual address currently programmed in MAC */
! 733: uint8_t curr_mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS];
! 734: uint32_t num_tx_desc; /* Number of Transmit descriptors */
! 735: uint32_t num_rx_desc; /* Number of Receive descriptors */
! 736: uint32_t rx_buffer_size; /* Size of Receive buffer */
! 737: boolean_t link_up; /* TRUE if link is valid */
! 738: boolean_t adapter_stopped; /* State of adapter */
! 739: uint16_t device_id; /* device id from PCI configuration space */
! 740: uint16_t vendor_id; /* vendor id from PCI configuration space */
! 741: uint8_t revision_id; /* revision id from PCI configuration space */
! 742: uint16_t subsystem_vendor_id; /* subsystem vendor id from PCI
! 743: * configuration space */
! 744: uint16_t subsystem_id; /* subsystem id from PCI configuration space */
! 745: uint32_t bar0; /* Base Address registers */
! 746: uint32_t bar1;
! 747: uint32_t bar2;
! 748: uint32_t bar3;
! 749: uint16_t pci_cmd_word; /* PCI command register id from PCI
! 750: * configuration space */
! 751: uint16_t eeprom[IXGB_EEPROM_SIZE]; /* EEPROM contents read at init
! 752: * time */
! 753: unsigned long io_base; /* Our I/O mapped location */
! 754: uint32_t lastLFC;
! 755: uint32_t lastRFC;
! 756: };
! 757:
! 758: /* Statistics reported by the hardware */
! 759: struct ixgb_hw_stats {
! 760: uint64_t tprl;
! 761: uint64_t tprh;
! 762: uint64_t gprcl;
! 763: uint64_t gprch;
! 764: uint64_t bprcl;
! 765: uint64_t bprch;
! 766: uint64_t mprcl;
! 767: uint64_t mprch;
! 768: uint64_t uprcl;
! 769: uint64_t uprch;
! 770: uint64_t vprcl;
! 771: uint64_t vprch;
! 772: uint64_t jprcl;
! 773: uint64_t jprch;
! 774: uint64_t gorcl;
! 775: uint64_t gorch;
! 776: uint64_t torl;
! 777: uint64_t torh;
! 778: uint64_t rnbc;
! 779: uint64_t ruc;
! 780: uint64_t roc;
! 781: uint64_t rlec;
! 782: uint64_t crcerrs;
! 783: uint64_t icbc;
! 784: uint64_t ecbc;
! 785: uint64_t mpc;
! 786: uint64_t tptl;
! 787: uint64_t tpth;
! 788: uint64_t gptcl;
! 789: uint64_t gptch;
! 790: uint64_t bptcl;
! 791: uint64_t bptch;
! 792: uint64_t mptcl;
! 793: uint64_t mptch;
! 794: uint64_t uptcl;
! 795: uint64_t uptch;
! 796: uint64_t vptcl;
! 797: uint64_t vptch;
! 798: uint64_t jptcl;
! 799: uint64_t jptch;
! 800: uint64_t gotcl;
! 801: uint64_t gotch;
! 802: uint64_t totl;
! 803: uint64_t toth;
! 804: uint64_t dc;
! 805: uint64_t plt64c;
! 806: uint64_t tsctc;
! 807: uint64_t tsctfc;
! 808: uint64_t ibic;
! 809: uint64_t rfc;
! 810: uint64_t lfc;
! 811: uint64_t pfrc;
! 812: uint64_t pftc;
! 813: uint64_t mcfrc;
! 814: uint64_t mcftc;
! 815: uint64_t xonrxc;
! 816: uint64_t xontxc;
! 817: uint64_t xoffrxc;
! 818: uint64_t xofftxc;
! 819: uint64_t rjc;
! 820: };
! 821:
! 822: /* Function Prototypes */
! 823: extern boolean_t ixgb_adapter_stop(struct ixgb_hw *hw);
! 824: extern boolean_t ixgb_init_hw(struct ixgb_hw *hw);
! 825: extern boolean_t ixgb_adapter_start(struct ixgb_hw *hw);
! 826: extern void ixgb_check_for_link(struct ixgb_hw *hw);
! 827: extern boolean_t ixgb_check_for_bad_link(struct ixgb_hw *hw);
! 828: extern void ixgb_rar_set(struct ixgb_hw *hw, uint8_t *addr, uint32_t index);
! 829: extern void ixgb_init_rx_addrs(struct ixgb_hw *hw);
! 830: extern boolean_t ixgb_setup_fc(struct ixgb_hw *hw);
! 831: extern void ixgb_clear_hw_cntrs(struct ixgb_hw *hw);
! 832: extern boolean_t mac_addr_valid(uint8_t *mac_addr);
! 833:
! 834: extern uint16_t ixgb_read_phy_reg(struct ixgb_hw *hw, uint32_t reg_addr,
! 835: uint32_t phy_addr, uint32_t device_type);
! 836:
! 837: extern void ixgb_write_phy_reg(struct ixgb_hw *hw, uint32_t reg_addr,
! 838: uint32_t phy_addr, uint32_t device_type,
! 839: uint16_t data);
! 840:
! 841:
! 842: /* Filters (multicast, vlan, receive) */
! 843: extern void ixgb_mc_addr_list_update(struct ixgb_hw *hw, uint8_t *mc_addr_list,
! 844: uint32_t mc_addr_count, uint32_t pad);
! 845:
! 846: /* Vfta functions */
! 847: extern void ixgb_write_vfta(struct ixgb_hw *hw, uint32_t offset,
! 848: uint32_t value);
! 849:
! 850: extern void ixgb_clear_vfta(struct ixgb_hw *hw);
! 851:
! 852: /* Access functions to eeprom data */
! 853: void ixgb_get_ee_mac_addr(struct ixgb_hw *hw, uint8_t *mac_addr);
! 854: uint32_t ixgb_get_ee_pba_number(struct ixgb_hw *hw);
! 855: uint16_t ixgb_get_ee_device_id(struct ixgb_hw *hw);
! 856: boolean_t ixgb_get_eeprom_data(struct ixgb_hw *hw);
! 857: uint16_t ixgb_get_eeprom_word(struct ixgb_hw *hw, uint16_t index);
! 858:
! 859: /* Everything else */
! 860: void ixgb_led_on(struct ixgb_hw *hw);
! 861: void ixgb_led_off(struct ixgb_hw *hw);
! 862: void ixgb_write_pci_cfg(struct ixgb_hw *hw, uint32_t reg, uint16_t *value);
! 863:
! 864: #endif /* _IXGB_HW_H_ */
CVSweb
![[BACK]](/icons/back.gif){kind=icon}
Return to ixgb_hw.h CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / dev / pci