Annotation of sys/dev/pci/isesreg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: isesreg.h,v 1.10 2007/05/25 21:27:16 krw Exp $ $ */
! 2:
! 3: /*
! 4: * Copyright (c) 2000 Håkan Olsson (ho@crt.se)
! 5: * Copyright (c) 2000 Theo de Raadt
! 6: *
! 7: * Redistribution and use in source and binary forms, with or without
! 8: * modification, are permitted provided that the following conditions
! 9: * are met:
! 10: *
! 11: * 1. Redistributions of source code must retain the above copyright
! 12: * notice, this list of conditions and the following disclaimer.
! 13: * 2. Redistributions in binary form must reproduce the above copyright
! 14: * notice, this list of conditions and the following disclaimer in the
! 15: * documentation and/or other materials provided with the distribution.
! 16: *
! 17: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 18: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
! 19: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
! 20: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
! 21: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
! 22: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
! 23: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
! 24: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
! 25: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
! 26: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
! 27: */
! 28:
! 29: /*
! 30: * Register definitions for Pijnenburg PCC-ISES crypto chip.
! 31: * Definitions from revision 1.6 of the product datasheet.
! 32: */
! 33:
! 34: /*
! 35: * PCC-ISES Evaluation board DMA offsets
! 36: */
! 37: #define ISES_DMA_READ_COUNT 0x0100 /* bit 31-16 */
! 38: #define ISES_DMA_RCOUNT(x) ((x) << 16)
! 39: #define ISES_DMA_WRITE_COUNT 0x0100 /* bit 15-0 */
! 40: #define ISES_DMA_WCOUNT(x) ((x) & 0x00FF)
! 41:
! 42: #define ISES_DMA_WRITE_START 0x0104
! 43: #define ISES_DMA_READ_START 0x0108
! 44: #define ISES_DMA_CTRL 0x010C
! 45: #define ISES_DMA_STATUS ISES_DMA_CTRL
! 46: #define ISES_DMA_RESET 0x0110
! 47:
! 48: #define ISES_DMA_CTRL_ILT 0x40000000 /* Ignore Latency Timer */
! 49: #define ISES_DMA_CTRL_RMULT 0x0D000000 /* Enable PCI Read Multiple */
! 50: #define ISES_DMA_CTRL_RLINE 0x09000000 /* Enable PCI Read Line */
! 51: #define ISES_DMA_CTRL_READ 0x01000000 /* Enable PCI Read */
! 52: #define ISES_DMA_CTRL_WRITE 0x00000100 /* Enable PCI Write */
! 53:
! 54: #define ISES_DMA_STATUS_R_RUN 0x01000000 /* PCI Read running */
! 55: #define ISES_DMA_STATUS_R_ERR 0x02000000 /* PCI Read error */
! 56: #define ISES_DMA_STATUS_W_RUN 0x00000100 /* PCI Write running */
! 57: #define ISES_DMA_STATUS_W_ERR 0x00000200 /* PCI Write error */
! 58:
! 59: /*
! 60: * PCC-ISES A-interface
! 61: */
! 62:
! 63: #define ISES_A_OFFSET 0x0200
! 64: #define ISES_A(x) (ISES_A_OFFSET + (x))
! 65:
! 66: #define ISES_A_STAT ISES_A(0x00) /* status register */
! 67: #define ISES_A_INTS ISES_A(0x04) /* interrupt status register */
! 68: #define ISES_A_INTE ISES_A(0x08) /* interrupt enable register */
! 69: #define ISES_A_SREQ ISES_A(0x0C) /* service request (read) */
! 70: #define ISES_A_CTRL ISES_A_SREQ /* control register (write) */
! 71: #define ISES_A_OQD ISES_A(0x10) /* Output Queue Data (read) */
! 72: #define ISES_A_IQD ISES_A_OQD /* Input Queue Data (write) */
! 73: #define ISES_A_OQS ISES_A(0x14) /* Output Queue Semaphore */
! 74: #define ISES_A_IQS ISES_A(0x18) /* Input Queue Semaphore */
! 75: #define ISES_A_OQF ISES_A(0x1C) /* Output Queue Filled (ro) */
! 76: #define ISES_A_IQF ISES_A(0x20) /* Input Queue Free (ro) */
! 77:
! 78: /*
! 79: * PCC-ISES B-interface
! 80: */
! 81:
! 82: #define ISES_B_OFFSET 0x0300
! 83: #define ISES_B(x) (ISES_B_OFFSET + (x))
! 84:
! 85: #define ISES_B_BDATAIN ISES_B(0x0)
! 86: #define ISES_B_BDATAOUT ISES_B(0x4)
! 87: #define ISES_B_STAT ISES_B(0x8)
! 88:
! 89: /*
! 90: * PCC-ISES I-interface (not used)
! 91: */
! 92:
! 93: #define ISES_I_OFFSET 0x0400
! 94:
! 95: /*
! 96: * PCC-ISES board registers
! 97: */
! 98:
! 99: #define ISES_BO_OFFSET 0x0500
! 100: #define ISES_BO(x) (ISES_BO_OFFSET + (x))
! 101:
! 102: #define ISES_BO_STAT ISES_BO(0x0)
! 103: #define ISES_BO_LOOPCOUNTER ISES_BO(0x4)
! 104: #define ISES_BO_TESTREG ISES_BO(0x8)
! 105:
! 106: #define ISES_BO_STAT_LOOP 0x00000001 /* B-interface LoopMode */
! 107: #define ISES_BO_STAT_TAMPER 0x00000002 /* Set tamper */
! 108: #define ISES_BO_STAT_POWERDOWN 0x00000004 /* Set power down */
! 109: #define ISES_BO_STAT_ACONF 0x00000008 /* Set A-intf access to 16b */
! 110: #define ISES_BO_STAT_HWRESET 0x00000010 /* Reset PCC-ISES (hw) */
! 111: #define ISES_BO_STAT_AIRQ 0x00000020 /* A-interface interrupt (ro)*/
! 112:
! 113: /*
! 114: * PCC-ISES A-interface STAT register bits
! 115: */
! 116:
! 117: #define ISES_STAT_LNAU_MASKED 0x00000001 /* LNAU flags masked, this bit
! 118: must be zero for the other
! 119: LNAU flags to be read
! 120: correctly. */
! 121: #define ISES_STAT_LNAU_BUSY_1 0x00000002 /* LNAU unit 1 is busy */
! 122: #define ISES_STAT_LNAU_ERR_1 0x00000004 /* LNAU unit 1 error */
! 123: #define ISES_STAT_LNAU_BUSY_2 0x00000008 /* LNAU unit 2 is busy */
! 124: #define ISES_STAT_LNAU_ERR_2 0x00000010 /* LNAU unit 2 error */
! 125: #define ISES_STAT_BCHU_MASKED 0x00000020 /* BCHU flags masked */
! 126: #define ISES_STAT_BCHU_BUSY 0x00000040 /* BCHU is busy */
! 127: #define ISES_STAT_BCHU_ERR 0x00000080 /* BCHU error flag */
! 128: #define ISES_STAT_BCHU_SCIF 0x00000100 /* symm. crypto inoperative */
! 129: #define ISES_STAT_BCHU_HIF 0x00000200 /* hash unit inoperative */
! 130: #define ISES_STAT_BCHU_DDB 0x00000400 /* discard data blocks */
! 131: #define ISES_STAT_BCHU_IRF 0x00000800 /* input request flag */
! 132: #define ISES_STAT_BCHU_OAF 0x00001000 /* output available flag */
! 133: #define ISES_STAT_BCHU_DIE 0x00002000 /* data input enabled */
! 134: #define ISES_STAT_BCHU_UE 0x00004000 /* unit enable bit */
! 135: #define ISES_STAT_BCHU_IFE 0x00008000 /* input FIFO empty */
! 136: #define ISES_STAT_BCHU_IFHE 0x00010000 /* input FIFO half emtpy */
! 137: #define ISES_STAT_BCHU_IFF 0x00020000 /* input FIFO full */
! 138: #define ISES_STAT_BCHU_OFE 0x00040000 /* output FIFO emtpy */
! 139: #define ISES_STAT_BCHU_OFHF 0x00080000 /* output FIFO half full */
! 140: #define ISES_STAT_BCHU_OFF 0x00100000 /* output FIFO full */
! 141: #define ISES_STAT_HW_DA 0x00200000 /* downloaded appl flag */
! 142: #define ISES_STAT_HW_ACONF 0x00400000 /* A-intf configuration flag */
! 143: #define ISES_STAT_SW_WFOQ 0x00800000 /* SW: Waiting for out queue */
! 144: #define ISES_STAT_SW_OQSINC 0x08000000 /* SW 2.x: OQS increased */
! 145:
! 146: #define ISES_STAT_IDP_MASK 0x0f000000 /* IDP state mask (HW_DA=0) */
! 147: #define ISES_STAT_IDP_STATE(x) (((x) & ISES_STAT_IDP_MASK) >> 24)
! 148: #define ISES_IDP_WFPL 0x4 /* Waiting for pgm len state */
! 149:
! 150: static const char *ises_idp_state[] =
! 151: {
! 152: "reset state", /* 0x0 */
! 153: "testing NSRAM", /* 0x1 */
! 154: "checking for firmware", /* 0x2 */
! 155: "clearing NSRAM", /* 0x3 */
! 156: "waiting for program length", /* 0x4 */
! 157: "waiting for program data", /* 0x5 */
! 158: "waiting for program CRC", /* 0x6 */
! 159: "functional test program", /* 0x7 */
! 160: 0, 0, 0, 0, 0, 0, 0, /* 0x8-0xe */
! 161: "Error: NSRAM or firmware failed" /* 0xf */
! 162: };
! 163:
! 164: #define ISES_STAT_SW_MASK 0x03000000 /* SW mode (HW_DA=1) */
! 165: #define ISES_STAT_SW_MODE(x) (((x) & ISES_STAT_SW_MASK) >> 24)
! 166:
! 167: #define ISES_A_CTRL_RESET 0x0000 /* SW reset (go to ST mode) */
! 168: #define ISES_A_CTRL_CONTINUE 0x0001 /* Return to CMD from WFC */
! 169:
! 170: #ifdef ISESDEBUG
! 171: static const char *ises_sw_mode[] =
! 172: {
! 173: "ST (SelfTest)", /* 0x0 */
! 174: "CMD", /* 0x1 (normal) */
! 175: "WFC (Wait for continue)", /* 0x2 */
! 176: "CMD (Wait for reset)" /* 0x3 */
! 177: };
! 178: #endif
! 179:
! 180: /* BERR (BCHU Error Register) */
! 181: #define ISES_BERR_DPAR 0x00000001 /* DES parity error */
! 182: #define ISES_BERR_IDESBCP 0x00000002 /* illegal DES mode value */
! 183: #define ISES_BERR_ISFRBCP 0x00000004 /* illegal SAFER rounds spec */
! 184: #define ISES_BERR_INCMBCP 0x00000008 /* illegal non-crypto mode */
! 185: #define ISES_BERR_IBCF 0x00000010 /* illegal value in BCFR */
! 186: #define ISES_BERR_reserved 0x00000020 /* reserved */
! 187: #define ISES_BERR_SRB 0x00000040 /* write SCU while busy */
! 188: #define ISES_BERR_HRB 0x00000080 /* write HU while busy */
! 189: #define ISES_BERR_IHFR 0x00000100 /* illegal value in HFR */
! 190: #define ISES_BERR_PADERR 0x00000200 /* padding error */
! 191: #define ISES_BERR_BIDM 0x00000400 /* B-interface input data
! 192: misalignment */
! 193: /* BCHCR (BCHU Control Register) */
! 194: #define ISES_BCHCR_BCHU_DIE 0x00000001 /* data input enabled */
! 195: #define ISES_BCHCR_BCHU_UE 0x00000002 /* unit enable */
! 196: #define ISES_BCHCR_BCHU_RST 0x00000004 /* BCHU reset */
! 197:
! 198: /*
! 199: * OMR (Operation Method Register)
! 200: */
! 201: /* -- SELR (Selector Register) */
! 202: #define ISES_SELR_BCHU_EH 0x80000000 /* stop/continue on error */
! 203: #define ISES_SELR_BCHU_HISOF 0x01000000 /* HU input is SCU output */
! 204: #define ISES_SELR_BCHU_DIS 0x02000000 /* data interface select */
! 205:
! 206: /* -- HOMR (HU Operation Mode Register) */
! 207: #define ISES_HOMR_HMTR 0x00800000 /* hash message type reg bit */
! 208: #define ISES_HOMR_ER 0x00300000 /* BE/LE, 2bit mask */
! 209:
! 210: #define ISES_HOMR_HFR 0x00070000 /* Hash function mask, 3bits */
! 211: #define ISES_HOMR_HFR_NOP 0x00000000 /* NOP */
! 212: #define ISES_HOMR_HFR_MD5 0x00010000 /* MD5 */
! 213: #define ISES_HOMR_HFR_RMD160 0x00020000 /* RIPEMD-160 */
! 214: #define ISES_HOMR_HFR_RMD128 0x00030000 /* RIPEMD-128 */
! 215: #define ISES_HOMR_HFR_SHA1 0x00040000 /* SHA-1 */
! 216:
! 217: /* -- SOMR (Symmetric crypto Operation Method Register) */
! 218: #define ISES_SOMR_BCFR 0x0000f000 /* block cipher function reg */
! 219: #define ISES_SOMR_BCPR 0x00000ff0 /* block cipher parameters */
! 220: #define ISES_SOMR_BOMR (ISES_SOMR_BCFR | ISES_SOMR_BCPR)
! 221: #define ISES_SOMR_BOMR_NOP 0x00000000 /* NOP */
! 222: #define ISES_SOMR_BOMR_TRANSPARENT 0x00000010 /* Transparent */
! 223: #define ISES_SOMR_BOMR_DES 0x00001000 /* DES */
! 224: #define ISES_SOMR_BOMR_3DES2 0x00001010 /* 3DES-2 */
! 225: #define ISES_SOMR_BOMR_3DES 0x00001020 /* 3DES-3 */
! 226: #define ISES_SOMR_BOMR_SAFER 0x00002000 /* SAFER (actually more) */
! 227: #define ISES_SOMR_EDR 0x00000008 /* Encrypt/Decrypt register */
! 228: #define ISES_SOMR_FMR 0x00000003 /* feedback mode mask */
! 229: #define ISES_SOMR_FMR_ECB 0x00000000 /* EBC */
! 230: #define ISES_SOMR_FMR_CBC 0x00000001 /* CBC */
! 231: #define ISES_SOMR_FMR_CFB64 0x00000002 /* CFB64 */
! 232: #define ISES_SOMR_FMR_OFB64 0x00000003 /* OFB64 */
! 233:
! 234: /*
! 235: * HRNG (Hardware Random Number Generator)
! 236: */
! 237: #define ISES_OFFSET_HRNG_CTRL 0x00 /* Control register */
! 238: #define ISES_OFFSET_HRNG_LFSR 0x04 /* Linear feedback shift reg */
! 239: #define ISES_HRNG_CTRL_HE 0x00000001 /* HRNG enable */
! 240:
! 241: /*
! 242: * A-interface commands
! 243: */
! 244: #define ISES_MKCMD(cmd,len) (cmd | cmd << 16 | len << 8 | len << 24)
! 245: #define ISES_CMD_NONE -1
! 246:
! 247: /* Command name Code Len RLen Desc */
! 248: #define ISES_CMD_CHIP_ID 0x00 /* 0 3 Read chipID */
! 249: /* LNAU commands - LNAU 1 */
! 250: #define ISES_CMD_LRESET_1 0x01 /* 0 0 LNAU reset */
! 251: #define ISES_CMD_LRSFLG_1 0x02 /* 0 0 LNAU flags reset */
! 252: #define ISES_CMD_LUPLOAD_1 0x03 /* 0 64 Upload result */
! 253: #define ISES_CMD_LW_A_1 0x04 /* ?64 0 Load A register */
! 254: #define ISES_CMD_LW_B_1 0x05 /* ?64 0 Load B register */
! 255: #define ISES_CMD_LW_N_1 0x06 /* ?64 0 Load N register */
! 256: #define ISES_CMD_LW_Bq_1 0x07 /* ?32 0 Load Bq register */
! 257: #define ISES_CMD_LW_Nq_1 0x08 /* ?32 0 Load Nq register */
! 258: #define ISES_CMD_LW_Bp_1 0x09 /* ?34 0 Load Bp register */
! 259: #define ISES_CMD_LW_Np_1 0x0a /* ?34 0 Load Np register */
! 260: #define ISES_CMD_LW_U_1 0x0b /* ?34 0 Load U register */
! 261: #define ISES_CMD_LMOD_1 0x0c /* 0 0 Start A % N */
! 262: #define ISES_CMD_LMULMOD_1 0x0d /* 0 0 Start (A*B) % N */
! 263: #define ISES_CMD_LEXPMOD_1 0x0e /* 0 0 Start (A^B) % N */
! 264: #define ISES_CMD_LEXPCRTMOD_1 0x0f /* 0 0 Start (A^B)%N w/ CRT */
! 265: /* LNAU commands - LNAU 2 */
! 266: #define ISES_CMD_LRESET_2 0x10 /* 0 0 Reset */
! 267: #define ISES_CMD_LRSFLG_2 0x11 /* 0 0 Flags reset */
! 268: #define ISES_CMD_LUPLOAD_2 0x12 /* 0 64 Upload result */
! 269: #define ISES_CMD_LW_A_2 0x13 /* ?64 0 Load A register */
! 270: #define ISES_CMD_LW_B_2 0x14 /* ?64 0 Load B register */
! 271: #define ISES_CMD_LW_N_2 0x15 /* ?64 0 Load N register */
! 272: #define ISES_CMD_LW_Bq_2 0x16 /* ?32 0 Load Bq register */
! 273: #define ISES_CMD_LW_Nq_2 0x17 /* ?32 0 Load Nq register */
! 274: #define ISES_CMD_LW_Bp_2 0x18 /* ?34 0 Load Bp register */
! 275: #define ISES_CMD_LW_Np_2 0x19 /* ?34 0 Load Np register */
! 276: #define ISES_CMD_LW_U_2 0x1a /* ?34 0 Load U register */
! 277: #define ISES_CMD_LMOD_2 0x1b /* 0 0 Start A % N */
! 278: #define ISES_CMD_LMULMOD_2 0x1c /* 0 0 Start (A*B) % N */
! 279: #define ISES_CMD_LEXPMOD_2 0x1d /* 0 0 Start (A^B) % N */
! 280: #define ISES_CMD_LEXPCRTMOD_2 0x1e /* 0 0 Start (A^B)%N w/ CRT */
! 281: /* BCHU commands */
! 282: #define ISES_CMD_RST_BERR 0x1f /* 0 0 Reset BERR */
! 283: #define ISES_CMD_BR_BERR 0x20 /* 0 0 Read BERR */
! 284: #define ISES_CMD_BW_DATA 0x21 /* 2 0 Write DATA */
! 285: #define ISES_CMD_BR_DATA 0x22 /* 0 2 Read DATA */
! 286: #define ISES_CMD_BW_BCHCR 0x23 /* 1 0 Write BCHCR */
! 287: #define ISES_CMD_BR_BCHCR 0x24 /* 0 0 Read BCHCR */
! 288: #define ISES_CMD_BW_OMR 0x25 /* 1 0 Write OMR */
! 289: #define ISES_CMD_BR_OMR 0x26 /* 0 1 Read OMR */
! 290: #define ISES_CMD_BW_KR0 0x27 /* 2 0 Write key 0 */
! 291: #define ISES_CMD_BR_KR0 0x28 /* 0 2 Read key 0 */
! 292: #define ISES_CMD_BW_KR1 0x29 /* 2 0 Write key 1 */
! 293: #define ISES_CMD_BR_KR1 0x2a /* 0 2 Read key 1 */
! 294: #define ISES_CMD_BW_KR2 0x2b /* 2 0 Write key 2 */
! 295: #define ISES_CMD_BR_KR2 0x2c /* 0 2 Read key 2 */
! 296: #define ISES_CMD_BW_SCCR 0x2d /* 2 0 Write SCCR */
! 297: #define ISES_CMD_BR_SCCR 0x2e /* 0 2 Read SCCR */
! 298: #define ISES_CMD_BW_DBCR 0x2f /* 2 0 Write DBCR */
! 299: #define ISES_CMD_BR_DBCR 0x30 /* 0 2 Read DBCR */
! 300: #define ISES_CMD_BW_HMLR 0x31 /* 2 0 Write HMLR */
! 301: #define ISES_CMD_BR_HMLR 0x32 /* 0 2 Read HMLR */
! 302: #define ISES_CMD_BW_CVR 0x33 /* 5 0 Write CVR */
! 303: #define ISES_CMD_BR_CVR 0x34 /* 0 5 Read CVR */
! 304: #define ISES_CMD_BPROC 0x35 /* ?255 ?255 Process data blocks */
! 305: #define ISES_CMD_BTERM 0x36 /* 0 0 Terminate session */
! 306: #define ISES_CMD_BSWITCH 0x37 /* 18 18 Switch BCHU session */
! 307: /* HRNG commands */
! 308: #define ISES_CMD_HSTART 0x38 /* 0 0 Start RBG unit */
! 309: #define ISES_CMD_HSTOP 0x39 /* 0 0 Stop RGB unit */
! 310: #define ISES_CMD_HSEED 0x3a /* 1 0 Seed LFSR */
! 311: #define ISES_CMD_HBITS 0x3b /* 1 ?255 Return n*32 rnd bits */
! 312:
! 313: /* Command return codes (RC) */
! 314: #define ISES_RC_MASK 0x0000ffff
! 315: #define ISES_RC_SUCCESS 0x0000 /* success */
! 316: #define ISES_RC_CMDERR 0x0001 /* cmd interpretation error */
! 317: #define ISES_RC_QERR 0x0002 /* queue handling error */
! 318: #define ISES_RC_LNAU_ERR 0x0003 /* LNAU cmd proc error */
! 319: #define ISES_RC_BCHU_ERR 0x0004 /* BCHU cmd proc error */
! 320: #define ISES_RC_BCHU_BIFCSEL 0x0005 /* OMR says B-if, must be A */
! 321: #define ISES_RC_BCHU_ODD 0x0006 /* odd #words in param list */
! 322: #define ISES_RC_HRNG_ILLEN 0x0007 /* too large bitstream */
! 323:
! 324: /* Interrupt bits, IRQE, IRQES, IRQEC, IRQSS, IRQ registers */
! 325: #define ISES_IRQ_TIMER_1 0x00000001 /* Timer 1 reached zero */
! 326: #define ISES_IRQ_TIMER_2 0x00000002 /* Timer 2 reached zero */
! 327: #define ISES_IRQ_I_IIN0 0x00000004 /* I-int 'Iin0' */
! 328: #define ISES_IRQ_I_IIN1 0x00000008 /* I-int 'Iin1' */
! 329: #define ISES_IRQ_I_IIN2 0x00000010 /* I-int 'Iin2' */
! 330: #define ISES_IRQ_I_IIN3 0x00000020 /* I-int 'Iin3' */
! 331: #define ISES_IRQ_LNAU_1_ERROR 0x00000040 /* LNAU 1 op error/abort */
! 332: #define ISES_IRQ_LNAU_1_DONE 0x00000080 /* LNAU 1 op done */
! 333: #define ISES_IRQ_LNAU_2_ERROR 0x00000100 /* LNAU 2 op error/abort */
! 334: #define ISES_IRQ_LNAU_2_DONE 0x00000200 /* LNAU 1 op done */
! 335: #define ISES_IRQ_BCHU_DONE 0x00000400 /* BCHU operation done */
! 336: #define ISES_IRQ_BCHU_ERROR 0x00000800 /* BCHU operation error/abrt */
! 337: #define ISES_IRQ_BCHU_IRF 0x00001000 /* BCHU input request flag >1*/
! 338: #define ISES_IRQ_BCHU_OAF 0x00002000 /* BCHU output avail flag >1 */
! 339: #define ISES_IRQ_BCHU_IEF 0x00004000 /* BCHU input empty flag >1 */
! 340: #define ISES_IRQ_A_WCTRL 0x00008000 /* A-int CTRL reg was written*/
! 341: #define ISES_IRQ_A_RSREQ 0x00010000 /* A-int SREQ reg was read */
! 342: #define ISES_IRQ_A_DIQ 0x00020000 /* in queue emtpy, IQD write */
! 343: #define ISES_IRQ_A_CIQ 0x00040000 /* in queue has complete cmd */
! 344: #define ISES_IRQ_A_OQF 0x00080000 /* output queue full */
! 345:
! 346: #define ISES_SESSION(sid) ( (sid) & 0x0fffffff)
! 347: #define ISES_CARD(sid) (((sid) & 0xf0000000) >> 28)
! 348: #define ISES_SID(crd,ses) (((crd) << 28) | ((ses) & 0x0fffffff))
! 349:
! 350: /* Size and layout of ises_session is firmware dependent. */
! 351: /* This structure should be usable for the SWITCH_SESSION command. */
! 352: struct ises_session {
! 353: u_int32_t kr[6]; /* Key register KR2,KR1,KR0 */
! 354: u_int32_t omr; /* Operation method register */
! 355:
! 356: /* The following values (on-chip) are cleared after an OMR write */
! 357: u_int32_t sccr[2]; /* Symm. crypto chaining reg. (IV) */
! 358: u_int32_t cvr[5]; /* Chaining variables reg. */
! 359: u_int32_t dbcr[2]; /* Data block count register */
! 360: u_int32_t hmlr[2]; /* Hash message length reg. */
! 361: } __attribute__((packed));
! 362:
! 363: #define ISES_B_DATASIZE 4096
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