Annotation of sys/dev/pci/if_wpireg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: if_wpireg.h,v 1.17 2007/07/24 16:07:47 damien Exp $ */
2:
3: /*-
4: * Copyright (c) 2006, 2007
5: * Damien Bergamini <damien.bergamini@free.fr>
6: *
7: * Permission to use, copy, modify, and distribute this software for any
8: * purpose with or without fee is hereby granted, provided that the above
9: * copyright notice and this permission notice appear in all copies.
10: *
11: * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12: * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13: * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14: * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15: * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16: * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17: * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18: */
19:
20: #define WPI_TX_RING_COUNT 256
21: #define WPI_CMD_RING_COUNT 256
22: #define WPI_RX_RING_COUNT 64
23:
24: /*
25: * Rings must be aligned on a 16K boundary.
26: * I had a hard time figuring this out.
27: */
28: #define WPI_RING_DMA_ALIGN 0x4000
29:
30: /* maximum scatter/gather */
31: #define WPI_MAX_SCATTER 4
32:
33: /* maximum Rx buffer size (larger than MCLBYTES) */
34: #define WPI_RBUF_SIZE (3 * 1024) /* XXX 3000 but must be aligned! */
35:
36: /*
37: * Control and status registers.
38: */
39: #define WPI_HWCONFIG 0x000
40: #define WPI_INTR 0x008
41: #define WPI_MASK 0x00c
42: #define WPI_INTR_STATUS 0x010
43: #define WPI_GPIO_STATUS 0x018
44: #define WPI_RESET 0x020
45: #define WPI_GPIO_CTL 0x024
46: #define WPI_EEPROM_CTL 0x02c
47: #define WPI_EEPROM_STATUS 0x030
48: #define WPI_UCODE_CLR 0x05c
49: #define WPI_TEMPERATURE 0x060
50: #define WPI_CHICKEN 0x100
51: #define WPI_PLL_CTL 0x20c
52: #define WPI_WRITE_MEM_ADDR 0x444
53: #define WPI_READ_MEM_ADDR 0x448
54: #define WPI_WRITE_MEM_DATA 0x44c
55: #define WPI_READ_MEM_DATA 0x450
56: #define WPI_TX_WIDX 0x460
57: #define WPI_TX_CTL(qid) (0x940 + (qid) * 8)
58: #define WPI_TX_BASE(qid) (0x944 + (qid) * 8)
59: #define WPI_TX_DESC(qid) (0x980 + (qid) * 80)
60: #define WPI_RX_CONFIG 0xc00
61: #define WPI_RX_BASE 0xc04
62: #define WPI_RX_WIDX 0xc20
63: #define WPI_RX_RIDX_PTR 0xc24
64: #define WPI_RX_CTL 0xcc0
65: #define WPI_RX_STATUS 0xcc4
66: #define WPI_TX_CONFIG(qid) (0xd00 + (qid) * 32)
67: #define WPI_TX_CREDIT(qid) (0xd04 + (qid) * 32)
68: #define WPI_TX_STATE(qid) (0xd08 + (qid) * 32)
69: #define WPI_TX_BASE_PTR 0xe80
70: #define WPI_MSG_CONFIG 0xe88
71: #define WPI_TX_STATUS 0xe90
72:
73:
74: /*
75: * NIC internal memory offsets.
76: */
77: #define WPI_MEM_MODE 0x2e00
78: #define WPI_MEM_RA 0x2e04
79: #define WPI_MEM_TXCFG 0x2e10
80: #define WPI_MEM_MAGIC4 0x2e14
81: #define WPI_MEM_MAGIC5 0x2e20
82: #define WPI_MEM_BYPASS1 0x2e2c
83: #define WPI_MEM_BYPASS2 0x2e30
84: #define WPI_MEM_CLOCK1 0x3004
85: #define WPI_MEM_CLOCK2 0x3008
86: #define WPI_MEM_POWER 0x300c
87: #define WPI_MEM_PCIDEV 0x3010
88: #define WPI_MEM_UCODE_CTL 0x3400
89: #define WPI_MEM_UCODE_SRC 0x3404
90: #define WPI_MEM_UCODE_DST 0x3408
91: #define WPI_MEM_UCODE_SIZE 0x340c
92: #define WPI_MEM_UCODE_BASE 0x3800
93:
94: #define WPI_MEM_TEXT_BASE 0x3490
95: #define WPI_MEM_TEXT_SIZE 0x3494
96: #define WPI_MEM_DATA_BASE 0x3498
97: #define WPI_MEM_DATA_SIZE 0x349c
98:
99:
100: /* possible flags for register WPI_HWCONFIG */
101: #define WPI_HW_ALM_MB (1 << 8)
102: #define WPI_HW_ALM_MM (1 << 9)
103: #define WPI_HW_SKU_MRC (1 << 10)
104: #define WPI_HW_REV_D (1 << 11)
105: #define WPI_HW_TYPE_B (1 << 12)
106:
107: /* possible flags for registers WPI_READ_MEM_ADDR/WPI_WRITE_MEM_ADDR */
108: #define WPI_MEM_4 ((sizeof (uint32_t) - 1) << 24)
109:
110: /* possible values for WPI_MEM_UCODE_DST */
111: #define WPI_FW_TEXT 0x00000000
112:
113: /* possible flags for WPI_GPIO_STATUS */
114: #define WPI_POWERED (1 << 9)
115:
116: /* possible flags for register WPI_RESET */
117: #define WPI_NEVO_RESET (1 << 0)
118: #define WPI_SW_RESET (1 << 7)
119: #define WPI_MASTER_DISABLED (1 << 8)
120: #define WPI_STOP_MASTER (1 << 9)
121:
122: /* possible flags for register WPI_GPIO_CTL */
123: #define WPI_GPIO_CLOCK (1 << 0)
124: #define WPI_GPIO_INIT (1 << 2)
125: #define WPI_GPIO_MAC (1 << 3)
126: #define WPI_GPIO_SLEEP (1 << 4)
127: #define WPI_GPIO_PWR_STATUS 0x07000000
128: #define WPI_GPIO_PWR_SLEEP (4 << 24)
129:
130: /* possible flags for register WPI_CHICKEN */
131: #define WPI_CHICKEN_RXNOLOS (1 << 23)
132:
133: /* possible flags for register WPI_PLL_CTL */
134: #define WPI_PLL_INIT (1 << 24)
135:
136: /* possible flags for register WPI_UCODE_CLR */
137: #define WPI_RADIO_OFF (1 << 1)
138: #define WPI_DISABLE_CMD (1 << 2)
139:
140: /* possible flags for WPI_RX_STATUS */
141: #define WPI_RX_IDLE (1 << 24)
142:
143: /* possible flags for register WPI_UC_CTL */
144: #define WPI_UC_ENABLE (1 << 30)
145: #define WPI_UC_RUN (1 << 31)
146:
147: /* possible flags for register WPI_INTR_CSR */
148: #define WPI_ALIVE_INTR (1 << 0)
149: #define WPI_WAKEUP_INTR (1 << 1)
150: #define WPI_SW_ERROR (1 << 25)
151: #define WPI_TX_INTR (1 << 27)
152: #define WPI_HW_ERROR (1 << 29)
153: #define WPI_RX_INTR (1 << 31)
154:
155: #define WPI_INTR_MASK \
156: (WPI_SW_ERROR | WPI_HW_ERROR | WPI_TX_INTR | WPI_RX_INTR | \
157: WPI_ALIVE_INTR | WPI_WAKEUP_INTR)
158:
159: /* possible flags for register WPI_TX_STATUS */
160: #define WPI_TX_IDLE(qid) (1 << ((qid) + 24) | 1 << ((qid) + 16))
161:
162: /* possible flags for register WPI_EEPROM_CTL */
163: #define WPI_EEPROM_READY (1 << 0)
164:
165: /* possible flags for register WPI_EEPROM_STATUS */
166: #define WPI_EEPROM_VERSION 0x00000007
167: #define WPI_EEPROM_LOCKED 0x00000180
168:
169:
170: struct wpi_shared {
171: uint32_t txbase[8];
172: uint32_t next;
173: uint32_t reserved[2];
174: } __packed;
175:
176: #define WPI_MAX_SEG_LEN 65520
177: struct wpi_tx_desc {
178: uint32_t flags;
179: #define WPI_PAD32(x) ((((x) + 3) & ~3) - (x))
180:
181: struct {
182: uint32_t addr;
183: uint32_t len;
184: } __packed segs[WPI_MAX_SCATTER];
185: uint8_t reserved[28];
186: } __packed;
187:
188: struct wpi_tx_stat {
189: uint8_t nrts;
190: uint8_t ntries;
191: uint8_t nkill;
192: uint8_t rate;
193: uint32_t duration;
194: uint32_t status;
195: } __packed;
196:
197: struct wpi_rx_desc {
198: uint32_t len;
199: uint8_t type;
200: #define WPI_UC_READY 1
201: #define WPI_ADD_NODE_DONE 24
202: #define WPI_RX_DONE 27
203: #define WPI_TX_DONE 28
204: #define WPI_START_SCAN 130
205: #define WPI_STOP_SCAN 132
206: #define WPI_STATE_CHANGED 161
207:
208: uint8_t flags;
209: uint8_t idx;
210: uint8_t qid;
211: } __packed;
212:
213: struct wpi_rx_stat {
214: uint8_t len;
215: #define WPI_STAT_MAXLEN 20
216:
217: uint8_t id;
218: uint8_t rssi; /* received signal strength */
219: #define WPI_RSSI_OFFSET 95
220:
221: uint8_t agc; /* access gain control */
222: uint16_t signal;
223: uint16_t noise;
224: } __packed;
225:
226: struct wpi_rx_head {
227: uint16_t chan;
228: uint16_t flags;
229: uint8_t reserved;
230: uint8_t rate;
231: uint16_t len;
232: } __packed;
233:
234: struct wpi_rx_tail {
235: uint32_t flags;
236: #define WPI_RX_NO_CRC_ERR (1 << 0)
237: #define WPI_RX_NO_OVFL_ERR (1 << 1)
238: /* shortcut for the above */
239: #define WPI_RX_NOERROR (WPI_RX_NO_CRC_ERR | WPI_RX_NO_OVFL_ERR)
240:
241: uint64_t tstamp;
242: uint32_t tbeacon;
243: } __packed;
244:
245: struct wpi_tx_cmd {
246: uint8_t code;
247: #define WPI_CMD_CONFIGURE 16
248: #define WPI_CMD_ASSOCIATE 17
249: #define WPI_CMD_TSF 20
250: #define WPI_CMD_ADD_NODE 24
251: #define WPI_CMD_TX_DATA 28
252: #define WPI_CMD_MRR_SETUP 71
253: #define WPI_CMD_SET_LED 72
254: #define WPI_CMD_SET_POWER_MODE 119
255: #define WPI_CMD_SCAN 128
256: #define WPI_CMD_SET_BEACON 145
257: #define WPI_CMD_TXPOWER 151
258: #define WPI_CMD_BLUETOOTH 155
259:
260: uint8_t flags;
261: uint8_t idx;
262: uint8_t qid;
263: uint8_t data[124];
264: } __packed;
265:
266: /* structure for WPI_CMD_CONFIGURE */
267: struct wpi_config {
268: uint8_t myaddr[IEEE80211_ADDR_LEN];
269: uint16_t reserved1;
270: uint8_t bssid[IEEE80211_ADDR_LEN];
271: uint16_t reserved2;
272: uint32_t reserved3[2];
273: uint8_t mode;
274: #define WPI_MODE_HOSTAP 1
275: #define WPI_MODE_STA 3
276: #define WPI_MODE_IBSS 4
277: #define WPI_MODE_MONITOR 6
278:
279: uint8_t reserved4[3];
280: uint8_t ofdm_mask;
281: uint8_t cck_mask;
282: uint16_t associd;
283: uint32_t flags;
284: #define WPI_CONFIG_24GHZ (1 << 0)
285: #define WPI_CONFIG_CCK (1 << 1)
286: #define WPI_CONFIG_AUTO (1 << 2)
287: #define WPI_CONFIG_SHSLOT (1 << 4)
288: #define WPI_CONFIG_SHPREAMBLE (1 << 5)
289: #define WPI_CONFIG_NODIVERSITY (1 << 7)
290: #define WPI_CONFIG_ANTENNA_A (1 << 8)
291: #define WPI_CONFIG_ANTENNA_B (1 << 9)
292: #define WPI_CONFIG_TSF (1 << 15)
293:
294: uint32_t filter;
295: #define WPI_FILTER_PROMISC (1 << 0)
296: #define WPI_FILTER_CTL (1 << 1)
297: #define WPI_FILTER_MULTICAST (1 << 2)
298: #define WPI_FILTER_NODECRYPT (1 << 3)
299: #define WPI_FILTER_BSS (1 << 5)
300:
301: uint8_t chan;
302: uint8_t reserved6[3];
303: } __packed;
304:
305: /* structure for command WPI_CMD_ASSOCIATE */
306: struct wpi_assoc {
307: uint32_t flags;
308: uint32_t filter;
309: uint8_t ofdm_mask;
310: uint8_t cck_mask;
311: uint16_t reserved;
312: } __packed;
313:
314: /* structure for command WPI_CMD_TSF */
315: struct wpi_cmd_tsf {
316: uint64_t tstamp;
317: uint16_t bintval;
318: uint16_t atim;
319: uint32_t binitval;
320: uint16_t lintval;
321: uint16_t reserved;
322: } __packed;
323:
324: /* structure for WPI_CMD_ADD_NODE */
325: struct wpi_node_info {
326: uint8_t control;
327: #define WPI_NODE_UPDATE (1 << 0)
328:
329: uint8_t reserved1[3];
330: uint8_t bssid[IEEE80211_ADDR_LEN];
331: uint16_t reserved2;
332: uint8_t id;
333: #define WPI_ID_BSS 0
334: #define WPI_ID_BROADCAST 24
335:
336: uint8_t flags;
337: #define WPI_FLAG_SET_KEY (1 << 0)
338:
339: uint16_t reserved3;
340: uint16_t security;
341: uint8_t tkip;
342: uint8_t reserved4;
343: uint16_t ttak[5];
344: uint16_t reserved5;
345: uint8_t key[IEEE80211_KEYBUF_SIZE];
346: uint32_t action;
347: #define WPI_ACTION_SET_RATE (1 << 2)
348:
349: uint32_t mask;
350: uint16_t tid;
351: uint8_t rate;
352: uint8_t antenna;
353: #define WPI_ANTENNA_A (1 << 6)
354: #define WPI_ANTENNA_B (1 << 7)
355: #define WPI_ANTENNA_BOTH (WPI_ANTENNA_A | WPI_ANTENNA_B)
356:
357: uint8_t add_imm;
358: uint8_t del_imm;
359: uint16_t add_imm_start;
360: } __packed;
361:
362: /* structure for command WPI_CMD_TX_DATA */
363: struct wpi_cmd_data {
364: uint16_t len;
365: uint16_t lnext;
366: uint32_t flags;
367: #define WPI_TX_NEED_RTS (1 << 1)
368: #define WPI_TX_NEED_CTS (1 << 2)
369: #define WPI_TX_NEED_ACK (1 << 3)
370: #define WPI_TX_FULL_TXOP (1 << 7)
371: #define WPI_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */
372: #define WPI_TX_AUTO_SEQ (1 << 13)
373: #define WPI_TX_INSERT_TSTAMP (1 << 16)
374:
375: uint8_t rate;
376: uint8_t id;
377: uint8_t tid;
378: uint8_t security;
379: #define WPI_CIPHER_WEP40 1
380: #define WPI_CIPHER_CCMP 2
381: #define WPI_CIPHER_TKIP 3
382: #define WPI_CIPHER_WEP104 9
383:
384: uint8_t key[IEEE80211_KEYBUF_SIZE];
385: uint8_t tkip[IEEE80211_WEP_MICLEN];
386: uint32_t fnext;
387: uint32_t lifetime;
388: #define WPI_LIFETIME_INFINITE 0xffffffff
389:
390: uint8_t ofdm_mask;
391: uint8_t cck_mask;
392: uint8_t rts_ntries;
393: uint8_t data_ntries;
394: uint16_t timeout;
395: uint16_t txop;
396: struct ieee80211_frame wh;
397: } __packed;
398:
399: /* structure for command WPI_CMD_SET_BEACON */
400: struct wpi_cmd_beacon {
401: uint16_t len;
402: uint16_t reserved1;
403: uint32_t flags; /* same as wpi_cmd_data */
404: uint8_t rate;
405: uint8_t id;
406: uint8_t reserved2[30];
407: uint32_t lifetime;
408: uint8_t ofdm_mask;
409: uint8_t cck_mask;
410: uint16_t reserved3[3];
411: uint16_t tim;
412: uint8_t timsz;
413: uint8_t reserved4;
414: struct ieee80211_frame wh;
415: } __packed;
416:
417: /* structure for WPI_CMD_MRR_SETUP */
418: struct wpi_mrr_setup {
419: uint32_t which;
420: #define WPI_MRR_CTL 0
421: #define WPI_MRR_DATA 1
422:
423: struct {
424: uint8_t plcp;
425: uint8_t flags;
426: uint8_t ntries;
427: uint8_t next;
428: #define WPI_OFDM6 0
429: #define WPI_OFDM54 7
430: #define WPI_CCK1 8
431: #define WPI_CCK2 9
432: #define WPI_CCK11 11
433:
434: } __packed rates[WPI_CCK11 + 1];
435: } __packed;
436:
437: /* structure for WPI_CMD_SET_LED */
438: struct wpi_cmd_led {
439: uint32_t unit; /* multiplier (in usecs) */
440: uint8_t which;
441: #define WPI_LED_ACTIVITY 1
442: #define WPI_LED_LINK 2
443:
444: uint8_t off;
445: uint8_t on;
446: uint8_t reserved;
447: } __packed;
448:
449: /* structure for WPI_CMD_SET_POWER_MODE */
450: struct wpi_power {
451: uint32_t flags;
452: #define WPI_POWER_CAM 0 /* constantly awake mode */
453:
454: uint32_t rx_timeout;
455: uint32_t tx_timeout;
456: uint32_t sleep[5];
457: } __packed;
458:
459: /* structures for command WPI_CMD_SCAN */
460: struct wpi_scan_essid {
461: uint8_t id;
462: uint8_t len;
463: uint8_t data[IEEE80211_NWID_LEN];
464: } __packed;
465:
466: struct wpi_scan_hdr {
467: uint16_t len;
468: uint8_t reserved1;
469: uint8_t nchan;
470: uint16_t quiet;
471: uint16_t plcp_threshold;
472: uint16_t crc_threshold;
473: uint16_t reserved2;
474: uint32_t max_svc; /* background scans */
475: uint32_t pause_svc; /* background scans */
476: uint32_t flags;
477: uint32_t filter;
478:
479: /* wpi_cmd_data structure */
480: uint16_t paylen;
481: uint16_t lnext;
482: uint32_t txflags;
483: uint8_t rate;
484: uint8_t id;
485: uint8_t tid;
486: uint8_t security;
487: uint8_t key[IEEE80211_KEYBUF_SIZE];
488: uint8_t tkip[IEEE80211_WEP_MICLEN];
489: uint32_t fnext;
490: uint32_t lifetime;
491: uint8_t ofdm_mask;
492: uint8_t cck_mask;
493: uint8_t rts_ntries;
494: uint8_t data_ntries;
495: uint16_t timeout;
496: uint16_t txop;
497:
498: struct wpi_scan_essid essid[4];
499:
500: /* followed by probe request body */
501: /* followed by nchan x wpi_scan_chan */
502: } __packed;
503:
504: struct wpi_scan_chan {
505: uint8_t flags;
506: #define WPI_CHAN_ACTIVE (1 << 0)
507: #define WPI_CHAN_DIRECT (1 << 1)
508:
509: uint8_t chan;
510: uint8_t rf_gain;
511: uint8_t dsp_gain;
512: uint16_t active; /* msecs */
513: uint16_t passive; /* msecs */
514: } __packed;
515:
516: /* structure for WPI_CMD_TXPOWER */
517: struct wpi_cmd_txpower {
518: uint8_t band;
519: #define WPI_BAND_5GHZ 0
520: #define WPI_BAND_2GHZ 1
521:
522: uint8_t reserved;
523: uint16_t chan;
524: struct {
525: uint8_t plcp;
526: uint8_t rf_gain;
527: uint8_t dsp_gain;
528: uint8_t reserved;
529: } __packed rates[WPI_CCK11 + 1];
530: } __packed;
531:
532: /* structure for WPI_CMD_BLUETOOTH */
533: struct wpi_bluetooth {
534: uint8_t flags;
535: uint8_t lead;
536: uint8_t kill;
537: uint8_t reserved;
538: uint32_t ack;
539: uint32_t cts;
540: } __packed;
541:
542:
543: /* structure for WPI_UC_READY notification */
544: struct wpi_ucode_info {
545: uint32_t version;
546: uint8_t revision[8];
547: uint8_t type;
548: uint8_t subtype;
549: uint16_t reserved;
550: uint32_t logptr;
551: uint32_t errorptr;
552: uint32_t timestamp;
553: uint32_t valid;
554: } __packed;
555:
556: /* structure for WPI_START_SCAN notification */
557: struct wpi_start_scan {
558: uint64_t tstamp;
559: uint32_t tbeacon;
560: uint8_t chan;
561: uint8_t band;
562: uint16_t reserved;
563: uint32_t status;
564: } __packed;
565:
566: /* structure for WPI_STOP_SCAN notification */
567: struct wpi_stop_scan {
568: uint8_t nchan;
569: uint8_t status;
570: uint8_t reserved;
571: uint8_t chan;
572: uint64_t tsf;
573: } __packed;
574:
575:
576: /* firmware image header */
577: struct wpi_firmware_hdr {
578: uint32_t version;
579: uint32_t main_textsz;
580: uint32_t main_datasz;
581: uint32_t init_textsz;
582: uint32_t init_datasz;
583: uint32_t boot_textsz;
584: } __packed;
585:
586: #define WPI_FW_MAIN_TEXT_MAXSZ (80 * 1024)
587: #define WPI_FW_MAIN_DATA_MAXSZ (32 * 1024)
588: #define WPI_FW_INIT_TEXT_MAXSZ (80 * 1024)
589: #define WPI_FW_INIT_DATA_MAXSZ (32 * 1024)
590: #define WPI_FW_BOOT_TEXT_MAXSZ (80 * 1024)
591:
592: #define WPI_FW_UPDATED (1 << 31)
593:
594: /*
595: * Offsets into EEPROM.
596: */
597: #define WPI_EEPROM_MAC 0x015
598: #define WPI_EEPROM_REVISION 0x035
599: #define WPI_EEPROM_CAPABILITIES 0x045
600: #define WPI_EEPROM_TYPE 0x04a
601: #define WPI_EEPROM_DOMAIN 0x060
602: #define WPI_EEPROM_BAND1 0x063
603: #define WPI_EEPROM_BAND2 0x072
604: #define WPI_EEPROM_BAND3 0x080
605: #define WPI_EEPROM_BAND4 0x08d
606: #define WPI_EEPROM_BAND5 0x099
607: #define WPI_EEPROM_POWER_GRP 0x100
608:
609: struct wpi_eeprom_chan {
610: uint8_t flags;
611: #define WPI_EEPROM_CHAN_VALID (1 << 0)
612: #define WPI_EEPROM_CHAN_IBSS (1 << 1)
613: #define WPI_EEPROM_CHAN_ACTIVE (1 << 3)
614: #define WPI_EEPROM_CHAN_RADAR (1 << 4)
615:
616: int8_t maxpwr;
617: } __packed;
618:
619: struct wpi_eeprom_sample {
620: uint8_t index;
621: int8_t power;
622: uint16_t volt;
623: } __packed;
624:
625: #define WPI_POWER_GROUPS_COUNT 5
626: struct wpi_eeprom_group {
627: struct wpi_eeprom_sample samples[5];
628: int32_t coef[5];
629: int32_t corr[5];
630: int8_t maxpwr;
631: uint8_t chan;
632: int16_t temp;
633: } __packed;
634:
635: #define WPI_CHAN_BANDS_COUNT 5
636: #define WPI_MAX_CHAN_PER_BAND 14
637: static const struct wpi_chan_band {
638: uint32_t addr; /* offset in EEPROM */
639: uint8_t nchan;
640: uint8_t chan[WPI_MAX_CHAN_PER_BAND];
641: } wpi_bands[5] = {
642: { WPI_EEPROM_BAND1, 14,
643: { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } },
644: { WPI_EEPROM_BAND2, 13,
645: { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } },
646: { WPI_EEPROM_BAND3, 12,
647: { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } },
648: { WPI_EEPROM_BAND4, 11,
649: { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } },
650: { WPI_EEPROM_BAND5, 6,
651: { 145, 149, 153, 157, 161, 165 } }
652: };
653:
654: /* convert rate index (device view) into rate in 500Kbps unit */
655: static const uint8_t wpi_ridx_to_rate[] = {
656: 12, 18, 24, 36, 48, 72, 96, 108, /* OFDM */
657: 2, 4, 11, 22 /* CCK */
658: };
659:
660: /* convert rate index (device view) into PLCP code */
661: static const uint8_t wpi_ridx_to_plcp[] = {
662: 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, /* OFDM R1-R4 */
663: 10, 20, 55, 110 /* CCK */
664: };
665:
666: #define WPI_MAX_PWR_INDEX 77
667: /*
668: * RF Tx gain values from highest to lowest power (values obtained from
669: * the reference driver.)
670: */
671: static const uint8_t wpi_rf_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = {
672: 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xbb, 0xbb, 0xbb,
673: 0xbb, 0xf3, 0xf3, 0xf3, 0xf3, 0xf3, 0xd3, 0xd3, 0xb3, 0xb3, 0xb3,
674: 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x73, 0xeb, 0xeb, 0xeb,
675: 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xab, 0xab, 0xab, 0x8b,
676: 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xc3, 0xc3, 0xc3, 0xc3, 0xa3,
677: 0xa3, 0xa3, 0xa3, 0x83, 0x83, 0x83, 0x83, 0x63, 0x63, 0x63, 0x63,
678: 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 0x03, 0x03, 0x03,
679: 0x03
680: };
681:
682: static const uint8_t wpi_rf_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = {
683: 0xfb, 0xfb, 0xfb, 0xdb, 0xdb, 0xbb, 0xbb, 0x9b, 0x9b, 0x7b, 0x7b,
684: 0x7b, 0x7b, 0x5b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x1b, 0x1b,
685: 0x1b, 0x73, 0x73, 0x73, 0x53, 0x53, 0x53, 0x53, 0x53, 0x33, 0x33,
686: 0x33, 0x33, 0x13, 0x13, 0x13, 0x13, 0x13, 0xab, 0xab, 0xab, 0x8b,
687: 0x8b, 0x8b, 0x8b, 0x6b, 0x6b, 0x6b, 0x6b, 0x4b, 0x4b, 0x4b, 0x4b,
688: 0x2b, 0x2b, 0x2b, 0x2b, 0x0b, 0x0b, 0x0b, 0x0b, 0x83, 0x83, 0x63,
689: 0x63, 0x63, 0x63, 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23,
690: 0x03
691: };
692:
693: /*
694: * DSP pre-DAC gain values from highest to lowest power (values obtained
695: * from the reference driver.)
696: */
697: static const uint8_t wpi_dsp_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = {
698: 0x7f, 0x7f, 0x7f, 0x7f, 0x7d, 0x6e, 0x69, 0x62, 0x7d, 0x73, 0x6c,
699: 0x63, 0x77, 0x6f, 0x69, 0x61, 0x5c, 0x6a, 0x64, 0x78, 0x71, 0x6b,
700: 0x7d, 0x77, 0x70, 0x6a, 0x65, 0x61, 0x5b, 0x6b, 0x79, 0x73, 0x6d,
701: 0x7f, 0x79, 0x73, 0x6c, 0x66, 0x60, 0x5c, 0x6e, 0x68, 0x62, 0x74,
702: 0x7d, 0x77, 0x71, 0x6b, 0x65, 0x60, 0x71, 0x6a, 0x66, 0x5f, 0x71,
703: 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f,
704: 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66,
705: 0x5f
706: };
707:
708: static const uint8_t wpi_dsp_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = {
709: 0x7f, 0x78, 0x72, 0x77, 0x65, 0x71, 0x66, 0x72, 0x67, 0x75, 0x6b,
710: 0x63, 0x5c, 0x6c, 0x7d, 0x76, 0x6d, 0x66, 0x60, 0x5a, 0x68, 0x62,
711: 0x5c, 0x76, 0x6f, 0x68, 0x7e, 0x79, 0x71, 0x69, 0x63, 0x76, 0x6f,
712: 0x68, 0x62, 0x74, 0x6d, 0x66, 0x62, 0x5d, 0x71, 0x6b, 0x63, 0x78,
713: 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63,
714: 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x6b, 0x63, 0x78,
715: 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63,
716: 0x78
717: };
718:
719: #define WPI_READ(sc, reg) \
720: bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
721:
722: #define WPI_WRITE(sc, reg, val) \
723: bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
724:
725: #define WPI_WRITE_REGION_4(sc, offset, datap, count) \
726: bus_space_write_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \
727: (datap), (count))
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