Annotation of sys/dev/pci/if_sisreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: if_sisreg.h,v 1.27 2007/05/28 17:51:26 ckuethe Exp $ */
2: /*
3: * Copyright (c) 1997, 1998, 1999
4: * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
5: *
6: * Redistribution and use in source and binary forms, with or without
7: * modification, are permitted provided that the following conditions
8: * are met:
9: * 1. Redistributions of source code must retain the above copyright
10: * notice, this list of conditions and the following disclaimer.
11: * 2. Redistributions in binary form must reproduce the above copyright
12: * notice, this list of conditions and the following disclaimer in the
13: * documentation and/or other materials provided with the distribution.
14: * 3. All advertising materials mentioning features or use of this software
15: * must display the following acknowledgement:
16: * This product includes software developed by Bill Paul.
17: * 4. Neither the name of the author nor the names of any co-contributors
18: * may be used to endorse or promote products derived from this software
19: * without specific prior written permission.
20: *
21: * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24: * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31: * THE POSSIBILITY OF SUCH DAMAGE.
32: *
33: * $FreeBSD: src/sys/pci/if_sisreg.h,v 1.3 2000/08/22 23:26:51 wpaul Exp $
34: */
35:
36: /*
37: * Register definitions for the SiS 900 and SiS 7016 chipsets. The
38: * 7016 is actually an older chip and some of its registers differ
39: * from the 900, however the core operational registers are the same:
40: * the differences lie in the OnNow/Wake on LAN stuff which we don't
41: * use anyway. The 7016 needs an external MII compliant PHY while the
42: * SiS 900 has one built in. All registers are 32-bits wide.
43: */
44:
45: /* Registers common to SiS 900 and SiS 7016 */
46: #define SIS_CSR 0x00
47: #define SIS_CFG 0x04
48: #define SIS_EECTL 0x08
49: #define SIS_PCICTL 0x0C
50: #define SIS_ISR 0x10
51: #define SIS_IMR 0x14
52: #define SIS_IER 0x18
53: #define SIS_PHYCTL 0x1C
54: #define SIS_TX_LISTPTR 0x20
55: #define SIS_TX_CFG 0x24
56: #define SIS_RX_LISTPTR 0x30
57: #define SIS_RX_CFG 0x34
58: #define SIS_FLOWCTL 0x38
59: #define SIS_RXFILT_CTL 0x48
60: #define SIS_RXFILT_DATA 0x4C
61: #define SIS_PWRMAN_CTL 0xB0
62: #define SIS_PWERMAN_WKUP_EVENT 0xB4
63: #define SIS_WKUP_FRAME_CRC 0xBC
64: #define SIS_WKUP_FRAME_MASK0 0xC0
65: #define SIS_WKUP_FRAME_MASKXX 0xEC
66:
67: /* SiS 7016 specific registers */
68: #define SIS_SILICON_REV 0x5C
69: #define SIS_MIB_CTL0 0x60
70: #define SIS_MIB_CTL1 0x64
71: #define SIS_MIB_CTL2 0x68
72: #define SIS_MIB_CTL3 0x6C
73: #define SIS_MIB 0x80
74: #define SIS_LINKSTS 0xA0
75: #define SIS_TIMEUNIT 0xA4
76: #define SIS_GPIO 0xB8
77:
78: /* NS DP83815/6 registers */
79: #define NS_IHR 0x1C
80: #define NS_CLKRUN 0x3C
81: #define NS_SRR 0x58
82: #define NS_BMCR 0x80
83: #define NS_BMSR 0x84
84: #define NS_PHYIDR1 0x88
85: #define NS_PHYIDR2 0x8C
86: #define NS_ANAR 0x90
87: #define NS_ANLPAR 0x94
88: #define NS_ANER 0x98
89: #define NS_ANNPTR 0x9C
90:
91: #define NS_PHY_CR 0xE4
92: #define NS_PHY_10BTSCR 0xE8
93: #define NS_PHY_PAGE 0xCC
94: #define NS_PHY_EXTCFG 0xF0
95: #define NS_PHY_DSPCFG 0xF4
96: #define NS_PHY_SDCFG 0xF8
97: #define NS_PHY_TDATA 0xFC
98:
99: #define NS_CLKRUN_PMESTS 0x00008000
100: #define NS_CLKRUN_PMEENB 0x00000100
101: #define NS_CLNRUN_CLKRUN_ENB 0x00000001
102:
103: /* NS silicon revisions */
104: #define NS_SRR_15C 0x302
105: #define NS_SRR_15D 0x403
106: #define NS_SRR_16A 0x505
107:
108: #define SIS_CSR_TX_ENABLE 0x00000001
109: #define SIS_CSR_TX_DISABLE 0x00000002
110: #define SIS_CSR_RX_ENABLE 0x00000004
111: #define SIS_CSR_RX_DISABLE 0x00000008
112: #define SIS_CSR_TX_RESET 0x00000010
113: #define SIS_CSR_RX_RESET 0x00000020
114: #define SIS_CSR_SOFTINTR 0x00000080
115: #define SIS_CSR_RESET 0x00000100
116: #define SIS_CSR_RELOAD 0x00000400
117:
118: #define SIS_CFG_BIGENDIAN 0x00000001
119: #define SIS_CFG_PERR_DETECT 0x00000008
120: #define SIS_CFG_DEFER_DISABLE 0x00000010
121: #define SIS_CFG_OUTOFWIN_TIMER 0x00000020
122: #define SIS_CFG_SINGLE_BACKOFF 0x00000040
123: #define SIS_CFG_PCIREQ_ALG 0x00000080
124: #define SIS_CFG_FAIR_BACKOFF 0x00000200 /* 635 & 900B Specific */
125: #define SIS_CFG_RND_CNT 0x00000400 /* 635 & 900B Specific */
126: #define SIS_CFG_EDB_MASTER_EN 0x00002000
127:
128: #define SIS_EECTL_DIN 0x00000001
129: #define SIS_EECTL_DOUT 0x00000002
130: #define SIS_EECTL_CLK 0x00000004
131: #define SIS_EECTL_CSEL 0x00000008
132:
133: #define SIS96x_EECTL_GNT 0x00000100
134: #define SIS96x_EECTL_DONE 0x00000200
135: #define SIS96x_EECTL_REQ 0x00000400
136:
137: #define SIS_MII_CLK 0x00000040
138: #define SIS_MII_DIR 0x00000020
139: #define SIS_MII_DATA 0x00000010
140:
141: #define SIS_EECMD_WRITE 0x140
142: #define SIS_EECMD_READ 0x180
143: #define SIS_EECMD_ERASE 0x1c0
144:
145: #define SIS_EE_NODEADDR 0x8
146: #define NS_EE_NODEADDR 0x6
147:
148: #define SIS_PCICTL_SRAMADDR 0x0000001F
149: #define SIS_PCICTL_RAMTSTENB 0x00000020
150: #define SIS_PCICTL_TXTSTENB 0x00000040
151: #define SIS_PCICTL_RXTSTENB 0x00000080
152: #define SIS_PCICTL_BMTSTENB 0x00000200
153: #define SIS_PCICTL_RAMADDR 0x001F0000
154: #define SIS_PCICTL_ROMTIME 0x0F000000
155: #define SIS_PCICTL_DISCTEST 0x40000000
156:
157: #define SIS_ISR_RX_OK 0x00000001
158: #define SIS_ISR_RX_DESC_OK 0x00000002
159: #define SIS_ISR_RX_ERR 0x00000004
160: #define SIS_ISR_RX_EARLY 0x00000008
161: #define SIS_ISR_RX_IDLE 0x00000010
162: #define SIS_ISR_RX_OFLOW 0x00000020
163: #define SIS_ISR_TX_OK 0x00000040
164: #define SIS_ISR_TX_DESC_OK 0x00000080
165: #define SIS_ISR_TX_ERR 0x00000100
166: #define SIS_ISR_TX_IDLE 0x00000200
167: #define SIS_ISR_TX_UFLOW 0x00000400
168: #define SIS_ISR_SOFTINTR 0x00000800
169: #define SIS_ISR_HIBITS 0x00008000
170: #define SIS_ISR_RX_FIFO_OFLOW 0x00010000
171: #define SIS_ISR_TGT_ABRT 0x00100000
172: #define SIS_ISR_BM_ABRT 0x00200000
173: #define SIS_ISR_SYSERR 0x00400000
174: #define SIS_ISR_PARITY_ERR 0x00800000
175: #define SIS_ISR_RX_RESET_DONE 0x01000000
176: #define SIS_ISR_TX_RESET_DONE 0x02000000
177: #define SIS_ISR_TX_PAUSE_START 0x04000000
178: #define SIS_ISR_TX_PAUSE_DONE 0x08000000
179: #define SIS_ISR_WAKE_EVENT 0x10000000
180:
181: #define SIS_IMR_RX_OK 0x00000001
182: #define SIS_IMR_RX_DESC_OK 0x00000002
183: #define SIS_IMR_RX_ERR 0x00000004
184: #define SIS_IMR_RX_EARLY 0x00000008
185: #define SIS_IMR_RX_IDLE 0x00000010
186: #define SIS_IMR_RX_OFLOW 0x00000020
187: #define SIS_IMR_TX_OK 0x00000040
188: #define SIS_IMR_TX_DESC_OK 0x00000080
189: #define SIS_IMR_TX_ERR 0x00000100
190: #define SIS_IMR_TX_IDLE 0x00000200
191: #define SIS_IMR_TX_UFLOW 0x00000400
192: #define SIS_IMR_SOFTINTR 0x00000800
193: #define SIS_IMR_HIBITS 0x00008000
194: #define SIS_IMR_RX_FIFO_OFLOW 0x00010000
195: #define SIS_IMR_TGT_ABRT 0x00100000
196: #define SIS_IMR_BM_ABRT 0x00200000
197: #define SIS_IMR_SYSERR 0x00400000
198: #define SIS_IMR_PARITY_ERR 0x00800000
199: #define SIS_IMR_RX_RESET_DONE 0x01000000
200: #define SIS_IMR_TX_RESET_DONE 0x02000000
201: #define SIS_IMR_TX_PAUSE_START 0x04000000
202: #define SIS_IMR_TX_PAUSE_DONE 0x08000000
203: #define SIS_IMR_WAKE_EVENT 0x10000000
204:
205: #define SIS_INTRS \
206: (SIS_IMR_RX_OFLOW|SIS_IMR_TX_UFLOW|SIS_IMR_TX_OK|\
207: SIS_IMR_TX_IDLE|SIS_IMR_RX_OK|SIS_IMR_RX_ERR|\
208: SIS_IMR_RX_IDLE|\
209: SIS_IMR_SYSERR)
210:
211: /* Interrupt Holdoff Register */
212: #define NS_IHR_HOLDCTL 0x00000100
213:
214: /*
215: * Interrupt holdoff value for NS DP8316. We can have the chip
216: * delay interrupt delivery for a certain period. Units are in
217: * 100us - this sets the delay to 1ms holdoff.
218: */
219: #define NS_IHR_DELAY 10
220:
221: #define NS_IHR_VALUE (NS_IHR_HOLDCTL|NS_IHR_DELAY)
222:
223: #define SIS_IER_INTRENB 0x00000001
224:
225: #define SIS_PHYCTL_ACCESS 0x00000010
226: #define SIS_PHYCTL_OP 0x00000020
227: #define SIS_PHYCTL_REGADDR 0x000007C0
228: #define SIS_PHYCTL_PHYADDR 0x0000F800
229: #define SIS_PHYCTL_PHYDATA 0xFFFF0000
230:
231: #define SIS_PHYOP_READ 0x00000020
232: #define SIS_PHYOP_WRITE 0x00000000
233:
234: #define SIS_TXCFG_DRAIN_THRESH 0x0000003F /* 32-byte units */
235: #define SIS_TXCFG_FILL_THRESH 0x00003F00 /* 32-byte units */
236: #define SIS_TXCFG_MPII03D 0x00040000 /* "Must be 1" */
237: #define SIS_TXCFG_DMABURST 0x00700000
238: #define SIS_TXCFG_AUTOPAD 0x10000000
239: #define SIS_TXCFG_LOOPBK 0x20000000
240: #define SIS_TXCFG_IGN_HBEAT 0x40000000
241: #define SIS_TXCFG_IGN_CARR 0x80000000
242:
243: #define SIS_TXCFG_DRAIN(x) (((x) >> 5) & SIS_TXCFG_DRAIN_THRESH)
244: #define SIS_TXCFG_FILL(x) ((((x) >> 5) << 8) & SIS_TXCFG_FILL_THRESH)
245:
246: #define SIS_TXDMA_512BYTES 0x00000000
247: #define SIS_TXDMA_4BYTES 0x00100000
248: #define SIS_TXDMA_8BYTES 0x00200000
249: #define SIS_TXDMA_16BYTES 0x00300000
250: #define SIS_TXDMA_32BYTES 0x00400000
251: #define SIS_TXDMA_64BYTES 0x00500000
252: #define SIS_TXDMA_128BYTES 0x00600000
253: #define SIS_TXDMA_256BYTES 0x00700000
254:
255: #define SIS_TXCFG_100 \
256: (SIS_TXDMA_64BYTES|SIS_TXCFG_AUTOPAD|\
257: SIS_TXCFG_FILL(ETHER_MIN_LEN)|SIS_TXCFG_DRAIN(ETHER_MAX_DIX_LEN))
258:
259: #define SIS_TXCFG_10 \
260: (SIS_TXDMA_32BYTES|SIS_TXCFG_AUTOPAD|\
261: SIS_TXCFG_FILL(ETHER_MIN_LEN)|SIS_TXCFG_DRAIN(ETHER_MAX_DIX_LEN))
262:
263: #define SIS_RXCFG_DRAIN_THRESH 0x0000003E /* 8-byte units */
264: #define SIS_RXCFG_DMABURST 0x00700000
265: #define SIS_RXCFG_RX_JABBER 0x08000000
266: #define SIS_RXCFG_RX_TXPKTS 0x10000000
267: #define SIS_RXCFG_RX_RUNTS 0x40000000
268: #define SIS_RXCFG_RX_GIANTS 0x80000000
269:
270: #define SIS_RXCFG_DRAIN(x) ((((x) >> 3) << 1) & SIS_RXCFG_DRAIN_THRESH)
271:
272: #define SIS_RXDMA_512BYTES 0x00000000
273: #define SIS_RXDMA_4BYTES 0x00100000
274: #define SIS_RXDMA_8BYTES 0x00200000
275: #define SIS_RXDMA_16BYTES 0x00300000
276: #define SIS_RXDMA_32BYTES 0x00400000
277: #define SIS_RXDMA_64BYTES 0x00500000
278: #define SIS_RXDMA_128BYTES 0x00600000
279: #define SIS_RXDMA_256BYTES 0x00700000
280:
281: #define SIS_RXCFG256 \
282: (SIS_RXCFG_DRAIN(64)|SIS_RXDMA_256BYTES)
283: #define SIS_RXCFG64 \
284: (SIS_RXCFG_DRAIN(64)|SIS_RXDMA_64BYTES)
285:
286: #define SIS_RXFILTCTL_ADDR 0x000F0000
287: #define NS_RXFILTCTL_MCHASH 0x00200000
288: #define NS_RXFILTCTL_ARP 0x00400000
289: #define NS_RXFILTCTL_PERFECT 0x08000000
290: #define SIS_RXFILTCTL_ALLPHYS 0x10000000
291: #define SIS_RXFILTCTL_ALLMULTI 0x20000000
292: #define SIS_RXFILTCTL_BROAD 0x40000000
293: #define SIS_RXFILTCTL_ENABLE 0x80000000
294:
295: #define SIS_FILTADDR_PAR0 0x00000000
296: #define SIS_FILTADDR_PAR1 0x00010000
297: #define SIS_FILTADDR_PAR2 0x00020000
298: #define SIS_FILTADDR_MAR0 0x00040000
299: #define SIS_FILTADDR_MAR1 0x00050000
300: #define SIS_FILTADDR_MAR2 0x00060000
301: #define SIS_FILTADDR_MAR3 0x00070000
302: #define SIS_FILTADDR_MAR4 0x00080000
303: #define SIS_FILTADDR_MAR5 0x00090000
304: #define SIS_FILTADDR_MAR6 0x000A0000
305: #define SIS_FILTADDR_MAR7 0x000B0000
306:
307: #define NS_FILTADDR_PAR0 0x00000000
308: #define NS_FILTADDR_PAR1 0x00000002
309: #define NS_FILTADDR_PAR2 0x00000004
310:
311: #define NS_FILTADDR_FMEM_LO 0x00000200
312: #define NS_FILTADDR_FMEM_HI 0x000003FE
313:
314: /*
315: * DMA descriptor structures. The first part of the descriptor
316: * is the hardware descriptor format, which is just three longwords.
317: * After this, we include some additional structure members for
318: * use by the driver. Note that for this structure will be a different
319: * size on the alpha, but that's okay as long as it's a multiple of 4
320: * bytes in size.
321: */
322: struct sis_desc {
323: /* SiS hardware descriptor section */
324: u_int32_t sis_next;
325: u_int32_t sis_cmdsts;
326: #define sis_rxstat sis_cmdsts
327: #define sis_txstat sis_cmdsts
328: #define sis_ctl sis_cmdsts
329: u_int32_t sis_ptr;
330: /* Driver software section */
331: struct mbuf *sis_mbuf;
332: struct sis_desc *sis_nextdesc;
333: bus_dmamap_t map;
334: };
335:
336: #define SIS_CMDSTS_BUFLEN 0x00000FFF
337: #define SIS_CMDSTS_PKT_OK 0x08000000
338: #define SIS_CMDSTS_CRC 0x10000000
339: #define SIS_CMDSTS_INTR 0x20000000
340: #define SIS_CMDSTS_MORE 0x40000000
341: #define SIS_CMDSTS_OWN 0x80000000
342:
343: #define SIS_LASTDESC(x) (!((x)->sis_ctl & SIS_CMDSTS_MORE)))
344: #define SIS_OWNDESC(x) ((x)->sis_ctl & SIS_CMDSTS_OWN)
345: #define SIS_INC(x, y) (x) = ((x) == ((y)-1)) ? 0 : (x)+1
346: #define SIS_RXBYTES(x) (((x)->sis_ctl & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN)
347:
348: #define SIS_RXSTAT_COLL 0x00010000
349: #define SIS_RXSTAT_LOOPBK 0x00020000
350: #define SIS_RXSTAT_ALIGNERR 0x00040000
351: #define SIS_RXSTAT_CRCERR 0x00080000
352: #define SIS_RXSTAT_SYMBOLERR 0x00100000
353: #define SIS_RXSTAT_RUNT 0x00200000
354: #define SIS_RXSTAT_GIANT 0x00400000
355: #define SIS_RXSTAT_DSTCLASS 0x01800000
356: #define SIS_RXSTAT_OVERRUN 0x02000000
357: #define SIS_RXSTAT_RX_ABORT 0x04000000
358:
359: #define SIS_DSTCLASS_REJECT 0x00000000
360: #define SIS_DSTCLASS_UNICAST 0x00800000
361: #define SIS_DSTCLASS_MULTICAST 0x01000000
362: #define SIS_DSTCLASS_BROADCAST 0x02000000
363:
364: #define SIS_TXSTAT_COLLCNT 0x000F0000
365: #define SIS_TXSTAT_EXCESSCOLLS 0x00100000
366: #define SIS_TXSTAT_OUTOFWINCOLL 0x00200000
367: #define SIS_TXSTAT_EXCESS_DEFER 0x00400000
368: #define SIS_TXSTAT_DEFERED 0x00800000
369: #define SIS_TXSTAT_CARR_LOST 0x01000000
370: #define SIS_TXSTAT_UNDERRUN 0x02000000
371: #define SIS_TXSTAT_TX_ABORT 0x04000000
372:
373: #define SIS_RX_LIST_CNT_MIN 4
374: #define SIS_RX_LIST_CNT_MAX 64
375: #define SIS_TX_LIST_CNT 128
376:
377: struct sis_list_data {
378: struct sis_desc sis_rx_list[SIS_RX_LIST_CNT_MAX];
379: struct sis_desc sis_tx_list[SIS_TX_LIST_CNT];
380: };
381:
382: struct sis_ring_data {
383: struct sis_desc *sis_rx_pdsc;
384: int sis_tx_prod;
385: int sis_tx_cons;
386: int sis_tx_cnt;
387: };
388:
389:
390: /*
391: * SiS PCI vendor ID.
392: */
393: #define SIS_VENDORID 0x1039
394:
395: /*
396: * SiS PCI device IDs
397: */
398: #define SIS_DEVICEID_900 0x0900
399: #define SIS_DEVICEID_7016 0x7016
400:
401:
402: /*
403: * SiS 900 PCI revision codes.
404: */
405: #define SIS_REV_900B 0x0003
406: #define SIS_REV_630A 0x0080
407: #define SIS_REV_630E 0x0081
408: #define SIS_REV_630S 0x0082
409: #define SIS_REV_630EA1 0x0083
410: #define SIS_REV_630ET 0x0084
411: #define SIS_REV_635 0x0090
412: #define SIS_REV_96x 0x0091
413:
414: struct sis_type {
415: u_int16_t sis_vid;
416: u_int16_t sis_did;
417: char *sis_name;
418: };
419:
420: struct sis_mii_frame {
421: u_int8_t mii_stdelim;
422: u_int8_t mii_opcode;
423: u_int8_t mii_phyaddr;
424: u_int8_t mii_regaddr;
425: u_int8_t mii_turnaround;
426: u_int16_t mii_data;
427: };
428:
429: /*
430: * MII constants
431: */
432: #define SIS_MII_STARTDELIM 0x01
433: #define SIS_MII_READOP 0x02
434: #define SIS_MII_WRITEOP 0x01
435: #define SIS_MII_TURNAROUND 0x02
436:
437: #define SIS_TYPE_900 1
438: #define SIS_TYPE_7016 2
439: #define SIS_TYPE_83815 3
440:
441: struct sis_softc {
442: struct device sc_dev; /* generic device structure */
443: void *sc_ih; /* interrupt handler cookie */
444: struct arpcom arpcom; /* interface info */
445: mii_data_t sc_mii;
446: bus_space_handle_t sis_bhandle;
447: bus_space_tag_t sis_btag;
448: u_int8_t sis_type;
449: u_int8_t sis_rev;
450: u_int8_t sis_link;
451: u_int sis_srr;
452: struct sis_list_data *sis_ldata;
453: struct sis_ring_data sis_cdata;
454: struct timeout sis_timeout;
455: bus_dma_tag_t sc_dmat;
456: bus_dmamap_t sc_listmap;
457: bus_dma_segment_t sc_listseg[1];
458: int sc_listnseg;
459: caddr_t sc_listkva;
460: bus_dmamap_t sc_rx_sparemap;
461: bus_dmamap_t sc_tx_sparemap;
462: int sis_stopped;
463: int sc_rxbufs;
464: int sc_if_flags;
465: };
466:
467: /*
468: * register space access macros
469: */
470: #define CSR_WRITE_4(sc, reg, val) \
471: bus_space_write_4(sc->sis_btag, sc->sis_bhandle, reg, val)
472:
473: #define CSR_READ_4(sc, reg) \
474: bus_space_read_4(sc->sis_btag, sc->sis_bhandle, reg)
475:
476: #define SIS_TIMEOUT 1000
477: #define SIS_MIN_FRAMELEN 60
478:
479: /*
480: * PCI low memory base and low I/O base register, and
481: * other PCI registers.
482: */
483:
484: #define SIS_PCI_VENDOR_ID 0x00
485: #define SIS_PCI_DEVICE_ID 0x02
486: #define SIS_PCI_COMMAND 0x04
487: #define SIS_PCI_STATUS 0x06
488: #define SIS_PCI_REVID 0x08
489: #define SIS_PCI_CLASSCODE 0x09
490: #define SIS_PCI_CACHELEN 0x0C
491: #define SIS_PCI_LATENCY_TIMER 0x0D
492: #define SIS_PCI_HEADER_TYPE 0x0E
493: #define SIS_PCI_LOIO 0x10
494: #define SIS_PCI_LOMEM 0x14
495: #define SIS_PCI_BIOSROM 0x30
496: #define SIS_PCI_INTLINE 0x3C
497: #define SIS_PCI_INTPIN 0x3D
498: #define SIS_PCI_MINGNT 0x3E
499: #define SIS_PCI_MINLAT 0x0F
500: #define SIS_PCI_RESETOPT 0x48
501: #define SIS_PCI_EEPROM_DATA 0x4C
502:
503: /* power management registers */
504: #define SIS_PCI_CAPID 0x50 /* 8 bits */
505: #define SIS_PCI_NEXTPTR 0x51 /* 8 bits */
506: #define SIS_PCI_PWRMGMTCAP 0x52 /* 16 bits */
507: #define SIS_PCI_PWRMGMTCTRL 0x54 /* 16 bits */
508:
509: #define SIS_PSTATE_MASK 0x0003
510: #define SIS_PSTATE_D0 0x0000
511: #define SIS_PSTATE_D1 0x0001
512: #define SIS_PSTATE_D2 0x0002
513: #define SIS_PSTATE_D3 0x0003
514: #define SIS_PME_EN 0x0010
515: #define SIS_PME_STATUS 0x8000
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