Annotation of sys/dev/pci/if_san_te1.c, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: if_san_te1.c,v 1.9 2005/07/07 20:58:50 canacar Exp $ */
2:
3: /*-
4: * Copyright (c) 2001-2004 Sangoma Technologies (SAN)
5: * All rights reserved. www.sangoma.com
6: *
7: * This code is written by Alex Feldman <al.feldman@sangoma.com> for SAN.
8: *
9: * Redistribution and use in source and binary forms, with or without
10: * modification, are permitted provided that the following conditions
11: * are met:
12: * 1. Redistributions of source code must retain the above copyright
13: * notice, this list of conditions and the following disclaimer.
14: * 2. Redistributions in binary form must reproduce the above
15: * copyright notice, this list of conditions and the following disclaimer
16: * in the documentation and/or other materials provided with the
17: * distribution.
18: * 3. Neither the name of Sangoma Technologies nor the names of its
19: * contributors may be used to endorse or promote products derived
20: * from this software without specific prior written permission.
21: *
22: * THIS SOFTWARE IS PROVIDED BY SANGOMA TECHNOLOGIES AND CONTRIBUTORS
23: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
24: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
25: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
26: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32: * THE POSSIBILITY OF SUCH DAMAGE.
33: */
34:
35: #include <sys/types.h>
36: #include <sys/param.h>
37: #include <sys/systm.h>
38: #include <sys/syslog.h>
39: #include <sys/ioccom.h>
40: #include <sys/malloc.h>
41: #include <sys/errno.h>
42: #include <sys/mbuf.h>
43: #include <sys/socket.h>
44: #include <sys/sockio.h>
45: #include <sys/kernel.h>
46: #include <sys/time.h>
47: #include <sys/timeout.h>
48:
49: #include <net/if.h>
50: #include <net/if_media.h>
51: #include <net/if_sppp.h>
52: #include <netinet/in_systm.h>
53: #include <netinet/in.h>
54: #include <netinet/in_var.h>
55: #include <netinet/udp.h>
56: #include <netinet/ip.h>
57:
58: #include <dev/pci/if_san_common.h>
59: #include <dev/pci/if_san_obsd.h>
60:
61:
62:
63: #define FIRST_SAMPLE 0
64: #define LAST_SAMPLE 23
65: #define FIRST_UI 0
66: #define LAST_UI 4
67:
68: #define MAX_BUSY_READ 0x05
69:
70: /* Enabling/Disabling register debugging */
71: #undef WAN_DEBUG_TE1_REG
72: #ifdef WAN_DEBUG_TE1_REG
73:
74: #define TEST_REG(reg,value) \
75: { \
76: unsigned char test_value = READ_REG(reg); \
77: if (test_value != value) { \
78: log(LOG_INFO, "%s:%d: Test failed!\n", \
79: __FILE__,__LINE__); \
80: log(LOG_INFO, "%s:%d: Reg=%02x, Val=%02x\n", \
81: __FILE__,__LINE__,reg, value); \
82: } \
83: }
84:
85: #define TEST_RPSC_REG(card,reg,channel,value) \
86: { \
87: unsigned char test_value = ReadRPSCReg(card,channel,reg); \
88: if (test_value != value) { \
89: log(LOG_INFO, "%s:%d: RPSC REG Test failed!\n", \
90: __FILE__,__LINE__); \
91: log(LOG_INFO, "%s:%d: Reg=%02x,Channel=%d,Val=%02x!\n", \
92: __FILE__, __LINE__, reg, channel, value); \
93: } \
94: }
95:
96: #define TEST_TPSC_REG(card,reg,channel,value) \
97: { \
98: unsigned char test_value = ReadTPSCReg(card,channel,reg); \
99: if (test_value != value) { \
100: log(LOG_INFO, "%s:%d: TPSC REG Test failed!\n", \
101: __FILE__,__LINE__); \
102: log(LOG_INFO, "%s:%d: Reg=%02x,Channel=%d,Val=%02x)!\n",\
103: __FILE__, __LINE__, reg, channel, value); \
104: } \
105: }
106:
107: #else
108:
109: #define TEST_REG(reg,value)
110: #define TEST_RPSC_REG(card,reg,channel,value)
111: #define TEST_TPSC_REG(card,reg,channel,value)
112:
113: #endif
114:
115: #define READ_RPSC_REG(reg,channel) ReadRPSCReg(card,reg,channel)
116: #define READ_TPSC_REG(reg,channel) ReadTPSCReg(card,reg,channel)
117: #define READ_SIGX_REG(reg,channel) ReadSIGXReg(card,reg,channel)
118: #define WRITE_RPSC_REG(reg,channel,value) \
119: { \
120: WriteRPSCReg(card,reg,channel,(unsigned char)value); \
121: TEST_RPSC_REG(card,reg,channel,(unsigned char)value); \
122: }
123:
124: #define WRITE_TPSC_REG(reg,channel,value) \
125: { \
126: WriteTPSCReg(card,reg,channel,(unsigned char)value); \
127: TEST_TPSC_REG(card,reg,channe,(unsigned char)value); \
128: }
129:
130: #if 0
131: #define WRITE_SIGX_REG(reg,channel,value) \
132: { \
133: WriteSIGXReg(card,reg,channel,(unsigned char)value); \
134: TEST_SIGX_REG(card,reg,channel,(unsigned char)value); \
135: }
136: #endif
137:
138: #define IS_T1_ALARM(alarm) ((alarm) & \
139: ( \
140: BIT_RED_ALARM | \
141: BIT_AIS_ALARM | \
142: BIT_YEL_ALARM \
143: ))
144:
145: #define IS_E1_ALARM(alarm) ((alarm) & \
146: ( \
147: BIT_RED_ALARM | \
148: BIT_AIS_ALARM | \
149: BIT_ALOS_ALARM \
150: ))
151:
152:
153: typedef
154: unsigned char TX_WAVEFORM[LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1];
155:
156: typedef struct RLPS_EQUALIZER_RAM_T {
157: /*unsigned char address;*/
158: unsigned char byte1;
159: unsigned char byte2;
160: unsigned char byte3;
161: unsigned char byte4;
162: } RLPS_EQUALIZER_RAM;
163:
164:
165:
166: /* Transmit Waveform Values for T1 Long Haul (LBO 0db)
167: ** unsigned char t1_tx_waveform_lh_0db
168: ** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */
169: TX_WAVEFORM t1_tx_waveform_lh_0db =
170: {
171: { 0x00, 0x44, 0x00, 0x00, 0x00 },
172: { 0x0A, 0x44, 0x00, 0x00, 0x00 },
173: { 0x20, 0x43, 0x00, 0x00, 0x00 },
174: { 0x32, 0x43, 0x00, 0x00, 0x00 },
175: { 0x3E, 0x42, 0x00, 0x00, 0x00 },
176: { 0x3D, 0x42, 0x00, 0x00, 0x00 },
177: { 0x3C, 0x41, 0x00, 0x00, 0x00 },
178: { 0x3B, 0x41, 0x00, 0x00, 0x00 },
179: { 0x3A, 0x00, 0x00, 0x00, 0x00 },
180: { 0x39, 0x00, 0x00, 0x00, 0x00 },
181: { 0x39, 0x00, 0x00, 0x00, 0x00 },
182: { 0x38, 0x00, 0x00, 0x00, 0x00 },
183: { 0x37, 0x00, 0x00, 0x00, 0x00 },
184: { 0x36, 0x00, 0x00, 0x00, 0x00 },
185: { 0x34, 0x00, 0x00, 0x00, 0x00 },
186: { 0x29, 0x00, 0x00, 0x00, 0x00 },
187: { 0x4F, 0x00, 0x00, 0x00, 0x00 },
188: { 0x4C, 0x00, 0x00, 0x00, 0x00 },
189: { 0x4A, 0x00, 0x00, 0x00, 0x00 },
190: { 0x49, 0x00, 0x00, 0x00, 0x00 },
191: { 0x47, 0x00, 0x00, 0x00, 0x00 },
192: { 0x47, 0x00, 0x00, 0x00, 0x00 },
193: { 0x46, 0x00, 0x00, 0x00, 0x00 },
194: { 0x46, 0x00, 0x00, 0x00, 0x00 }
195: };
196:
197: /* Transmit Waveform Values for T1 Long Haul (LBO 7.5 dB):
198: ** unsigned char t1_tx_waveform_lh_75db
199: ** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */
200: TX_WAVEFORM t1_tx_waveform_lh_75db =
201: {
202: { 0x00, 0x10, 0x00, 0x00, 0x00 },
203: { 0x01, 0x0E, 0x00, 0x00, 0x00 },
204: { 0x02, 0x0C, 0x00, 0x00, 0x00 },
205: { 0x04, 0x0A, 0x00, 0x00, 0x00 },
206: { 0x08, 0x08, 0x00, 0x00, 0x00 },
207: { 0x0C, 0x06, 0x00, 0x00, 0x00 },
208: { 0x10, 0x04, 0x00, 0x00, 0x00 },
209: { 0x16, 0x02, 0x00, 0x00, 0x00 },
210: { 0x1A, 0x01, 0x00, 0x00, 0x00 },
211: { 0x1E, 0x00, 0x00, 0x00, 0x00 },
212: { 0x22, 0x00, 0x00, 0x00, 0x00 },
213: { 0x26, 0x00, 0x00, 0x00, 0x00 },
214: { 0x2A, 0x00, 0x00, 0x00, 0x00 },
215: { 0x2B, 0x00, 0x00, 0x00, 0x00 },
216: { 0x2C, 0x00, 0x00, 0x00, 0x00 },
217: { 0x2D, 0x00, 0x00, 0x00, 0x00 },
218: { 0x2C, 0x00, 0x00, 0x00, 0x00 },
219: { 0x28, 0x00, 0x00, 0x00, 0x00 },
220: { 0x24, 0x00, 0x00, 0x00, 0x00 },
221: { 0x20, 0x00, 0x00, 0x00, 0x00 },
222: { 0x1C, 0x00, 0x00, 0x00, 0x00 },
223: { 0x18, 0x00, 0x00, 0x00, 0x00 },
224: { 0x14, 0x00, 0x00, 0x00, 0x00 },
225: { 0x12, 0x00, 0x00, 0x00, 0x00 }
226: };
227:
228:
229: /* Transmit Waveform Values for T1 Long Haul (LBO 15 dB)
230: ** unsigned char t1_tx_waveform_lh_15db
231: ** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */
232: TX_WAVEFORM t1_tx_waveform_lh_15db =
233: {
234: { 0x00, 0x2A, 0x09, 0x01, 0x00 },
235: { 0x00, 0x28, 0x08, 0x01, 0x00 },
236: { 0x00, 0x26, 0x08, 0x01, 0x00 },
237: { 0x00, 0x24, 0x07, 0x01, 0x00 },
238: { 0x01, 0x22, 0x07, 0x01, 0x00 },
239: { 0x02, 0x20, 0x06, 0x01, 0x00 },
240: { 0x04, 0x1E, 0x06, 0x01, 0x00 },
241: { 0x07, 0x1C, 0x05, 0x00, 0x00 },
242: { 0x0A, 0x1B, 0x05, 0x00, 0x00 },
243: { 0x0D, 0x19, 0x05, 0x00, 0x00 },
244: { 0x10, 0x18, 0x04, 0x00, 0x00 },
245: { 0x14, 0x16, 0x04, 0x00, 0x00 },
246: { 0x18, 0x15, 0x04, 0x00, 0x00 },
247: { 0x1B, 0x13, 0x03, 0x00, 0x00 },
248: { 0x1E, 0x12, 0x03, 0x00, 0x00 },
249: { 0x21, 0x10, 0x03, 0x00, 0x00 },
250: { 0x24, 0x0F, 0x03, 0x00, 0x00 },
251: { 0x27, 0x0D, 0x03, 0x00, 0x00 },
252: { 0x2A, 0x0D, 0x02, 0x00, 0x00 },
253: { 0x2D, 0x0B, 0x02, 0x00, 0x00 },
254: { 0x30, 0x0B, 0x02, 0x00, 0x00 },
255: { 0x30, 0x0A, 0x02, 0x00, 0x00 },
256: { 0x2E, 0x0A, 0x02, 0x00, 0x00 },
257: { 0x2C, 0x09, 0x02, 0x00, 0x00 }
258: };
259:
260:
261: /* Transmit Waveform Values for T1 Long Haul (LBO 22.5 dB)
262: ** unsigned char t1_tx_waveform_lh_225db
263: ** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */
264: TX_WAVEFORM t1_tx_waveform_lh_225db =
265: {
266: { 0x00, 0x1F, 0x16, 0x06, 0x01 },
267: { 0x00, 0x20, 0x15, 0x05, 0x01 },
268: { 0x00, 0x21, 0x15, 0x05, 0x01 },
269: { 0x00, 0x22, 0x14, 0x05, 0x01 },
270: { 0x00, 0x22, 0x13, 0x04, 0x00 },
271: { 0x00, 0x23, 0x12, 0x04, 0x00 },
272: { 0x01, 0x23, 0x12, 0x04, 0x00 },
273: { 0x01, 0x24, 0x11, 0x03, 0x00 },
274: { 0x01, 0x23, 0x10, 0x03, 0x00 },
275: { 0x02, 0x23, 0x10, 0x03, 0x00 },
276: { 0x03, 0x22, 0x0F, 0x03, 0x00 },
277: { 0x05, 0x22, 0x0E, 0x03, 0x00 },
278: { 0x07, 0x21, 0x0E, 0x02, 0x00 },
279: { 0x09, 0x20, 0x0D, 0x02, 0x00 },
280: { 0x0B, 0x1E, 0x0C, 0x02, 0x00 },
281: { 0x0E, 0x1D, 0x0C, 0x02, 0x00 },
282: { 0x10, 0x1B, 0x0B, 0x02, 0x00 },
283: { 0x13, 0x1B, 0x0A, 0x02, 0x00 },
284: { 0x15, 0x1A, 0x0A, 0x02, 0x00 },
285: { 0x17, 0x19, 0x09, 0x01, 0x00 },
286: { 0x19, 0x19, 0x08, 0x01, 0x00 },
287: { 0x1B, 0x18, 0x08, 0x01, 0x00 },
288: { 0x1D, 0x17, 0x07, 0x01, 0x00 },
289: { 0x1E, 0x17, 0x06, 0x01, 0x00 }
290: };
291:
292:
293: /* Transmit Waveform Values for T1 Short Haul (0 - 110 ft.)
294: ** unsigned char t1_tx_waveform_sh_110ft
295: ** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */
296: TX_WAVEFORM t1_tx_waveform_sh_110ft =
297: {
298: { 0x00, 0x45, 0x00, 0x00, 0x00 },
299: { 0x0A, 0x44, 0x00, 0x00, 0x00 },
300: { 0x20, 0x43, 0x00, 0x00, 0x00 },
301: { 0x3F, 0x43, 0x00, 0x00, 0x00 },
302: { 0x3F, 0x42, 0x00, 0x00, 0x00 },
303: { 0x3F, 0x42, 0x00, 0x00, 0x00 },
304: { 0x3C, 0x41, 0x00, 0x00, 0x00 },
305: { 0x3B, 0x41, 0x00, 0x00, 0x00 },
306: { 0x3A, 0x00, 0x00, 0x00, 0x00 },
307: { 0x39, 0x00, 0x00, 0x00, 0x00 },
308: { 0x39, 0x00, 0x00, 0x00, 0x00 },
309: { 0x38, 0x00, 0x00, 0x00, 0x00 },
310: { 0x37, 0x00, 0x00, 0x00, 0x00 },
311: { 0x36, 0x00, 0x00, 0x00, 0x00 },
312: { 0x34, 0x00, 0x00, 0x00, 0x00 },
313: { 0x29, 0x00, 0x00, 0x00, 0x00 },
314: { 0x59, 0x00, 0x00, 0x00, 0x00 },
315: { 0x55, 0x00, 0x00, 0x00, 0x00 },
316: { 0x50, 0x00, 0x00, 0x00, 0x00 },
317: { 0x4D, 0x00, 0x00, 0x00, 0x00 },
318: { 0x4A, 0x00, 0x00, 0x00, 0x00 },
319: { 0x48, 0x00, 0x00, 0x00, 0x00 },
320: { 0x46, 0x00, 0x00, 0x00, 0x00 },
321: { 0x46, 0x00, 0x00, 0x00, 0x00 }
322: };
323:
324:
325: /* Transmit Waveform Values for T1 Short Haul (110 - 220 ft.)
326: ** unsigned char t1_tx_waveform_sh_220ft
327: ** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */
328: TX_WAVEFORM t1_tx_waveform_sh_220ft =
329: {
330: { 0x00, 0x44, 0x00, 0x00, 0x00 },
331: { 0x0A, 0x44, 0x00, 0x00, 0x00 },
332: { 0x3F, 0x43, 0x00, 0x00, 0x00 },
333: { 0x3F, 0x43, 0x00, 0x00, 0x00 },
334: { 0x36, 0x42, 0x00, 0x00, 0x00 },
335: { 0x34, 0x42, 0x00, 0x00, 0x00 },
336: { 0x30, 0x41, 0x00, 0x00, 0x00 },
337: { 0x2F, 0x41, 0x00, 0x00, 0x00 },
338: { 0x2E, 0x00, 0x00, 0x00, 0x00 },
339: { 0x2D, 0x00, 0x00, 0x00, 0x00 },
340: { 0x2C, 0x00, 0x00, 0x00, 0x00 },
341: { 0x2B, 0x00, 0x00, 0x00, 0x00 },
342: { 0x2A, 0x00, 0x00, 0x00, 0x00 },
343: { 0x28, 0x00, 0x00, 0x00, 0x00 },
344: { 0x26, 0x00, 0x00, 0x00, 0x00 },
345: { 0x4A, 0x00, 0x00, 0x00, 0x00 },
346: { 0x68, 0x00, 0x00, 0x00, 0x00 },
347: { 0x54, 0x00, 0x00, 0x00, 0x00 },
348: { 0x4F, 0x00, 0x00, 0x00, 0x00 },
349: { 0x4A, 0x00, 0x00, 0x00, 0x00 },
350: { 0x49, 0x00, 0x00, 0x00, 0x00 },
351: { 0x47, 0x00, 0x00, 0x00, 0x00 },
352: { 0x47, 0x00, 0x00, 0x00, 0x00 },
353: { 0x46, 0x00, 0x00, 0x00, 0x00 }
354: };
355:
356:
357: /* Transmit Waveform Values for T1 Short Haul (220 - 330 ft.)
358: ** unsigned char t1_tx_waveform_sh_330ft
359: ** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */
360: TX_WAVEFORM t1_tx_waveform_sh_330ft =
361: {
362: { 0x00, 0x44, 0x00, 0x00, 0x00 },
363: { 0x0A, 0x44, 0x00, 0x00, 0x00 },
364: { 0x3F, 0x43, 0x00, 0x00, 0x00 },
365: { 0x3A, 0x43, 0x00, 0x00, 0x00 },
366: { 0x3A, 0x42, 0x00, 0x00, 0x00 },
367: { 0x38, 0x42, 0x00, 0x00, 0x00 },
368: { 0x30, 0x41, 0x00, 0x00, 0x00 },
369: { 0x2F, 0x41, 0x00, 0x00, 0x00 },
370: { 0x2E, 0x00, 0x00, 0x00, 0x00 },
371: { 0x2D, 0x00, 0x00, 0x00, 0x00 },
372: { 0x2C, 0x00, 0x00, 0x00, 0x00 },
373: { 0x2B, 0x00, 0x00, 0x00, 0x00 },
374: { 0x2A, 0x00, 0x00, 0x00, 0x00 },
375: { 0x29, 0x00, 0x00, 0x00, 0x00 },
376: { 0x23, 0x00, 0x00, 0x00, 0x00 },
377: { 0x4A, 0x00, 0x00, 0x00, 0x00 },
378: { 0x6C, 0x00, 0x00, 0x00, 0x00 },
379: { 0x60, 0x00, 0x00, 0x00, 0x00 },
380: { 0x4F, 0x00, 0x00, 0x00, 0x00 },
381: { 0x4A, 0x00, 0x00, 0x00, 0x00 },
382: { 0x49, 0x00, 0x00, 0x00, 0x00 },
383: { 0x47, 0x00, 0x00, 0x00, 0x00 },
384: { 0x47, 0x00, 0x00, 0x00, 0x00 },
385: { 0x46, 0x00, 0x00, 0x00, 0x00 }
386: };
387:
388:
389: /* Transmit Waveform Values for T1 Short Haul (330 - 440 ft.)
390: ** unsigned char t1_tx_waveform_sh_440ft
391: ** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */
392: TX_WAVEFORM t1_tx_waveform_sh_440ft =
393: {
394: { 0x00, 0x44, 0x00, 0x00, 0x00 },
395: { 0x0A, 0x44, 0x00, 0x00, 0x00 },
396: { 0x3F, 0x43, 0x00, 0x00, 0x00 },
397: { 0x3F, 0x43, 0x00, 0x00, 0x00 },
398: { 0x3F, 0x42, 0x00, 0x00, 0x00 },
399: { 0x3F, 0x42, 0x00, 0x00, 0x00 },
400: { 0x2F, 0x41, 0x00, 0x00, 0x00 },
401: { 0x2E, 0x41, 0x00, 0x00, 0x00 },
402: { 0x2D, 0x00, 0x00, 0x00, 0x00 },
403: { 0x2C, 0x00, 0x00, 0x00, 0x00 },
404: { 0x2B, 0x00, 0x00, 0x00, 0x00 },
405: { 0x2A, 0x00, 0x00, 0x00, 0x00 },
406: { 0x29, 0x00, 0x00, 0x00, 0x00 },
407: { 0x28, 0x00, 0x00, 0x00, 0x00 },
408: { 0x19, 0x00, 0x00, 0x00, 0x00 },
409: { 0x4A, 0x00, 0x00, 0x00, 0x00 },
410: { 0x7F, 0x00, 0x00, 0x00, 0x00 },
411: { 0x60, 0x00, 0x00, 0x00, 0x00 },
412: { 0x4F, 0x00, 0x00, 0x00, 0x00 },
413: { 0x4A, 0x00, 0x00, 0x00, 0x00 },
414: { 0x49, 0x00, 0x00, 0x00, 0x00 },
415: { 0x47, 0x00, 0x00, 0x00, 0x00 },
416: { 0x47, 0x00, 0x00, 0x00, 0x00 },
417: { 0x46, 0x00, 0x00, 0x00, 0x00 }
418: };
419:
420:
421: /* Transmit Waveform Values for T1 Short Haul (440 - 550 ft.)
422: ** unsigned char t1_tx_waveform_sh_550ft
423: ** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */
424: TX_WAVEFORM t1_tx_waveform_sh_550ft =
425: {
426: { 0x00, 0x44, 0x00, 0x00, 0x00 },
427: { 0x0A, 0x44, 0x00, 0x00, 0x00 },
428: { 0x3F, 0x43, 0x00, 0x00, 0x00 },
429: { 0x3F, 0x43, 0x00, 0x00, 0x00 },
430: { 0x3F, 0x42, 0x00, 0x00, 0x00 },
431: { 0x3F, 0x42, 0x00, 0x00, 0x00 },
432: { 0x30, 0x41, 0x00, 0x00, 0x00 },
433: { 0x2B, 0x41, 0x00, 0x00, 0x00 },
434: { 0x2A, 0x00, 0x00, 0x00, 0x00 },
435: { 0x29, 0x00, 0x00, 0x00, 0x00 },
436: { 0x28, 0x00, 0x00, 0x00, 0x00 },
437: { 0x27, 0x00, 0x00, 0x00, 0x00 },
438: { 0x26, 0x00, 0x00, 0x00, 0x00 },
439: { 0x26, 0x00, 0x00, 0x00, 0x00 },
440: { 0x24, 0x00, 0x00, 0x00, 0x00 },
441: { 0x4A, 0x00, 0x00, 0x00, 0x00 },
442: { 0x7F, 0x00, 0x00, 0x00, 0x00 },
443: { 0x7F, 0x00, 0x00, 0x00, 0x00 },
444: { 0x4F, 0x00, 0x00, 0x00, 0x00 },
445: { 0x4A, 0x00, 0x00, 0x00, 0x00 },
446: { 0x49, 0x00, 0x00, 0x00, 0x00 },
447: { 0x47, 0x00, 0x00, 0x00, 0x00 },
448: { 0x47, 0x00, 0x00, 0x00, 0x00 },
449: { 0x46, 0x00, 0x00, 0x00, 0x00 }
450: };
451:
452:
453: /* Transmit Waveform Values for T1 Short Haul (550 - 660 ft.)
454: ** unsigned char t1_tx_waveform_sh_660ft
455: ** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */
456: TX_WAVEFORM t1_tx_waveform_sh_660ft =
457: {
458: { 0x00, 0x44, 0x00, 0x00, 0x00 },
459: { 0x0A, 0x44, 0x00, 0x00, 0x00 },
460: { 0x3F, 0x43, 0x00, 0x00, 0x00 },
461: { 0x3F, 0x43, 0x00, 0x00, 0x00 },
462: { 0x3F, 0x42, 0x00, 0x00, 0x00 },
463: { 0x3F, 0x42, 0x00, 0x00, 0x00 },
464: { 0x3F, 0x41, 0x00, 0x00, 0x00 },
465: { 0x30, 0x41, 0x00, 0x00, 0x00 },
466: { 0x2A, 0x00, 0x00, 0x00, 0x00 },
467: { 0x29, 0x00, 0x00, 0x00, 0x00 },
468: { 0x28, 0x00, 0x00, 0x00, 0x00 },
469: { 0x27, 0x00, 0x00, 0x00, 0x00 },
470: { 0x26, 0x00, 0x00, 0x00, 0x00 },
471: { 0x25, 0x00, 0x00, 0x00, 0x00 },
472: { 0x24, 0x00, 0x00, 0x00, 0x00 },
473: { 0x4A, 0x00, 0x00, 0x00, 0x00 },
474: { 0x7F, 0x00, 0x00, 0x00, 0x00 },
475: { 0x7F, 0x00, 0x00, 0x00, 0x00 },
476: { 0x5F, 0x00, 0x00, 0x00, 0x00 },
477: { 0x50, 0x00, 0x00, 0x00, 0x00 },
478: { 0x49, 0x00, 0x00, 0x00, 0x00 },
479: { 0x47, 0x00, 0x00, 0x00, 0x00 },
480: { 0x47, 0x00, 0x00, 0x00, 0x00 },
481: { 0x46, 0x00, 0x00, 0x00, 0x00 }
482: };
483:
484:
485: /* Transmit Waveform Values for E1 120 Ohm
486: ** unsigned char e1_tx_waveform_120
487: ** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */
488: TX_WAVEFORM e1_tx_waveform_120 =
489: {
490: { 0x00, 0x00, 0x00, 0x00, 0x00 },
491: { 0x00, 0x00, 0x00, 0x00, 0x00 },
492: { 0x0A, 0x00, 0x00, 0x00, 0x00 },
493: { 0x3F, 0x00, 0x00, 0x00, 0x00 },
494: { 0x3F, 0x00, 0x00, 0x00, 0x00 },
495: { 0x39, 0x00, 0x00, 0x00, 0x00 },
496: { 0x38, 0x00, 0x00, 0x00, 0x00 },
497: { 0x36, 0x00, 0x00, 0x00, 0x00 },
498: { 0x36, 0x00, 0x00, 0x00, 0x00 },
499: { 0x35, 0x00, 0x00, 0x00, 0x00 },
500: { 0x35, 0x00, 0x00, 0x00, 0x00 },
501: { 0x35, 0x00, 0x00, 0x00, 0x00 },
502: { 0x35, 0x00, 0x00, 0x00, 0x00 },
503: { 0x35, 0x00, 0x00, 0x00, 0x00 },
504: { 0x35, 0x00, 0x00, 0x00, 0x00 },
505: { 0x2D, 0x00, 0x00, 0x00, 0x00 },
506: { 0x00, 0x00, 0x00, 0x00, 0x00 },
507: { 0x00, 0x00, 0x00, 0x00, 0x00 },
508: { 0x00, 0x00, 0x00, 0x00, 0x00 },
509: { 0x00, 0x00, 0x00, 0x00, 0x00 },
510: { 0x00, 0x00, 0x00, 0x00, 0x00 },
511: { 0x00, 0x00, 0x00, 0x00, 0x00 },
512: { 0x00, 0x00, 0x00, 0x00, 0x00 },
513: { 0x00, 0x00, 0x00, 0x00, 0x00 }
514: };
515:
516:
517: /* Transmit Waveform Values for E1 75 Ohm
518: ** unsigned char e1_tx_waveform_75
519: ** [LAST_SAMPLE-FIRST_SAMPLE+1][LAST_UI-FIRST_UI+1] = */
520: TX_WAVEFORM e1_tx_waveform_75 =
521: {
522: { 0x00, 0x00, 0x00, 0x00, 0x00 },
523: { 0x00, 0x00, 0x00, 0x00, 0x00 },
524: { 0x0A, 0x00, 0x00, 0x00, 0x00 },
525: { 0x28, 0x00, 0x00, 0x00, 0x00 },
526: { 0x3A, 0x00, 0x00, 0x00, 0x00 },
527: { 0x3A, 0x00, 0x00, 0x00, 0x00 },
528: { 0x3A, 0x00, 0x00, 0x00, 0x00 },
529: { 0x3A, 0x00, 0x00, 0x00, 0x00 },
530: { 0x3A, 0x00, 0x00, 0x00, 0x00 },
531: { 0x3A, 0x00, 0x00, 0x00, 0x00 },
532: { 0x3A, 0x00, 0x00, 0x00, 0x00 },
533: { 0x3A, 0x00, 0x00, 0x00, 0x00 },
534: { 0x3A, 0x00, 0x00, 0x00, 0x00 },
535: { 0x3A, 0x00, 0x00, 0x00, 0x00 },
536: { 0x32, 0x00, 0x00, 0x00, 0x00 },
537: { 0x14, 0x00, 0x00, 0x00, 0x00 },
538: { 0x00, 0x00, 0x00, 0x00, 0x00 },
539: { 0x00, 0x00, 0x00, 0x00, 0x00 },
540: { 0x00, 0x00, 0x00, 0x00, 0x00 },
541: { 0x00, 0x00, 0x00, 0x00, 0x00 },
542: { 0x00, 0x00, 0x00, 0x00, 0x00 },
543: { 0x00, 0x00, 0x00, 0x00, 0x00 },
544: { 0x00, 0x00, 0x00, 0x00, 0x00 },
545: { 0x00, 0x00, 0x00, 0x00, 0x00 }
546: };
547:
548:
549: RLPS_EQUALIZER_RAM t1_rlps_ram_table[] =
550: {
551: { 0x03, 0xFE, 0x18, 0x40 },
552: { 0x03, 0xF6, 0x18, 0x40 },
553: { 0x03, 0xEE, 0x18, 0x40 },
554: { 0x03, 0xE6, 0x18, 0x40 },
555: { 0x03, 0xDE, 0x18, 0x40 },
556: { 0x03, 0xD6, 0x18, 0x40 },
557: { 0x03, 0xD6, 0x18, 0x40 },
558: { 0x03, 0xD6, 0x18, 0x40 },
559: { 0x03, 0xCE, 0x18, 0x40 },
560: { 0x03, 0xCE, 0x18, 0x40 },
561: { 0x03, 0xCE, 0x18, 0x40 },
562: { 0x03, 0xCE, 0x18, 0x40 },
563: { 0x03, 0xC6, 0x18, 0x40 },
564: { 0x03, 0xC6, 0x18, 0x40 },
565: { 0x03, 0xC6, 0x18, 0x40 },
566: { 0x0B, 0xBE, 0x18, 0x40 },
567: { 0x0B, 0xBE, 0x18, 0x40 },
568: { 0x0B, 0xBE, 0x18, 0x40 },
569: { 0x0B, 0xBE, 0x18, 0x40 },
570: { 0x0B, 0xB6, 0x18, 0x40 },
571: { 0x0B, 0xB6, 0x18, 0x40 },
572: { 0x0B, 0xB6, 0x18, 0x40 },
573: { 0x0B, 0xB6, 0x18, 0x40 },
574: { 0x13, 0xAE, 0x18, 0x38 },
575: { 0x13, 0xAE, 0x18, 0x3C },
576: { 0x13, 0xAE, 0x18, 0x40 },
577: { 0x13, 0xAE, 0x18, 0x40 },
578: { 0x13, 0xAE, 0x18, 0x40 },
579: { 0x13, 0xAE, 0x18, 0x40 },
580: { 0x1B, 0xB6, 0x18, 0xB8 },
581: { 0x1B, 0xAE, 0x18, 0xB8 },
582: { 0x1B, 0xAE, 0x18, 0xBC },
583: { 0x1B, 0xAE, 0x18, 0xC0 },
584: { 0x1B, 0xAE, 0x18, 0xC0 },
585: { 0x23, 0xA6, 0x18, 0xC0 },
586: { 0x23, 0xA6, 0x18, 0xC0 },
587: { 0x23, 0xA6, 0x18, 0xC0 },
588: { 0x23, 0xA6, 0x18, 0xC0 },
589: { 0x23, 0xA6, 0x18, 0xC0 },
590: { 0x23, 0x9E, 0x18, 0xC0 },
591: { 0x23, 0x9E, 0x18, 0xC0 },
592: { 0x23, 0x9E, 0x18, 0xC0 },
593: { 0x23, 0x9E, 0x18, 0xC0 },
594: { 0x23, 0x9E, 0x18, 0xC0 },
595: { 0x2B, 0x96, 0x18, 0xC0 },
596: { 0x2B, 0x96, 0x18, 0xC0 },
597: { 0x2B, 0x96, 0x18, 0xC0 },
598: { 0x33, 0x96, 0x19, 0x40 },
599: { 0x37, 0x96, 0x19, 0x40 },
600: { 0x37, 0x96, 0x19, 0x40 },
601: { 0x37, 0x96, 0x19, 0x40 },
602: { 0x3F, 0x9E, 0x19, 0xC0 },
603: { 0x3F, 0x9E, 0x19, 0xC0 },
604: { 0x3F, 0x9E, 0x19, 0xC0 },
605: { 0x3F, 0xA6, 0x1A, 0x40 },
606: { 0x3F, 0xA6, 0x1A, 0x40 },
607: { 0x3F, 0xA6, 0x1A, 0x40 },
608: { 0x3F, 0xA6, 0x1A, 0x40 },
609: { 0x3F, 0x96, 0x19, 0xC0 },
610: { 0x3F, 0x96, 0x19, 0xC0 },
611: { 0x3F, 0x96, 0x19, 0xC0 },
612: { 0x3F, 0x96, 0x19, 0xC0 },
613: { 0x47, 0x9E, 0x1A, 0x40 },
614: { 0x47, 0x9E, 0x1A, 0x40 },
615: { 0x47, 0x9E, 0x1A, 0x40 },
616: { 0x47, 0x96, 0x1A, 0x40 },
617: { 0x47, 0x96, 0x1A, 0x40 },
618: { 0x47, 0x96, 0x1A, 0x40 },
619: { 0x47, 0x96, 0x1A, 0x40 },
620: { 0x4F, 0x8E, 0x1A, 0x40 },
621: { 0x4F, 0x8E, 0x1A, 0x40 },
622: { 0x4F, 0x8E, 0x1A, 0x40 },
623: { 0x4F, 0x8E, 0x1A, 0x40 },
624: { 0x4F, 0x8E, 0x1A, 0x40 },
625: { 0x57, 0x86, 0x1A, 0x40 },
626: { 0x57, 0x86, 0x1A, 0x40 },
627: { 0x57, 0x86, 0x1A, 0x40 },
628: { 0x57, 0x86, 0x1A, 0x40 },
629: { 0x57, 0x86, 0x1A, 0x40 },
630: { 0x5F, 0x86, 0x1A, 0xC0 },
631: { 0x5F, 0x86, 0x1A, 0xC0 },
632: { 0x5F, 0x86, 0x1A, 0xC0 },
633: { 0x5F, 0x86, 0x1A, 0xC0 },
634: { 0x5F, 0x86, 0x1A, 0xC0 },
635: { 0x5F, 0x86, 0x1A, 0xC0 },
636: { 0x5F, 0x7E, 0x1A, 0xC0 },
637: { 0x5F, 0x7E, 0x1A, 0xC0 },
638: { 0x5F, 0x7E, 0x1A, 0xC0 },
639: { 0x5F, 0x7E, 0x1A, 0xC0 },
640: { 0x5F, 0x7E, 0x1A, 0xC0 },
641: { 0x67, 0x7E, 0x2A, 0xC0 },
642: { 0x67, 0x7E, 0x2A, 0xC0 },
643: { 0x67, 0x7E, 0x2A, 0xC0 },
644: { 0x67, 0x7E, 0x2A, 0xC0 },
645: { 0x67, 0x76, 0x2A, 0xC0 },
646: { 0x67, 0x76, 0x2A, 0xC0 },
647: { 0x67, 0x76, 0x2A, 0xC0 },
648: { 0x67, 0x76, 0x2A, 0xC0 },
649: { 0x67, 0x76, 0x2A, 0xC0 },
650: { 0x6F, 0x6E, 0x2A, 0xC0 },
651: { 0x6F, 0x6E, 0x2A, 0xC0 },
652: { 0x6F, 0x6E, 0x2A, 0xC0 },
653: { 0x6F, 0x6E, 0x2A, 0xC0 },
654: { 0x77, 0x6E, 0x3A, 0xC0 },
655: { 0x77, 0x6E, 0x3A, 0xC0 },
656: { 0x77, 0x6E, 0x3A, 0xC0 },
657: { 0x77, 0x6E, 0x3A, 0xC0 },
658: { 0x7F, 0x66, 0x3A, 0xC0 },
659: { 0x7F, 0x66, 0x3A, 0xC0 },
660: { 0x7F, 0x66, 0x4A, 0xC0 },
661: { 0x7F, 0x66, 0x4A, 0xC0 },
662: { 0x7F, 0x66, 0x4A, 0xC0 },
663: { 0x7F, 0x66, 0x4A, 0xC0 },
664: { 0x87, 0x66, 0x5A, 0xC0 },
665: { 0x87, 0x66, 0x5A, 0xC0 },
666: { 0x87, 0x66, 0x5A, 0xC0 },
667: { 0x87, 0x66, 0x5A, 0xC0 },
668: { 0x87, 0x66, 0x5A, 0xC0 },
669: { 0x87, 0x5E, 0x5A, 0xC0 },
670: { 0x87, 0x5E, 0x5A, 0xC0 },
671: { 0x87, 0x5E, 0x5A, 0xC0 },
672: { 0x87, 0x5E, 0x5A, 0xC0 },
673: { 0x87, 0x5E, 0x5A, 0xC0 },
674: { 0x8F, 0x5E, 0x6A, 0xC0 },
675: { 0x8F, 0x5E, 0x6A, 0xC0 },
676: { 0x8F, 0x5E, 0x6A, 0xC0 },
677: { 0x8F, 0x5E, 0x6A, 0xC0 },
678: { 0x97, 0x5E, 0x7A, 0xC0 },
679: { 0x97, 0x5E, 0x7A, 0xC0 },
680: { 0x97, 0x5E, 0x7A, 0xC0 },
681: { 0x97, 0x5E, 0x7A, 0xC0 },
682: { 0x9F, 0x5E, 0x8A, 0xC0 },
683: { 0x9F, 0x5E, 0x8A, 0xC0 },
684: { 0x9F, 0x5E, 0x8A, 0xC0 },
685: { 0x9F, 0x5E, 0x8A, 0xC0 },
686: { 0x9F, 0x5E, 0x8A, 0xC0 },
687: { 0xA7, 0x56, 0x9A, 0xC0 },
688: { 0xA7, 0x56, 0x9A, 0xC0 },
689: { 0xA7, 0x56, 0x9A, 0xC0 },
690: { 0xA7, 0x56, 0x9A, 0xC0 },
691: { 0xA7, 0x56, 0xAA, 0xC0 },
692: { 0xA7, 0x56, 0xAA, 0xC0 },
693: { 0xA7, 0x56, 0xAA, 0xC0 },
694: { 0xAF, 0x4E, 0xAA, 0xC0 },
695: { 0xAF, 0x4E, 0xAA, 0xC0 },
696: { 0xAF, 0x4E, 0xAA, 0xC0 },
697: { 0xAF, 0x4E, 0xAA, 0xC0 },
698: { 0xAF, 0x4E, 0xAA, 0xC0 },
699: { 0xB7, 0x46, 0xAA, 0xC0 },
700: { 0xB7, 0x46, 0xAA, 0xC0 },
701: { 0xB7, 0x46, 0xAA, 0xC0 },
702: { 0xB7, 0x46, 0xAA, 0xC0 },
703: { 0xB7, 0x46, 0xAA, 0xC0 },
704: { 0xB7, 0x46, 0xAA, 0xC0 },
705: { 0xB7, 0x46, 0xAA, 0xC0 },
706: { 0xB7, 0x46, 0xBA, 0xC0 },
707: { 0xB7, 0x46, 0xBA, 0xC0 },
708: { 0xB7, 0x46, 0xBA, 0xC0 },
709: { 0xBF, 0x4E, 0xBB, 0x40 },
710: { 0xBF, 0x4E, 0xBB, 0x40 },
711: { 0xBF, 0x4E, 0xBB, 0x40 },
712: { 0xBF, 0x4E, 0xBB, 0x40 },
713: { 0xBF, 0x4E, 0xBB, 0x40 },
714: { 0xBF, 0x4E, 0xBB, 0x40 },
715: { 0xBF, 0x4E, 0xBB, 0x40 },
716: { 0xBF, 0x4E, 0xBB, 0x40 },
717: { 0xBF, 0x4E, 0xBB, 0x40 },
718: { 0xBE, 0x46, 0xCB, 0x40 },
719: { 0xBE, 0x46, 0xCB, 0x40 },
720: { 0xBE, 0x46, 0xCB, 0x40 },
721: { 0xBE, 0x46, 0xCB, 0x40 },
722: { 0xBE, 0x46, 0xCB, 0x40 },
723: { 0xBE, 0x46, 0xCB, 0x40 },
724: { 0xBE, 0x46, 0xDB, 0x40 },
725: { 0xBE, 0x46, 0xDB, 0x40 },
726: { 0xBE, 0x46, 0xDB, 0x40 },
727: { 0xC6, 0x3E, 0xCB, 0x40 },
728: { 0xC6, 0x3E, 0xCB, 0x40 },
729: { 0xC6, 0x3E, 0xDB, 0x40 },
730: { 0xC6, 0x3E, 0xDB, 0x40 },
731: { 0xC6, 0x3E, 0xDB, 0x40 },
732: { 0xC6, 0x44, 0xDB, 0x40 },
733: { 0xC6, 0x44, 0xDB, 0x40 },
734: { 0xC6, 0x44, 0xDB, 0x40 },
735: { 0xC6, 0x44, 0xDB, 0x40 },
736: { 0xC6, 0x3C, 0xDB, 0x40 },
737: { 0xC6, 0x3C, 0xDB, 0x40 },
738: { 0xC6, 0x3C, 0xDB, 0x40 },
739: { 0xC6, 0x3C, 0xDB, 0x40 },
740: { 0xD6, 0x34, 0xDB, 0x40 },
741: { 0xD6, 0x34, 0xDB, 0x40 },
742: { 0xD6, 0x34, 0xDB, 0x40 },
743: { 0xD6, 0x34, 0xDB, 0x40 },
744: { 0xD6, 0x34, 0xDB, 0x40 },
745: { 0xDE, 0x2C, 0xDB, 0x3C },
746: { 0xDE, 0x2C, 0xDB, 0x3C },
747: { 0xDE, 0x2C, 0xDB, 0x3C },
748: { 0xE6, 0x2C, 0xDB, 0x40 },
749: { 0xE6, 0x2C, 0xDB, 0x40 },
750: { 0xE6, 0x2C, 0xDB, 0x40 },
751: { 0xE6, 0x2C, 0xDB, 0x40 },
752: { 0xE6, 0x2C, 0xDB, 0x40 },
753: { 0xE6, 0x2C, 0xEB, 0x40 },
754: { 0xE6, 0x2C, 0xEB, 0x40 },
755: { 0xE6, 0x2C, 0xEB, 0x40 },
756: { 0xEE, 0x2C, 0xFB, 0x40 },
757: { 0xEE, 0x2C, 0xFB, 0x40 },
758: { 0xEE, 0x2C, 0xFB, 0x40 },
759: { 0xEE, 0x2D, 0x0B, 0x40 },
760: { 0xEE, 0x2D, 0x0B, 0x40 },
761: { 0xEE, 0x2D, 0x0B, 0x40 },
762: { 0xEE, 0x2D, 0x0B, 0x40 },
763: { 0xEE, 0x2D, 0x0B, 0x40 },
764: { 0xF5, 0x25, 0x0B, 0x38 },
765: { 0xF5, 0x25, 0x0B, 0x3C },
766: { 0xF5, 0x25, 0x0B, 0x40 },
767: { 0xF5, 0x25, 0x1B, 0x40 },
768: { 0xF5, 0x25, 0x1B, 0x40 },
769: { 0xF5, 0x25, 0x1B, 0x40 },
770: { 0xF5, 0x25, 0x1B, 0x40 },
771: { 0xF5, 0x25, 0x1B, 0x40 },
772: { 0xFD, 0x25, 0x2B, 0x40 },
773: { 0xFD, 0x25, 0x2B, 0x40 },
774: { 0xFD, 0x25, 0x2B, 0x40 },
775: { 0xFD, 0x25, 0x2B, 0x40 },
776: { 0xFD, 0x25, 0x27, 0x40 },
777: { 0xFD, 0x25, 0x27, 0x40 },
778: { 0xFD, 0x25, 0x27, 0x40 },
779: { 0xFD, 0x25, 0x23, 0x40 },
780: { 0xFD, 0x25, 0x23, 0x40 },
781: { 0xFD, 0x25, 0x23, 0x40 },
782: { 0xFD, 0x25, 0x33, 0x40 },
783: { 0xFD, 0x25, 0x33, 0x40 },
784: { 0xFD, 0x25, 0x33, 0x40 },
785: { 0xFD, 0x25, 0x33, 0x40 },
786: { 0xFD, 0x25, 0x33, 0x40 },
787: { 0xFD, 0x25, 0x33, 0x40 },
788: { 0xFC, 0x25, 0x33, 0x40 },
789: { 0xFC, 0x25, 0x33, 0x40 },
790: { 0xFC, 0x25, 0x43, 0x40 },
791: { 0xFC, 0x25, 0x43, 0x40 },
792: { 0xFC, 0x25, 0x43, 0x40 },
793: { 0xFC, 0x25, 0x43, 0x44 },
794: { 0xFC, 0x25, 0x43, 0x48 },
795: { 0xFC, 0x25, 0x43, 0x4C },
796: { 0xFC, 0x25, 0x43, 0xBC },
797: { 0xFC, 0x25, 0x43, 0xC0 },
798: { 0xFC, 0x25, 0x43, 0xC0 },
799: { 0xFC, 0x23, 0x43, 0xC0 },
800: { 0xFC, 0x23, 0x43, 0xC0 },
801: { 0xFC, 0x23, 0x43, 0xC0 },
802: { 0xFC, 0x21, 0x43, 0xC0 },
803: { 0xFC, 0x21, 0x43, 0xC0 },
804: { 0xFC, 0x21, 0x53, 0xC0 },
805: { 0xFC, 0x21, 0x53, 0xC0 },
806: { 0xFC, 0x21, 0x53, 0xC0 }
807: };
808:
809: RLPS_EQUALIZER_RAM t1_rlps_perf_mode_ram_table[] =
810: {
811: { 0x03, 0xFE, 0x18, 0x40 },
812: { 0x03, 0xFE, 0x18, 0x40 },
813: { 0x03, 0xFE, 0x18, 0x40 },
814: { 0x03, 0xFE, 0x18, 0x40 },
815: { 0x03, 0xFE, 0x18, 0x40 },
816: { 0x03, 0xFE, 0x18, 0x40 },
817: { 0x03, 0xFE, 0x18, 0x40 },
818: { 0x03, 0xFE, 0x18, 0x40 },
819: { 0x03, 0xF6, 0x18, 0x40 },
820: { 0x03, 0xF6, 0x18, 0x40 },
821: { 0x03, 0xF6, 0x18, 0x40 },
822: { 0x03, 0xF6, 0x18, 0x40 },
823: { 0x03, 0xF6, 0x18, 0x40 },
824: { 0x03, 0xF6, 0x18, 0x40 },
825: { 0x03, 0xF6, 0x18, 0x40 },
826: { 0x03, 0xF6, 0x18, 0x40 },
827: { 0x03, 0xEE, 0x18, 0x40 },
828: { 0x03, 0xEE, 0x18, 0x40 },
829: { 0x03, 0xEE, 0x18, 0x40 },
830: { 0x03, 0xEE, 0x18, 0x40 },
831: { 0x03, 0xEE, 0x18, 0x40 },
832: { 0x03, 0xEE, 0x18, 0x40 },
833: { 0x03, 0xEE, 0x18, 0x40 },
834: { 0x03, 0xEE, 0x18, 0x40 },
835: { 0x03, 0xE6, 0x18, 0x40 },
836: { 0x03, 0xE6, 0x18, 0x40 },
837: { 0x03, 0xE6, 0x18, 0x40 },
838: { 0x03, 0xE6, 0x18, 0x40 },
839: { 0x03, 0xE6, 0x18, 0x40 },
840: { 0x03, 0xE6, 0x18, 0x40 },
841: { 0x03, 0xE6, 0x18, 0x40 },
842: { 0x03, 0xE6, 0x18, 0x40 },
843: { 0x03, 0xDE, 0x18, 0x40 },
844: { 0x03, 0xDE, 0x18, 0x40 },
845: { 0x03, 0xDE, 0x18, 0x40 },
846: { 0x03, 0xDE, 0x18, 0x40 },
847: { 0x03, 0xDE, 0x18, 0x40 },
848: { 0x03, 0xDE, 0x18, 0x40 },
849: { 0x03, 0xDE, 0x18, 0x40 },
850: { 0x03, 0xDE, 0x18, 0x40 },
851: { 0x03, 0xD6, 0x18, 0x40 },
852: { 0x03, 0xD6, 0x18, 0x40 },
853: { 0x03, 0xD6, 0x18, 0x40 },
854: { 0x03, 0xD6, 0x18, 0x40 },
855: { 0x03, 0xD6, 0x18, 0x40 },
856: { 0x03, 0xD6, 0x18, 0x40 },
857: { 0x03, 0xD6, 0x18, 0x40 },
858: { 0x03, 0xD6, 0x18, 0x40 },
859: { 0x03, 0xCE, 0x18, 0x40 },
860: { 0x03, 0xCE, 0x18, 0x40 },
861: { 0x03, 0xCE, 0x18, 0x40 },
862: { 0x03, 0xCE, 0x18, 0x40 },
863: { 0x03, 0xCE, 0x18, 0x40 },
864: { 0x03, 0xCE, 0x18, 0x40 },
865: { 0x03, 0xCE, 0x18, 0x40 },
866: { 0x03, 0xCE, 0x18, 0x40 },
867: { 0x03, 0xC6, 0x18, 0x40 },
868: { 0x03, 0xC6, 0x18, 0x40 },
869: { 0x03, 0xC6, 0x18, 0x40 },
870: { 0x03, 0xC6, 0x18, 0x40 },
871: { 0x03, 0xC6, 0x18, 0x40 },
872: { 0x03, 0xC6, 0x18, 0x40 },
873: { 0x03, 0xC6, 0x18, 0x40 },
874: { 0x03, 0xC6, 0x18, 0x40 },
875: { 0x03, 0xBE, 0x18, 0x40 },
876: { 0x03, 0xBE, 0x18, 0x40 },
877: { 0x03, 0xBE, 0x18, 0x40 },
878: { 0x03, 0xBE, 0x18, 0x40 },
879: { 0x03, 0xBE, 0x18, 0x40 },
880: { 0x03, 0xBE, 0x18, 0x40 },
881: { 0x03, 0xBE, 0x18, 0x40 },
882: { 0x03, 0xBE, 0x18, 0x40 },
883: { 0x03, 0xB6, 0x18, 0x40 },
884: { 0x03, 0xB6, 0x18, 0x40 },
885: { 0x03, 0xB6, 0x18, 0x40 },
886: { 0x03, 0xB6, 0x18, 0x40 },
887: { 0x03, 0xB6, 0x18, 0x40 },
888: { 0x03, 0xB6, 0x18, 0x40 },
889: { 0x03, 0xB6, 0x18, 0x40 },
890: { 0x03, 0xB6, 0x18, 0x40 },
891: { 0x03, 0xA6, 0x18, 0x40 },
892: { 0x03, 0xA6, 0x18, 0x40 },
893: { 0x03, 0xA6, 0x18, 0x40 },
894: { 0x03, 0xA6, 0x18, 0x40 },
895: { 0x03, 0xA6, 0x18, 0x40 },
896: { 0x03, 0xA6, 0x18, 0x40 },
897: { 0x03, 0xA6, 0x18, 0x40 },
898: { 0x03, 0xA6, 0x18, 0x40 },
899: { 0x03, 0x9E, 0x18, 0x40 },
900: { 0x03, 0x9E, 0x18, 0x40 },
901: { 0x03, 0x9E, 0x18, 0x40 },
902: { 0x03, 0x9E, 0x18, 0x40 },
903: { 0x03, 0x9E, 0x18, 0x40 },
904: { 0x03, 0x9E, 0x18, 0x40 },
905: { 0x03, 0x9E, 0x18, 0x40 },
906: { 0x03, 0x9E, 0x18, 0x40 },
907: { 0x03, 0x96, 0x18, 0x40 },
908: { 0x03, 0x96, 0x18, 0x40 },
909: { 0x03, 0x96, 0x18, 0x40 },
910: { 0x03, 0x96, 0x18, 0x40 },
911: { 0x03, 0x96, 0x18, 0x40 },
912: { 0x03, 0x96, 0x18, 0x40 },
913: { 0x03, 0x96, 0x18, 0x40 },
914: { 0x03, 0x96, 0x18, 0x40 },
915: { 0x03, 0x8E, 0x18, 0x40 },
916: { 0x03, 0x8E, 0x18, 0x40 },
917: { 0x03, 0x8E, 0x18, 0x40 },
918: { 0x03, 0x8E, 0x18, 0x40 },
919: { 0x03, 0x8E, 0x18, 0x40 },
920: { 0x03, 0x8E, 0x18, 0x40 },
921: { 0x03, 0x8E, 0x18, 0x40 },
922: { 0x03, 0x8E, 0x18, 0x40 },
923: { 0x03, 0x86, 0x18, 0x40 },
924: { 0x03, 0x86, 0x18, 0x40 },
925: { 0x03, 0x86, 0x18, 0x40 },
926: { 0x03, 0x86, 0x18, 0x40 },
927: { 0x03, 0x86, 0x18, 0x40 },
928: { 0x03, 0x86, 0x18, 0x40 },
929: { 0x03, 0x86, 0x18, 0x40 },
930: { 0x03, 0x86, 0x18, 0x40 },
931: { 0x03, 0x7E, 0x18, 0x40 },
932: { 0x03, 0x7E, 0x18, 0x40 },
933: { 0x03, 0x7E, 0x18, 0x40 },
934: { 0x03, 0x7E, 0x18, 0x40 },
935: { 0x03, 0x7E, 0x18, 0x40 },
936: { 0x03, 0x7E, 0x18, 0x40 },
937: { 0x03, 0x7E, 0x18, 0x40 },
938: { 0x03, 0x7E, 0x18, 0x40 },
939: { 0x03, 0x76, 0x18, 0x40 },
940: { 0x03, 0x76, 0x18, 0x40 },
941: { 0x03, 0x76, 0x18, 0x40 },
942: { 0x03, 0x76, 0x18, 0x40 },
943: { 0x03, 0x76, 0x18, 0x40 },
944: { 0x03, 0x76, 0x18, 0x40 },
945: { 0x03, 0x76, 0x18, 0x40 },
946: { 0x03, 0x76, 0x18, 0x40 },
947: { 0x03, 0x6E, 0x18, 0x40 },
948: { 0x03, 0x6E, 0x18, 0x40 },
949: { 0x03, 0x6E, 0x18, 0x40 },
950: { 0x03, 0x6E, 0x18, 0x40 },
951: { 0x03, 0x6E, 0x18, 0x40 },
952: { 0x03, 0x6E, 0x18, 0x40 },
953: { 0x03, 0x6E, 0x18, 0x40 },
954: { 0x03, 0x6E, 0x18, 0x40 },
955: { 0x03, 0x66, 0x18, 0x40 },
956: { 0x03, 0x66, 0x18, 0x40 },
957: { 0x03, 0x66, 0x18, 0x40 },
958: { 0x03, 0x66, 0x18, 0x40 },
959: { 0x03, 0x66, 0x18, 0x40 },
960: { 0x03, 0x66, 0x18, 0x40 },
961: { 0x03, 0x66, 0x18, 0x40 },
962: { 0x03, 0x66, 0x18, 0x40 },
963: { 0x03, 0x5E, 0x18, 0x40 },
964: { 0x03, 0x5E, 0x18, 0x40 },
965: { 0x03, 0x5E, 0x18, 0x40 },
966: { 0x03, 0x5E, 0x18, 0x40 },
967: { 0x03, 0x5E, 0x18, 0x40 },
968: { 0x03, 0x5E, 0x18, 0x40 },
969: { 0x03, 0x5E, 0x18, 0x40 },
970: { 0x03, 0x5E, 0x18, 0x40 },
971: { 0x03, 0x56, 0x18, 0x40 },
972: { 0x03, 0x56, 0x18, 0x40 },
973: { 0x03, 0x56, 0x18, 0x40 },
974: { 0x03, 0x56, 0x18, 0x40 },
975: { 0x03, 0x56, 0x18, 0x40 },
976: { 0x03, 0x56, 0x18, 0x40 },
977: { 0x03, 0x56, 0x18, 0x40 },
978: { 0x03, 0x56, 0x18, 0x40 },
979: { 0x03, 0x4E, 0x18, 0x40 },
980: { 0x03, 0x4E, 0x18, 0x40 },
981: { 0x03, 0x4E, 0x18, 0x40 },
982: { 0x03, 0x4E, 0x18, 0x40 },
983: { 0x03, 0x4E, 0x18, 0x40 },
984: { 0x03, 0x4E, 0x18, 0x40 },
985: { 0x03, 0x4E, 0x18, 0x40 },
986: { 0x03, 0x4E, 0x18, 0x40 },
987: { 0x03, 0x46, 0x18, 0x40 },
988: { 0x03, 0x46, 0x18, 0x40 },
989: { 0x03, 0x46, 0x18, 0x40 },
990: { 0x03, 0x46, 0x18, 0x40 },
991: { 0x03, 0x46, 0x18, 0x40 },
992: { 0x03, 0x46, 0x18, 0x40 },
993: { 0x03, 0x46, 0x18, 0x40 },
994: { 0x03, 0x46, 0x18, 0x40 },
995: { 0x03, 0x3E, 0x18, 0x40 },
996: { 0x03, 0x3E, 0x18, 0x40 },
997: { 0x03, 0x3E, 0x18, 0x40 },
998: { 0x03, 0x3E, 0x18, 0x40 },
999: { 0x03, 0x3E, 0x18, 0x40 },
1000: { 0x03, 0x3E, 0x18, 0x40 },
1001: { 0x03, 0x3E, 0x18, 0x40 },
1002: { 0x03, 0x3E, 0x18, 0x40 },
1003: { 0x03, 0x36, 0x18, 0x40 },
1004: { 0x03, 0x36, 0x18, 0x40 },
1005: { 0x03, 0x36, 0x18, 0x40 },
1006: { 0x03, 0x36, 0x18, 0x40 },
1007: { 0x03, 0x36, 0x18, 0x40 },
1008: { 0x03, 0x36, 0x18, 0x40 },
1009: { 0x03, 0x36, 0x18, 0x40 },
1010: { 0x03, 0x36, 0x18, 0x40 },
1011: { 0x03, 0x2E, 0x18, 0x40 },
1012: { 0x03, 0x2E, 0x18, 0x40 },
1013: { 0x03, 0x2E, 0x18, 0x40 },
1014: { 0x03, 0x2E, 0x18, 0x40 },
1015: { 0x03, 0x2E, 0x18, 0x40 },
1016: { 0x03, 0x2E, 0x18, 0x40 },
1017: { 0x03, 0x2E, 0x18, 0x40 },
1018: { 0x03, 0x2E, 0x18, 0x40 },
1019: { 0x03, 0x26, 0x18, 0x40 },
1020: { 0x03, 0x26, 0x18, 0x40 },
1021: { 0x03, 0x26, 0x18, 0x40 },
1022: { 0x03, 0x26, 0x18, 0x40 },
1023: { 0x03, 0x26, 0x18, 0x40 },
1024: { 0x03, 0x26, 0x18, 0x40 },
1025: { 0x03, 0x26, 0x18, 0x40 },
1026: { 0x03, 0x26, 0x18, 0x40 },
1027: { 0x03, 0x1E, 0x18, 0x40 },
1028: { 0x03, 0x1E, 0x18, 0x40 },
1029: { 0x03, 0x1E, 0x18, 0x40 },
1030: { 0x03, 0x1E, 0x18, 0x40 },
1031: { 0x03, 0x1E, 0x18, 0x40 },
1032: { 0x03, 0x1E, 0x18, 0x40 },
1033: { 0x03, 0x1E, 0x18, 0x40 },
1034: { 0x03, 0x1E, 0x18, 0x40 },
1035: { 0x03, 0x16, 0x18, 0x40 },
1036: { 0x03, 0x16, 0x18, 0x40 },
1037: { 0x03, 0x16, 0x18, 0x40 },
1038: { 0x03, 0x16, 0x18, 0x40 },
1039: { 0x03, 0x16, 0x18, 0x40 },
1040: { 0x03, 0x16, 0x18, 0x40 },
1041: { 0x03, 0x16, 0x18, 0x40 },
1042: { 0x03, 0x16, 0x18, 0x40 },
1043: { 0x03, 0x0E, 0x18, 0x40 },
1044: { 0x03, 0x0E, 0x18, 0x40 },
1045: { 0x03, 0x0E, 0x18, 0x40 },
1046: { 0x03, 0x0E, 0x18, 0x40 },
1047: { 0x03, 0x0E, 0x18, 0x40 },
1048: { 0x03, 0x0E, 0x18, 0x40 },
1049: { 0x03, 0x0E, 0x18, 0x40 },
1050: { 0x03, 0x0E, 0x18, 0x40 },
1051: { 0x03, 0x0E, 0x18, 0x40 },
1052: { 0x03, 0x06, 0x18, 0x40 },
1053: { 0x03, 0x06, 0x18, 0x40 },
1054: { 0x03, 0x06, 0x18, 0x40 },
1055: { 0x03, 0x06, 0x18, 0x40 },
1056: { 0x03, 0x06, 0x18, 0x40 },
1057: { 0x03, 0x06, 0x18, 0x40 },
1058: { 0x03, 0x06, 0x18, 0x40 },
1059: { 0x03, 0x06, 0x18, 0x40 },
1060: { 0x03, 0x06, 0x18, 0x40 },
1061: { 0x03, 0x06, 0x18, 0x40 },
1062: { 0x03, 0x06, 0x18, 0x40 },
1063: { 0x03, 0x06, 0x18, 0x40 },
1064: { 0x03, 0x06, 0x18, 0x40 },
1065: { 0x03, 0x06, 0x18, 0x40 },
1066: { 0x03, 0x06, 0x18, 0x40 }
1067: };
1068:
1069: RLPS_EQUALIZER_RAM e1_rlps_ram_table[] =
1070: {
1071: { 0x07, 0xDE, 0x18, 0x2C },
1072: { 0x07, 0xDE, 0x18, 0x2C },
1073: { 0x07, 0xD6, 0x18, 0x2C },
1074: { 0x07, 0xD6, 0x18, 0x2C },
1075: { 0x07, 0xD6, 0x18, 0x2C },
1076: { 0x07, 0xCE, 0x18, 0x2C },
1077: { 0x07, 0xCE, 0x18, 0x2C },
1078: { 0x07, 0xCE, 0x18, 0x2C },
1079: { 0x07, 0xC6, 0x18, 0x2C },
1080: { 0x07, 0xC6, 0x18, 0x2C },
1081: { 0x07, 0xC6, 0x18, 0x2C },
1082: { 0x07, 0xBE, 0x18, 0x2C },
1083: { 0x07, 0xBE, 0x18, 0x2C },
1084: { 0x07, 0xBE, 0x18, 0x2C },
1085: { 0x07, 0xBE, 0x18, 0x2C },
1086: { 0x07, 0xBE, 0x18, 0x2C },
1087: { 0x07, 0xB6, 0x18, 0x2C },
1088: { 0x07, 0xB6, 0x18, 0x2C },
1089: { 0x07, 0xB6, 0x18, 0x2C },
1090: { 0x07, 0xB6, 0x18, 0x2C },
1091: { 0x07, 0xB6, 0x18, 0x2C },
1092: { 0x07, 0xAE, 0x18, 0x2C },
1093: { 0x07, 0xAE, 0x18, 0x2C },
1094: { 0x07, 0xAE, 0x18, 0x2C },
1095: { 0x07, 0xAE, 0x18, 0x2C },
1096: { 0x07, 0xAE, 0x18, 0x2C },
1097: { 0x07, 0xB6, 0x18, 0xAC },
1098: { 0x07, 0xAE, 0x18, 0xAC },
1099: { 0x07, 0xAE, 0x18, 0xAC },
1100: { 0x07, 0xAE, 0x18, 0xAC },
1101: { 0x07, 0xAE, 0x18, 0xAC },
1102: { 0x07, 0xA6, 0x18, 0xAC },
1103: { 0x07, 0xA6, 0x18, 0xAC },
1104: { 0x07, 0xA6, 0x18, 0xAC },
1105: { 0x07, 0xA6, 0x18, 0xAC },
1106: { 0x07, 0x9E, 0x18, 0xAC },
1107: { 0x07, 0xA6, 0x19, 0x2C },
1108: { 0x07, 0xA6, 0x19, 0x2C },
1109: { 0x07, 0xA6, 0x19, 0x2C },
1110: { 0x0F, 0xA6, 0x19, 0x2C },
1111: { 0x0F, 0xA6, 0x19, 0x2C },
1112: { 0x0F, 0x9E, 0x19, 0x2C },
1113: { 0x0F, 0x9E, 0x19, 0x2C },
1114: { 0x0F, 0x9E, 0x19, 0x2C },
1115: { 0x17, 0x9E, 0x19, 0x2C },
1116: { 0x17, 0xA6, 0x19, 0xAC },
1117: { 0x17, 0x9E, 0x19, 0xAC },
1118: { 0x17, 0x9E, 0x19, 0xAC },
1119: { 0x17, 0x96, 0x19, 0xAC },
1120: { 0x1F, 0x96, 0x19, 0xAC },
1121: { 0x1F, 0x96, 0x19, 0xAC },
1122: { 0x1F, 0x8E, 0x19, 0xAC },
1123: { 0x1F, 0x8E, 0x19, 0xAC },
1124: { 0x1F, 0x8E, 0x19, 0xAC },
1125: { 0x27, 0x8E, 0x19, 0xAC },
1126: { 0x27, 0x8E, 0x1A, 0x2C },
1127: { 0x27, 0x8E, 0x1A, 0x2C },
1128: { 0x27, 0x8E, 0x1A, 0x2C },
1129: { 0x27, 0x8E, 0x1A, 0x2C },
1130: { 0x2F, 0x86, 0x1A, 0x2C },
1131: { 0x2F, 0x86, 0x1A, 0x2C },
1132: { 0x2F, 0x86, 0x1A, 0x2C },
1133: { 0x2F, 0x7E, 0x1A, 0x2C },
1134: { 0x2F, 0x7E, 0x1A, 0x2C },
1135: { 0x2F, 0x7E, 0x1A, 0x2C },
1136: { 0x37, 0x7E, 0x1A, 0x2C },
1137: { 0x37, 0x7E, 0x1A, 0xAC },
1138: { 0x37, 0x7E, 0x1A, 0xAC },
1139: { 0x37, 0x7E, 0x1A, 0xAC },
1140: { 0x37, 0x7E, 0x1A, 0xAC },
1141: { 0x3F, 0x7E, 0x2A, 0xAC },
1142: { 0x3F, 0x7E, 0x2A, 0xAC },
1143: { 0x3F, 0x76, 0x2A, 0xAC },
1144: { 0x3F, 0x86, 0x2B, 0x2C },
1145: { 0x3F, 0x7E, 0x2B, 0x2C },
1146: { 0x47, 0x7E, 0x2B, 0x2C },
1147: { 0x47, 0x7E, 0x2F, 0x2C },
1148: { 0x47, 0x7E, 0x2F, 0x2C },
1149: { 0x47, 0x7E, 0x2F, 0x2C },
1150: { 0x47, 0x76, 0x2F, 0x2C },
1151: { 0x4F, 0x76, 0x2F, 0x2C },
1152: { 0x4F, 0x76, 0x2F, 0x2C },
1153: { 0x4F, 0x6E, 0x2F, 0x2C },
1154: { 0x4F, 0x6E, 0x2F, 0x2C },
1155: { 0x4F, 0x6E, 0x2F, 0x2C },
1156: { 0x57, 0x6E, 0x2F, 0x2C },
1157: { 0x57, 0x6E, 0x2F, 0x2C },
1158: { 0x57, 0x6E, 0x3F, 0x2C },
1159: { 0x57, 0x6E, 0x3F, 0x2C },
1160: { 0x57, 0x6E, 0x3F, 0x2C },
1161: { 0x5F, 0x6E, 0x3F, 0x2C },
1162: { 0x5F, 0x6E, 0x4F, 0x2C },
1163: { 0x5F, 0x6E, 0x4F, 0x2C },
1164: { 0x5F, 0x6E, 0x4F, 0x2C },
1165: { 0x5F, 0x66, 0x4F, 0x2C },
1166: { 0x67, 0x66, 0x4F, 0x2C },
1167: { 0x67, 0x66, 0x4F, 0x2C },
1168: { 0x67, 0x5E, 0x4F, 0x2C },
1169: { 0x67, 0x5E, 0x4F, 0x2C },
1170: { 0x67, 0x66, 0x4F, 0x2C },
1171: { 0x67, 0x66, 0x4F, 0x2C },
1172: { 0x67, 0x66, 0x5F, 0x2C },
1173: { 0x6F, 0x6E, 0x5F, 0x2C },
1174: { 0x6F, 0x6E, 0x6F, 0x2C },
1175: { 0x6F, 0x6E, 0x6F, 0x2C },
1176: { 0x6F, 0x6E, 0x7F, 0x2C },
1177: { 0x6F, 0x6E, 0x7F, 0x2C },
1178: { 0x6F, 0x6E, 0x7F, 0x2C },
1179: { 0x77, 0x66, 0x7F, 0x2C },
1180: { 0x77, 0x66, 0x7F, 0x2C },
1181: { 0x77, 0x5E, 0x6F, 0x2C },
1182: { 0x77, 0x5E, 0x7F, 0x2C },
1183: { 0x77, 0x5E, 0x7F, 0x2C },
1184: { 0x7F, 0x5E, 0x7F, 0x2C },
1185: { 0x7F, 0x5E, 0x8F, 0x2C },
1186: { 0x7F, 0x5E, 0x8F, 0x2C },
1187: { 0x7F, 0x5E, 0x8F, 0x2C },
1188: { 0x87, 0x56, 0x8F, 0x2C },
1189: { 0x87, 0x56, 0x8F, 0x2C },
1190: { 0x87, 0x56, 0x8F, 0x2C },
1191: { 0x87, 0x4E, 0x8F, 0x2C },
1192: { 0x87, 0x4E, 0x8F, 0x2C },
1193: { 0x87, 0x4E, 0x8F, 0x2C },
1194: { 0x8F, 0x4E, 0x9F, 0x2C },
1195: { 0x8F, 0x4E, 0x9F, 0x2C },
1196: { 0x8F, 0x4E, 0xAF, 0x2C },
1197: { 0x8F, 0x4E, 0xAF, 0x2C },
1198: { 0x8F, 0x4E, 0xAF, 0x2C },
1199: { 0x97, 0x4E, 0xAF, 0x2C },
1200: { 0x97, 0x4E, 0xAF, 0x2C },
1201: { 0x97, 0x4E, 0xAB, 0x2C },
1202: { 0x97, 0x4E, 0xAB, 0x2C },
1203: { 0x97, 0x4E, 0xAB, 0x2C },
1204: { 0x9F, 0x4E, 0xAB, 0x2C },
1205: { 0x9F, 0x4E, 0xBB, 0x2C },
1206: { 0x9F, 0x4E, 0xBB, 0x2C },
1207: { 0x9F, 0x4E, 0xBB, 0x2C },
1208: { 0x9F, 0x4E, 0xCB, 0x2C },
1209: { 0xA7, 0x4E, 0xCB, 0x2C },
1210: { 0xA7, 0x4E, 0xCB, 0x2C },
1211: { 0xA7, 0x46, 0xCB, 0x2C },
1212: { 0xA7, 0x46, 0xCB, 0x2C },
1213: { 0xA7, 0x46, 0xCB, 0x2C },
1214: { 0xA7, 0x46, 0xDB, 0x2C },
1215: { 0xAF, 0x46, 0xDB, 0x2C },
1216: { 0xAF, 0x46, 0xEB, 0x2C },
1217: { 0xAF, 0x46, 0xEB, 0x2C },
1218: { 0xAF, 0x4E, 0xEB, 0x2C },
1219: { 0xAE, 0x4E, 0xEB, 0x2C },
1220: { 0xAE, 0x4E, 0xEB, 0x2C },
1221: { 0xB5, 0x46, 0xFB, 0x2C },
1222: { 0xB5, 0x54, 0xFB, 0x2C },
1223: { 0xB5, 0x4C, 0xFB, 0x2C },
1224: { 0xB5, 0x54, 0xFB, 0x2C },
1225: { 0xB5, 0x54, 0xFB, 0x2C },
1226: { 0xBD, 0x54, 0xFB, 0x2C },
1227: { 0xBD, 0x4C, 0xFB, 0x2C },
1228: { 0xBD, 0x4C, 0xFB, 0x2C },
1229: { 0xBD, 0x4C, 0xFB, 0x2C },
1230: { 0xBD, 0x44, 0xEB, 0x2C },
1231: { 0xC5, 0x44, 0xFB, 0x2C },
1232: { 0xC5, 0x44, 0xFB, 0x2C },
1233: { 0xC5, 0x44, 0xFB, 0x2C },
1234: { 0xC5, 0x45, 0x0B, 0x2C },
1235: { 0xC5, 0x45, 0x0B, 0x2C },
1236: { 0xC5, 0x45, 0x0B, 0x2C },
1237: { 0xCD, 0x45, 0x0B, 0x2C },
1238: { 0xCD, 0x45, 0x0B, 0x2C },
1239: { 0xCD, 0x3D, 0x0B, 0x2C },
1240: { 0xCD, 0x3D, 0x0B, 0x2C },
1241: { 0xCD, 0x3D, 0x0B, 0x2C },
1242: { 0xD5, 0x3D, 0x0B, 0x2C },
1243: { 0xD5, 0x3D, 0x0B, 0x2C },
1244: { 0xD5, 0x3D, 0x1B, 0x2C },
1245: { 0xD5, 0x3D, 0x1B, 0x2C },
1246: { 0xD5, 0x3D, 0x1B, 0x2C },
1247: { 0xDD, 0x3D, 0x1B, 0x2C },
1248: { 0xDD, 0x3D, 0x1B, 0x2C },
1249: { 0xDD, 0x35, 0x1B, 0x2C },
1250: { 0xDD, 0x35, 0x1B, 0x2C },
1251: { 0xDD, 0x35, 0x1B, 0x2C },
1252: { 0xE5, 0x35, 0x1B, 0x2C },
1253: { 0xE5, 0x35, 0x1B, 0x2C },
1254: { 0xE5, 0x2D, 0x1B, 0x2C },
1255: { 0xE5, 0x2D, 0x1B, 0x2C },
1256: { 0xE5, 0x2D, 0x3B, 0x2C },
1257: { 0xED, 0x2D, 0x4B, 0x2C },
1258: { 0xED, 0x2D, 0x1B, 0xA8 },
1259: { 0xED, 0x2D, 0x1B, 0xAC },
1260: { 0xED, 0x2D, 0x17, 0xAC },
1261: { 0xED, 0x2D, 0x17, 0xAC },
1262: { 0xED, 0x2D, 0x27, 0xAC },
1263: { 0xF5, 0x2D, 0x27, 0xAC },
1264: { 0xF5, 0x2D, 0x27, 0xAC },
1265: { 0xF5, 0x2D, 0x2B, 0xAC },
1266: { 0xF5, 0x2D, 0x2B, 0xAC },
1267: { 0xF5, 0x2D, 0x2B, 0xAC },
1268: { 0xFD, 0x2D, 0x2B, 0xAC },
1269: { 0xFD, 0x2B, 0x2B, 0xAC },
1270: { 0xFD, 0x2B, 0x2B, 0xAC },
1271: { 0xFD, 0x2B, 0x2B, 0xAC },
1272: { 0xFD, 0x2B, 0x2B, 0xAC },
1273: { 0xFD, 0x23, 0x2B, 0xAC },
1274: { 0xFD, 0x23, 0x2B, 0xAC },
1275: { 0xFD, 0x23, 0x2B, 0xAC },
1276: { 0xFD, 0x21, 0x2B, 0xAC },
1277: { 0xFD, 0x21, 0x2B, 0xAC },
1278: { 0xFD, 0x29, 0x2B, 0xAC },
1279: { 0xFD, 0x29, 0x2B, 0xAC },
1280: { 0xFD, 0x29, 0x27, 0xAC },
1281: { 0xFD, 0x29, 0x37, 0xAC },
1282: { 0xFD, 0x29, 0x23, 0xAC },
1283: { 0xFD, 0x29, 0x23, 0xAC },
1284: { 0xFD, 0x29, 0x23, 0xAC },
1285: { 0xFD, 0x29, 0x23, 0xAC },
1286: { 0xFD, 0x21, 0x23, 0xAC },
1287: { 0xFD, 0x21, 0x23, 0xAC },
1288: { 0xFD, 0x21, 0x23, 0xAC },
1289: { 0xFD, 0x21, 0x33, 0xAC },
1290: { 0xFD, 0x21, 0x33, 0xAC },
1291: { 0xFD, 0x21, 0x33, 0xAC },
1292: { 0xFD, 0x21, 0x43, 0xAC },
1293: { 0xFD, 0x21, 0x43, 0xAC },
1294: { 0xFD, 0x21, 0x43, 0xAC },
1295: { 0xFC, 0x21, 0x43, 0xAC },
1296: { 0xFC, 0x21, 0x43, 0xAC },
1297: { 0xFC, 0x19, 0x43, 0xAC },
1298: { 0xFC, 0x19, 0x43, 0xAC },
1299: { 0xFC, 0x19, 0x43, 0xAC },
1300: { 0xFC, 0x19, 0x43, 0xAC },
1301: { 0xFC, 0x19, 0x53, 0xAC },
1302: { 0xFC, 0x19, 0x53, 0xAC },
1303: { 0xFC, 0x19, 0x53, 0xAC },
1304: { 0xFC, 0x19, 0x53, 0xAC },
1305: { 0xFC, 0x19, 0x63, 0xAC },
1306: { 0xFC, 0x19, 0x63, 0xAC },
1307: { 0xFC, 0x19, 0x63, 0xAC },
1308: { 0xFC, 0x19, 0x73, 0xAC },
1309: { 0xFC, 0x19, 0x73, 0xAC },
1310: { 0xFC, 0x19, 0x73, 0xAC },
1311: { 0xFC, 0x19, 0x73, 0xAC },
1312: { 0xFC, 0x19, 0x73, 0xAC },
1313: { 0xFC, 0x19, 0x83, 0xAC },
1314: { 0xFC, 0x19, 0x83, 0xAC },
1315: { 0xFC, 0x19, 0x83, 0xAC },
1316: { 0xFC, 0x19, 0x83, 0xAC },
1317: { 0xFC, 0x19, 0x83, 0xAC },
1318: { 0xFC, 0x19, 0x93, 0xAC },
1319: { 0xFC, 0x19, 0x93, 0xAC },
1320: { 0xFC, 0x19, 0x93, 0xAC },
1321: { 0xFC, 0x19, 0xA3, 0xAC },
1322: { 0xFC, 0x19, 0xA3, 0xAC },
1323: { 0xFC, 0x19, 0xB3, 0xAC },
1324: { 0xFC, 0x19, 0xB3, 0xAC },
1325: { 0xFC, 0x19, 0xB3, 0xAC },
1326: { 0xFC, 0x19, 0xB3, 0xAC }
1327: };
1328:
1329:
1330: static void ClearTemplate(sdla_t *);
1331: static unsigned char InitTemplate(sdla_t *);
1332: static void InitLineReceiver(sdla_t *);
1333:
1334: static void ClearTPSCReg(sdla_t *);
1335: static void ClearRPSCReg(sdla_t *);
1336:
1337: static int WriteTPSCReg(sdla_t *, int, int, unsigned char);
1338: static unsigned char ReadTPSCReg(sdla_t *, int, int);
1339:
1340: static int WriteRPSCReg(sdla_t *, int, int, unsigned char);
1341: static unsigned char ReadRPSCReg(sdla_t *, int, int);
1342:
1343: static void DisableAllChannels(sdla_t *);
1344: static void EnableAllChannels(sdla_t *);
1345: static int DisableTxChannel(sdla_t *, int);
1346: static int DisableRxChannel(sdla_t *, int);
1347: static int EnableTxChannel(sdla_t *, int);
1348: static int EnableRxChannel(sdla_t *, int);
1349:
1350: static void sdla_te_set_intr(sdla_t *);
1351: static void sdla_te_tx_intr(sdla_t *);
1352: static void sdla_te_rx_intr(sdla_t *);
1353: static void sdla_t1_rx_intr(sdla_t *);
1354: static void sdla_e1_rx_intr(sdla_t *);
1355:
1356: static void sdla_te_set_status(sdla_t *, unsigned long);
1357: static void sdla_te_enable_timer(sdla_t *, unsigned long);
1358:
1359: static int sdla_te_linelb(sdla_t *, unsigned char);
1360: static int sdla_te_paylb(sdla_t *, unsigned char);
1361: static int sdla_te_ddlb(sdla_t *, unsigned char);
1362: static int sdla_te_lb(sdla_t *, unsigned char);
1363:
1364:
1365: static void
1366: ClearTemplate(sdla_t *card)
1367: {
1368: int i = 0, j = 0;
1369: unsigned int indirect_addr = 0x00;
1370:
1371: for (i = FIRST_UI; i <= LAST_UI; i++) {
1372: for (j = FIRST_SAMPLE; j <= LAST_SAMPLE; j++) {
1373: indirect_addr = (j << 3) | i;
1374: /* Set up the indirect address */
1375: WRITE_REG(REG_XLPG_WAVEFORM_ADDR, indirect_addr);
1376: WRITE_REG(REG_XLPG_WAVEFORM_DATA, 0x00);
1377: }
1378: }
1379: }
1380:
1381: static unsigned char
1382: InitTemplate(sdla_t *card)
1383: {
1384: sdla_te_cfg_t* te_cfg = &card->fe_te.te_cfg;
1385: int i = 0, j = 0;
1386: unsigned char indirect_addr = 0x00, xlpg_scale = 0x00;
1387: TX_WAVEFORM* tx_waveform = NULL;
1388:
1389: if (IS_T1(&card->fe_te.te_cfg)) {
1390: switch (te_cfg->lbo) {
1391: case WAN_T1_LBO_0_DB:
1392: tx_waveform = &t1_tx_waveform_lh_0db;
1393: xlpg_scale = 0x0C;
1394: break;
1395: case WAN_T1_LBO_75_DB:
1396: tx_waveform = &t1_tx_waveform_lh_75db;
1397: xlpg_scale = 0x07;
1398: break;
1399: case WAN_T1_LBO_15_DB:
1400: tx_waveform = &t1_tx_waveform_lh_15db;
1401: xlpg_scale = 0x03;
1402: break;
1403: case WAN_T1_LBO_225_DB:
1404: tx_waveform = &t1_tx_waveform_lh_225db;
1405: xlpg_scale = 0x02;
1406: break;
1407: case WAN_T1_0_110:
1408: tx_waveform = &t1_tx_waveform_sh_110ft;
1409: xlpg_scale = 0x0C;
1410: break;
1411: case WAN_T1_110_220:
1412: tx_waveform = &t1_tx_waveform_sh_220ft;
1413: xlpg_scale = 0x10;
1414: break;
1415: case WAN_T1_220_330:
1416: tx_waveform = &t1_tx_waveform_sh_330ft;
1417: xlpg_scale = 0x11;
1418: break;
1419: case WAN_T1_330_440:
1420: tx_waveform = &t1_tx_waveform_sh_440ft;
1421: xlpg_scale = 0x12;
1422: break;
1423: case WAN_T1_440_550:
1424: tx_waveform = &t1_tx_waveform_sh_550ft;
1425: xlpg_scale = 0x14;
1426: break;
1427: case WAN_T1_550_660:
1428: tx_waveform = &t1_tx_waveform_sh_660ft;
1429: xlpg_scale = 0x15;
1430: break;
1431: default:
1432: /* Use 0DB as a default value */
1433: tx_waveform = &t1_tx_waveform_lh_0db;
1434: xlpg_scale = 0x0C;
1435: break;
1436: }
1437: } else {
1438: tx_waveform = &e1_tx_waveform_120;
1439: xlpg_scale = 0x0C;
1440: /*xlpg_scale = 0x0B; */
1441: }
1442:
1443: for (i = FIRST_UI; i <= LAST_UI; i++) {
1444: for (j = FIRST_SAMPLE; j <= LAST_SAMPLE; j++) {
1445: indirect_addr = (j << 3) | i;
1446: /* Set up the indirect address */
1447: WRITE_REG(REG_XLPG_WAVEFORM_ADDR, indirect_addr);
1448: WRITE_REG(REG_XLPG_WAVEFORM_DATA, (*tx_waveform)[j][i]);
1449: }
1450: }
1451: return xlpg_scale;
1452: }
1453:
1454:
1455: static void
1456: InitLineReceiver(sdla_t *card)
1457: {
1458: int ram_addr = 0x00;
1459: RLPS_EQUALIZER_RAM *rlps_ram_table = NULL;
1460:
1461: if (IS_E1(&card->fe_te.te_cfg)) {
1462: rlps_ram_table = e1_rlps_ram_table;
1463: } else {
1464: if (card->fe_te.te_cfg.high_impedance_mode == WAN_YES) {
1465: log(LOG_INFO, "%s: Setting to High-Impedance Mode!\n",
1466: card->devname);
1467: rlps_ram_table = t1_rlps_perf_mode_ram_table;
1468: } else {
1469: rlps_ram_table = t1_rlps_ram_table;
1470: }
1471: }
1472: for (ram_addr = 0; ram_addr <= 255; ram_addr++) {
1473: /* ERRATA VVV */
1474: /* Configure a write into the RAM address */
1475: WRITE_REG(REG_RLPS_EQ_RWB, BIT_RLPS_EQ_RWB);
1476: /* Initiate write into the specified RAM address */
1477: WRITE_REG(REG_RLPS_EQ_ADDR, (unsigned char)ram_addr);
1478: DELAY(100);
1479: /* ERRATA ^^^ */
1480: /* Write 1st value from conten column */
1481: WRITE_REG(REG_RLPS_IND_DATA_1, rlps_ram_table[ram_addr].byte1);
1482: /* Write 2st value from conten column */
1483: WRITE_REG(REG_RLPS_IND_DATA_2, rlps_ram_table[ram_addr].byte2);
1484: /* Write 3st value from conten column */
1485: WRITE_REG(REG_RLPS_IND_DATA_3, rlps_ram_table[ram_addr].byte3);
1486: /* Write 4st value from conten column */
1487: WRITE_REG(REG_RLPS_IND_DATA_4, rlps_ram_table[ram_addr].byte4);
1488: /* Configure a write into the RAM address */
1489: WRITE_REG(REG_RLPS_EQ_RWB, 0x00);
1490: /* Initiate write into the specified RAM address */
1491: WRITE_REG(REG_RLPS_EQ_ADDR, (unsigned char)ram_addr);
1492: /* ERRATA VVV */
1493: DELAY(100);
1494: /* ERRATA ^^^ */
1495: }
1496: }
1497:
1498: static void
1499: ClearTPSCReg(sdla_t *card)
1500: {
1501: int channel = 0;
1502: int start_channel = 0, stop_channel = 0;
1503:
1504: if (IS_E1(&card->fe_te.te_cfg)) {
1505: start_channel = 0;
1506: stop_channel = NUM_OF_E1_TIMESLOTS + 1;
1507: } else {
1508: start_channel = 1;
1509: stop_channel = NUM_OF_T1_CHANNELS;
1510: }
1511:
1512: for (channel = start_channel; channel <= stop_channel; channel++) {
1513: WRITE_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel, 0x00);
1514: WRITE_TPSC_REG(REG_TPSC_IDLE_CODE_BYTE, channel, 0x00);
1515: WRITE_TPSC_REG(REG_TPSC_SIGNALING_BYTE, channel, 0x00);
1516: }
1517: return;
1518: }
1519:
1520: static void
1521: ClearRPSCReg(sdla_t *card)
1522: {
1523: int channel = 0;
1524: int start_channel = 0, stop_channel = 0;
1525:
1526: if (IS_E1(&card->fe_te.te_cfg)) {
1527: start_channel = 0;
1528: stop_channel = NUM_OF_E1_TIMESLOTS + 1;
1529: } else {
1530: start_channel = 1;
1531: stop_channel = NUM_OF_T1_CHANNELS;
1532: }
1533:
1534: for (channel = start_channel; channel <= stop_channel; channel++) {
1535: WRITE_RPSC_REG(REG_RPSC_DATA_CTRL_BYTE, channel, 0x00);
1536: WRITE_RPSC_REG(REG_RPSC_DATA_COND_BYTE, channel, 0x00);
1537: WRITE_RPSC_REG(REG_RPSC_SIGNALING_BYTE, channel, 0x00);
1538: }
1539: return;
1540: }
1541:
1542: /*
1543: * Write value to TPSC indirect register.
1544: * Arguments: card - Pointer to the card structure
1545: * reg - Offset in TPSC indirect space.
1546: * channel - Channel number.
1547: * value - New PMC register value.
1548: * Returns: 0 - success, otherwise - error
1549: */
1550: static int
1551: WriteTPSCReg(sdla_t *card, int reg, int channel, unsigned char value)
1552: {
1553: unsigned char temp = 0x00;
1554: int i = 0, busy_flag = 0;
1555: int err = 0;
1556:
1557: reg += channel;
1558: /* Set IND bit to 1 in TPSC to enable indirect access to
1559: ** TPSC register */
1560: WRITE_REG(REG_TPSC_CFG, BIT_TPSC_IND);
1561: busy_flag = 1;
1562: for (i = 0; i < MAX_BUSY_READ; i++) {
1563: temp = READ_REG(REG_TPSC_MICRO_ACCESS_STATUS);
1564: if ((temp & BIT_TPSC_BUSY) == 0x0) {
1565: busy_flag = 0;
1566: break;
1567: }
1568: }
1569: if (busy_flag == 1) {
1570: log(LOG_INFO, "%s: Failed to write to TPSC Reg[%02x]<-%02x!\n",
1571: card->devname, reg, value);
1572: err = EBUSY;
1573: goto write_tpsc_done;
1574: }
1575:
1576: WRITE_REG(REG_TPSC_CHANNEL_INDIRECT_DATA_BUFFER,
1577: (unsigned char)value);
1578: WRITE_REG(REG_TPSC_CHANNEL_INDIRECT_ADDRESS_CONTROL,
1579: (unsigned char)(reg & 0x7F));
1580:
1581: for (i = 0; i < MAX_BUSY_READ; i++) {
1582: temp = READ_REG(REG_TPSC_MICRO_ACCESS_STATUS);
1583: if ((temp & BIT_TPSC_BUSY) == 0x0) {
1584: err = EBUSY;
1585: goto write_tpsc_done;
1586: }
1587: }
1588: log(LOG_INFO, "%s: Failed to write value to TPSC Reg=%02x, val=%02x.\n",
1589: card->devname, reg, value);
1590: write_tpsc_done:
1591: /* Set PCCE bit to 1 in TPSC to enable modifing the TPSC register */
1592: WRITE_REG(REG_TPSC_CFG, BIT_TPSC_IND | BIT_TPSC_PCCE);
1593: return err;
1594: }
1595:
1596: /*
1597: * Read value from TPSC indirect register.
1598: *
1599: * Arguments: card - Pointer to the card structure
1600: * reg - Offset in TPSC indirect space.
1601: * channel - Channel number.
1602: * Returns: Returns register value.
1603: */
1604: static unsigned char
1605: ReadTPSCReg(sdla_t *card, int reg, int channel)
1606: {
1607: unsigned char tmp = 0x00, value = 0x00;
1608: int i = 0, busy_flag = 0;
1609:
1610: reg += channel;
1611: /* Set IND bit to 1 in TPSC to enable indirect access to
1612: ** TPSC register */
1613: WRITE_REG(REG_TPSC_CFG, BIT_TPSC_IND);
1614: busy_flag = 1;
1615: for (i = 0; i < MAX_BUSY_READ; i++) {
1616: tmp = READ_REG(REG_TPSC_MICRO_ACCESS_STATUS);
1617: if ((tmp & BIT_TPSC_BUSY) == 0x0) {
1618: busy_flag = 0;
1619: break;
1620: }
1621: }
1622: if (busy_flag == 1) {
1623: log(LOG_INFO, "%s: Failed to read value to TPSC Reg=%02x!\n",
1624: card->devname, reg);
1625: goto read_tpsc_done;
1626: }
1627:
1628: WRITE_REG(REG_TPSC_CHANNEL_INDIRECT_ADDRESS_CONTROL,
1629: (unsigned char)(reg | 0x80));
1630:
1631: for (i = 0; i < MAX_BUSY_READ; i++) {
1632: tmp = READ_REG(REG_TPSC_MICRO_ACCESS_STATUS);
1633: if ((tmp & BIT_TPSC_BUSY) == 0x0) {
1634: value = READ_REG(REG_TPSC_CHANNEL_INDIRECT_DATA_BUFFER);
1635: goto read_tpsc_done;
1636: }
1637: }
1638: log(LOG_INFO, "%s: Failed to read value to TPSC Reg=%02x.\n",
1639: card->devname, reg);
1640: read_tpsc_done:
1641: /* Set PCCE bit to 1 in TPSC to enable modifing the TPSC register */
1642: WRITE_REG(REG_TPSC_CFG, BIT_TPSC_IND | BIT_TPSC_PCCE);
1643: return value;
1644: }
1645:
1646: /*
1647: * Write value to RPSC indirect register.
1648: *
1649: * Arguments: card - Pointer to the card structure
1650: * reg - Offset in RPSC indirect space.
1651: * channel - Channel number.
1652: * value - New PMC register value.
1653: * Returns: 0-success, otherwise - error
1654: */
1655: static int
1656: WriteRPSCReg(sdla_t* card, int reg, int channel, unsigned char value)
1657: {
1658: unsigned char temp = 0x00;
1659: int i = 0, busy_flag = 0;
1660: int err = 0;
1661:
1662: reg += channel;
1663: /* Set IND bit to 1 in RPSC to enable indirect access to
1664: ** RPSC register*/
1665: WRITE_REG(REG_RPSC_CFG, BIT_RPSC_IND);
1666: busy_flag = 1;
1667: for (i = 0; i < MAX_BUSY_READ; i++) {
1668: temp = READ_REG(REG_RPSC_MICRO_ACCESS_STATUS);
1669: if ((temp & BIT_RPSC_BUSY) == 0x0) {
1670: busy_flag = 0;
1671: break;
1672: }
1673: }
1674: if (busy_flag == 1) {
1675: log(LOG_INFO, "%s: Failed to write to RPSC Reg[%02x]<-%02x!\n",
1676: card->devname, reg, value);
1677: err = EBUSY;
1678: goto write_rpsc_done;
1679: }
1680:
1681: WRITE_REG(REG_RPSC_CHANNEL_INDIRECT_DATA_BUFFER, (unsigned char)value);
1682: WRITE_REG(REG_RPSC_CHANNEL_INDIRECT_ADDRESS_CONTROL,
1683: (unsigned char)(reg & 0x7F));
1684:
1685: for (i = 0; i < MAX_BUSY_READ; i++) {
1686: temp = READ_REG(REG_RPSC_MICRO_ACCESS_STATUS);
1687: if ((temp & BIT_RPSC_BUSY) == 0x0) {
1688: err = EBUSY;
1689: goto write_rpsc_done;
1690: }
1691: }
1692: log(LOG_INFO, "%s: Failed to write value to RPSC Reg=%02x, val=%02x.\n",
1693: card->devname, reg, value);
1694: write_rpsc_done:
1695: /* Set PCCE bit to 1 in RPSC to enable modifing the RPSC register */
1696: WRITE_REG(REG_RPSC_CFG, BIT_RPSC_IND | BIT_RPSC_PCCE);
1697: return err;
1698: }
1699:
1700: /*
1701: * Read value from RPSC indirect register.
1702: * Arguments: card - Pointer to the card structure
1703: * reg - Offset in RPSC indirect space.
1704: * channel - Channel number
1705: * Returns: Returns register value.
1706: */
1707: static unsigned char ReadRPSCReg(sdla_t* card, int reg, int channel)
1708: {
1709: unsigned char tmp = 0x00, value = 0x00;
1710: int i = 0,busy_flag = 0;
1711:
1712: reg += channel;
1713: /* Set IND bit to 1 in RPSC to enable indirect access to
1714: ** RPSC register*/
1715: WRITE_REG(REG_RPSC_CFG, BIT_RPSC_IND);
1716: busy_flag = 1;
1717: for (i = 0; i < MAX_BUSY_READ; i++) {
1718: tmp = READ_REG(REG_RPSC_MICRO_ACCESS_STATUS);
1719: if ((tmp & BIT_RPSC_BUSY) == 0x0) {
1720: busy_flag = 0;
1721: break;
1722: }
1723: }
1724: if (busy_flag == 1) {
1725: log(LOG_INFO, "%s: Failed to read value to RPSC Reg=%02x!\n",
1726: card->devname, reg);
1727: goto read_rpsc_done;
1728: }
1729:
1730: WRITE_REG(REG_RPSC_CHANNEL_INDIRECT_ADDRESS_CONTROL,
1731: (unsigned char)(reg | 0x80));
1732:
1733: for (i = 0; i < MAX_BUSY_READ; i++) {
1734: tmp = READ_REG(REG_RPSC_MICRO_ACCESS_STATUS);
1735: if ((tmp & BIT_RPSC_BUSY) == 0x0) {
1736: value = READ_REG(REG_RPSC_CHANNEL_INDIRECT_DATA_BUFFER);
1737: goto read_rpsc_done;
1738: }
1739: }
1740: log(LOG_INFO, "%s: Failed to read value to RPSC Reg=%02x.\n",
1741: card->devname, reg);
1742: read_rpsc_done:
1743: /* Set PCCE bit to 1 in RPSC to enable modifing the RPSC register */
1744: WRITE_REG(REG_RPSC_CFG, BIT_RPSC_IND | BIT_RPSC_PCCE);
1745: return value;
1746: }
1747:
1748:
1749: /*
1750: * Description: Disable All channels for RX/TX
1751: * Arguments: card - Pointer to the card structure.
1752: * Returns: none
1753: */
1754: static void DisableAllChannels(sdla_t* card)
1755: {
1756: int i = 0;
1757:
1758: if (IS_E1(&card->fe_te.te_cfg)) {
1759: DisableTxChannel(card, E1_FRAMING_TIMESLOT);
1760: DisableRxChannel(card, E1_FRAMING_TIMESLOT);
1761: for (i = 1; i <= NUM_OF_E1_TIMESLOTS; i++) {
1762: DisableTxChannel(card, i);
1763: DisableRxChannel(card, i);
1764: }
1765: } else {
1766: for (i = 1; i <= NUM_OF_T1_CHANNELS; i++) {
1767: DisableTxChannel(card, i);
1768: DisableRxChannel(card, i);
1769: }
1770: }
1771: }
1772:
1773: /*
1774: * Description: Enable All channels.
1775: * Arguments: card - Pointer to the card structure.
1776: * Returns: none
1777: */
1778: static void EnableAllChannels(sdla_t* card)
1779: {
1780: int i = 0;
1781:
1782: if (IS_E1(&card->fe_te.te_cfg)) {
1783: int first_ts =
1784: (card->fe_te.te_cfg.frame == WAN_FR_UNFRAMED) ?
1785: 0 : 1;
1786:
1787: DisableTxChannel(card, E1_FRAMING_TIMESLOT);
1788: DisableRxChannel(card, E1_FRAMING_TIMESLOT);
1789: for (i = first_ts; i <= NUM_OF_E1_TIMESLOTS; i++) {
1790: EnableTxChannel(card, i);
1791: EnableRxChannel(card, i);
1792: }
1793: } else {
1794: for (i = 1; i <= NUM_OF_T1_CHANNELS; i++) {
1795: EnableTxChannel(card, i);
1796: EnableRxChannel(card, i);
1797: }
1798: }
1799: }
1800:
1801: /*
1802: * Description: Enable Tx for specific channel
1803: * Arguments: card - pointer to the card structure
1804: * channel - channel number
1805: * Returns: 0-success, otherwise-error
1806: */
1807: static int EnableTxChannel(sdla_t* card, int channel)
1808: {
1809: sdla_te_cfg_t* te_cfg = &card->fe_te.te_cfg;
1810:
1811: if (te_cfg->lcode == WAN_LC_AMI) {
1812: /* ZCs=1 AMI*/
1813: WRITE_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel,
1814: (((READ_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel) &
1815: MASK_TPSC_DATA_CTRL_BYTE) &
1816: ~BIT_TPSC_DATA_CTRL_BYTE_IDLE_DS0) |
1817: BIT_TPSC_DATA_CTRL_BYTE_ZCS1));
1818: } else {
1819: WRITE_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel,
1820: ((READ_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel) &
1821: MASK_TPSC_DATA_CTRL_BYTE) &
1822: ~(BIT_TPSC_DATA_CTRL_BYTE_IDLE_DS0 |
1823: BIT_TPSC_DATA_CTRL_BYTE_ZCS1 |
1824: BIT_TPSC_DATA_CTRL_BYTE_ZCS0)));
1825: }
1826:
1827: if (IS_E1(&card->fe_te.te_cfg)) {
1828: /* Set SUBS=DS[0]=DS[1]=0x0 - no change to PCM timeslot data */
1829: WRITE_TPSC_REG(REG_TPSC_E1_CTRL_BYTE, channel,
1830: (READ_TPSC_REG(REG_TPSC_E1_CTRL_BYTE, channel) &
1831: ~(BIT_TPSC_E1_CTRL_BYTE_SUBS |
1832: BIT_TPSC_E1_CTRL_BYTE_DS0 |
1833: BIT_TPSC_E1_CTRL_BYTE_DS1)));
1834: } else {
1835: WRITE_TPSC_REG(REG_TPSC_SIGNALING_BYTE, channel, 0x00);
1836: }
1837:
1838: /* Erase contents of IDLE code byte */
1839: WRITE_TPSC_REG(REG_TPSC_IDLE_CODE_BYTE, channel, 0x00);
1840:
1841: return 0;
1842: }
1843: /*
1844: * Description: Enable Rx for specific channel
1845: * Arguments: card - pointer to the card structure
1846: * channel - channel number
1847: * Returns: 0-success, otherwise-error
1848: */
1849: static int EnableRxChannel(sdla_t* card, int channel)
1850: {
1851: /* Set DTRPC bit to 0 in RPSC */
1852: WRITE_RPSC_REG(REG_RPSC_DATA_CTRL_BYTE, channel,
1853: ((READ_RPSC_REG(REG_RPSC_DATA_CTRL_BYTE, channel) &
1854: MASK_RPSC_DATA_CTRL_BYTE) &
1855: ~BIT_RPSC_DATA_CTRL_BYTE_DTRKC));
1856: return 0;
1857: }
1858:
1859: /*
1860: * Description: Disable Tx for specific channel
1861: * Arguments: card - pointer to the card structure
1862: * channel - channel number
1863: * Returns: 0-success, otherwise-error
1864: */
1865: static int DisableTxChannel(sdla_t* card, int channel)
1866: {
1867: /* Set IDLE_DS0 to 1 for an IDLE code byte will insert and
1868: * BTCLK will suppressed
1869: */
1870: WRITE_TPSC_REG(REG_RPSC_DATA_CTRL_BYTE, channel,
1871: ((READ_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel) &
1872: MASK_TPSC_DATA_CTRL_BYTE) | BIT_TPSC_DATA_CTRL_BYTE_IDLE_DS0));
1873: if (IS_E1(&card->fe_te.te_cfg)) {
1874: /* Set SUBS=1, DS0=0 - data substitution on - IDLE code
1875: ** replaces BTPCM timeslot data */
1876: WRITE_TPSC_REG(REG_TPSC_E1_CTRL_BYTE, channel,
1877: ((READ_TPSC_REG(REG_TPSC_E1_CTRL_BYTE, channel) &
1878: ~BIT_TPSC_E1_CTRL_BYTE_DS0) | BIT_TPSC_E1_CTRL_BYTE_SUBS));
1879: } else {
1880: WRITE_TPSC_REG(REG_TPSC_SIGNALING_BYTE, channel, 0x00);
1881: }
1882: /* Erase contents of IDLE code byte */
1883: WRITE_TPSC_REG(REG_TPSC_IDLE_CODE_BYTE, channel, 0x55);
1884: return 0;
1885: }
1886:
1887: /*
1888: * Description: Disable Rx for specific channel
1889: * Arguments: card - pointer to the card structure
1890: * channel - channel number
1891: * Returns: 0-success, otherwise-error
1892: */
1893: static int DisableRxChannel(sdla_t* card, int channel)
1894: {
1895: /* Set DTRPC bit to 1 in RPSC to hold low for the duration of
1896: ** the channel */
1897: WRITE_RPSC_REG(REG_RPSC_DATA_CTRL_BYTE, channel,
1898: ((READ_RPSC_REG(REG_RPSC_DATA_CTRL_BYTE, channel) &
1899: MASK_RPSC_DATA_CTRL_BYTE) | BIT_RPSC_DATA_CTRL_BYTE_DTRKC));
1900: return 0;
1901: }
1902:
1903: /*
1904: * Set default T1 configuration
1905: */
1906: int
1907: sdla_te_defcfg(void *pte_cfg)
1908: {
1909: sdla_te_cfg_t *te_cfg = (sdla_te_cfg_t*)pte_cfg;
1910:
1911: te_cfg->media = WAN_MEDIA_T1;
1912: te_cfg->lcode = WAN_LC_B8ZS;
1913: te_cfg->frame = WAN_FR_ESF;
1914: te_cfg->lbo = WAN_T1_LBO_0_DB;
1915: te_cfg->te_clock = WAN_NORMAL_CLK;
1916: te_cfg->active_ch = ENABLE_ALL_CHANNELS;
1917: te_cfg->high_impedance_mode = WAN_NO;
1918: return 0;
1919: }
1920:
1921:
1922: int
1923: sdla_te_setcfg(struct ifnet *ifp, struct ifmedia *ifm)
1924: {
1925: struct ifreq ifr;
1926: struct if_settings ifs;
1927:
1928: wanpipe_common_t *common = (wanpipe_common_t *)ifp->if_softc;
1929: sdla_t *card = (sdla_t*)common->card;
1930: sdla_te_cfg_t *te_cfg = (sdla_te_cfg_t*)&card->fe_te.te_cfg;
1931: int ret;
1932:
1933: if (IFM_TYPE(ifm->ifm_media) != IFM_TDM)
1934: return (EINVAL);
1935:
1936: bcopy(ifp->if_xname, ifr.ifr_name, sizeof(ifr.ifr_name));
1937: bzero(&ifs, sizeof(ifs));
1938: ifr.ifr_data = (caddr_t) &ifs;
1939:
1940: if ((ifm->ifm_media & IFM_OMASK) == IFM_TDM_PPP)
1941: ifs.type = IF_PROTO_PPP;
1942: else if ((ifm->ifm_media & IFM_OMASK) == 0)
1943: ifs.type = IF_PROTO_CISCO;
1944: else {
1945: log(LOG_INFO, "%s: Unsupported ifmedia options\n",
1946: card->devname);
1947: return (EINVAL);
1948: }
1949:
1950: ret = wp_lite_set_proto(ifp, &ifr);
1951: if (ret != 0)
1952: return (ret);
1953:
1954: switch (IFM_SUBTYPE(ifm->ifm_media)) {
1955: case IFM_TDM_T1:
1956: #ifdef DEBUG_INIT
1957: log(LOG_INFO, "%s: Setting T1 media type!\n",
1958: card->devname);
1959: #endif /* DEBUG_INIT */
1960: te_cfg->media = WAN_MEDIA_T1;
1961: te_cfg->lcode = WAN_LC_B8ZS;
1962: te_cfg->frame = WAN_FR_ESF;
1963: break;
1964: case IFM_TDM_T1_AMI:
1965: #ifdef DEBUG_INIT
1966: log(LOG_INFO, "%s: Setting T1 AMI media type!\n",
1967: card->devname);
1968: #endif /* DEBUG_INIT */
1969: te_cfg->media = WAN_MEDIA_T1;
1970: te_cfg->lcode = WAN_LC_AMI;
1971: te_cfg->frame = WAN_FR_ESF;
1972: break;
1973: case IFM_TDM_E1:
1974: #ifdef DEBUG_INIT
1975: log(LOG_INFO, "%s: Setting E1 media type!\n",
1976: card->devname);
1977: #endif /* DEBUG_INIT */
1978: te_cfg->media = WAN_MEDIA_E1;
1979: te_cfg->lcode = WAN_LC_HDB3;
1980: te_cfg->frame = WAN_FR_NCRC4;
1981: break;
1982: case IFM_TDM_E1_AMI:
1983: #ifdef DEBUG_INIT
1984: log(LOG_INFO, "%s: Setting E1 AMI media type!\n",
1985: card->devname);
1986: #endif /* DEBUG_INIT */
1987: te_cfg->media = WAN_MEDIA_E1;
1988: te_cfg->lcode = WAN_LC_AMI;
1989: te_cfg->frame = WAN_FR_NCRC4;
1990: break;
1991: default:
1992: log(LOG_INFO, "%s: Unsupported ifmedia type (%04X)\n",
1993: card->devname, ifm->ifm_media);
1994: return (EINVAL);
1995: }
1996:
1997: return (0);
1998: }
1999:
2000: /*
2001: * Set timeslot map
2002: */
2003: void
2004: sdla_te_settimeslot(void* pcard, unsigned long ts_map)
2005: {
2006: sdla_t *card = (sdla_t*)pcard;
2007:
2008: #ifdef DEBUG_INIT
2009: log(LOG_INFO, "%s: Setting timeslot map to %08lX\n",
2010: card->devname, ts_map);
2011: #endif /* DEBUG_INIT */
2012: if (IS_T1(&card->fe_te.te_cfg)) {
2013: /* For T1, Shift timeslot map left by 1, because bit 0
2014: ** is not been used by T1 timeslot map (bit 1 is used for
2015: ** channel 1, bit 2 is used for channel 2 and so on). */
2016: ts_map = ts_map >> 1;
2017: }
2018: card->fe_te.te_cfg.active_ch = ts_map;
2019: return;
2020: }
2021:
2022: unsigned long
2023: sdla_te_gettimeslot(void* pcard)
2024: {
2025: sdla_t *card = (sdla_t*)pcard;
2026: unsigned long ts_map = card->fe_te.te_cfg.active_ch;
2027:
2028: if (IS_T1(&card->fe_te.te_cfg)) {
2029: /* See explaination before. */
2030: ts_map = ts_map << 1;
2031: }
2032: return ts_map;
2033: }
2034:
2035: /*
2036: * Configure Sangoma TE1 board
2037: *
2038: * Arguments:
2039: * Returns: 0 - TE1 configred successfully, otherwise EINVAL.
2040: */
2041: short
2042: sdla_te_config(void* card_id)
2043: {
2044: sdla_t *card = (sdla_t*)card_id;
2045: sdla_te_cfg_t *te_cfg = &card->fe_te.te_cfg;
2046: u_int16_t adapter_type;
2047: unsigned char value = 0x00, xlpg_scale = 0x00;
2048: int channel_range = (IS_T1(&card->fe_te.te_cfg)) ?
2049: NUM_OF_T1_CHANNELS : NUM_OF_E1_TIMESLOTS;
2050: int i = 0;
2051:
2052: WAN_ASSERT(card == NULL);
2053: WAN_ASSERT(card->write_front_end_reg == NULL);
2054: WAN_ASSERT(card->read_front_end_reg == NULL);
2055: sdla_getcfg(card->hw, SDLA_ADAPTERTYPE, &adapter_type);
2056:
2057: #ifdef DEBUG_INIT
2058: log(LOG_INFO, "%s: Setting %s configuration!\n",
2059: card->devname,
2060: IS_T1(&card->fe_te.te_cfg) ? "T1" : "E1");
2061: if (IS_T1(&card->fe_te.te_cfg)) {
2062: log(LOG_DEBUG, "%s: Line decoding %s\n",
2063: card->devname,
2064: (te_cfg->lcode == WAN_LC_AMI) ? "AMI" : "B8ZS");
2065: log(LOG_DEBUG, "%s: Frame type %s\n",
2066: card->devname,
2067: (te_cfg->frame == WAN_FR_ESF) ? "ESF" :
2068: (te_cfg->frame == WAN_FR_D4) ? "D4" : "Unframed");
2069: switch (te_cfg->lbo) {
2070: case WAN_T1_LBO_0_DB:
2071: log(LOG_DEBUG, "%s: LBO 0 dB\n", card->devname);
2072: break;
2073: case WAN_T1_LBO_75_DB:
2074: log(LOG_DEBUG, "%s: LBO 7.5 dB\n", card->devname);
2075: break;
2076: case WAN_T1_LBO_15_DB:
2077: log(LOG_DEBUG, "%s: LBO 15 dB\n", card->devname);
2078: break;
2079: case WAN_T1_LBO_225_DB:
2080: log(LOG_DEBUG, "%s: LBO 22.5 dB\n", card->devname);
2081: break;
2082: case WAN_T1_0_110:
2083: log(LOG_DEBUG, "%s: LBO 0-110 ft.\n", card->devname);
2084: break;
2085: case WAN_T1_110_220:
2086: log(LOG_DEBUG, "%s: LBO 110-220 ft.\n", card->devname);
2087: break;
2088: case WAN_T1_220_330:
2089: log(LOG_DEBUG, "%s: LBO 220-330 ft.\n", card->devname);
2090: break;
2091: case WAN_T1_330_440:
2092: log(LOG_DEBUG, "%s: LBO 330-440 ft.\n", card->devname);
2093: break;
2094: case WAN_T1_440_550:
2095: log(LOG_DEBUG, "%s: LBO 440-550 ft.\n", card->devname);
2096: break;
2097: case WAN_T1_550_660:
2098: log(LOG_DEBUG, "%s: LBO 550-660 ft.\n",
2099: card->devname);
2100: break;
2101: }
2102: } else {
2103: log(LOG_DEBUG, "%s: Line decoding %s\n", card->devname,
2104: (te_cfg->lcode == WAN_LC_AMI) ? "AMI" : "HDB3");
2105: log(LOG_DEBUG, "%s: Frame type %s\n", card->devname,
2106: (te_cfg->frame == WAN_FR_CRC4) ? "CRC4" :
2107: (te_cfg->frame == WAN_FR_NCRC4) ? "non-CRC3" :
2108: "Unframed");
2109: }
2110: log(LOG_DEBUG, "%s: Clock mode %s\n", card->devname,
2111: (te_cfg->te_clock == WAN_NORMAL_CLK) ? "Normal" : "Master");
2112: #endif /* DEBUG_INIT */
2113:
2114: /* 1. Initiate software reset of the COMET */
2115: /* Set RESET=1 to place COMET into RESET */
2116: WRITE_REG(REG_RESET, BIT_RESET);
2117:
2118: /* Set RESET=0, disable software reset. COMET in default mode. */
2119: WRITE_REG(REG_RESET, 0x0/*~BIT_RESET*/);
2120:
2121: /* 2.Setup the XLPG(Transmit pulse template) to clear the pulse
2122: ** template */
2123: ClearTemplate(card);
2124: xlpg_scale = InitTemplate(card);
2125:
2126: /* Program PMC for T1/E1 mode (Reg 0x00) */
2127: if (IS_E1(&card->fe_te.te_cfg)) {
2128: if (adapter_type & A101_ADPTR_T1E1_MASK) {
2129: WRITE_REG(REG_GLOBAL_CFG,
2130: BIT_GLOBAL_TRKEN | BIT_GLOBAL_PIO_OE |
2131: BIT_GLOBAL_E1);
2132: } else {
2133: WRITE_REG(REG_GLOBAL_CFG,
2134: BIT_GLOBAL_PIO_OE | BIT_GLOBAL_E1);
2135: }
2136: } else {
2137: if (adapter_type & A101_ADPTR_T1E1_MASK) {
2138: WRITE_REG(REG_GLOBAL_CFG,
2139: BIT_GLOBAL_TRKEN | BIT_GLOBAL_PIO_OE);
2140: }
2141: }
2142:
2143: /* Set SCALE[4-0] value in XLPG Line driver Configuration (Reg. 0xF0) */
2144: WRITE_REG(REG_XLPG_LINE_CFG, xlpg_scale);
2145:
2146: /* Set system clock and XCLK (Reg 0xD6) */
2147: if (IS_T1(&card->fe_te.te_cfg)) {
2148: WRITE_REG(REG_CSU_CFG, BIT_CSU_MODE0);
2149: /*WRITE_REG(REG_CSU_CFG,
2150: ** BIT_CSU_MODE2 | BIT_CSU_MODE1 | BIT_CSU_MODE0); */
2151: } else {
2152: WRITE_REG(REG_CSU_CFG, 0x00);
2153: }
2154:
2155: /* Set Line decoding (Reg. 0x10) */
2156: if (te_cfg->lcode == WAN_LC_AMI) {
2157: WRITE_REG(REG_CDRC_CFG, BIT_CDRC_CFG_AMI);
2158: } else {
2159: WRITE_REG(REG_CDRC_CFG, 0x00);
2160: }
2161:
2162: /* Program the RX-ELST/TX-ELST for the appropriate mode
2163: ** (Reg 0x1C, 0x20)*/
2164: if (IS_E1(&card->fe_te.te_cfg)) {
2165: WRITE_REG(REG_RX_ELST_CFG, BIT_RX_ELST_IR | BIT_RX_ELST_OR);
2166: WRITE_REG(REG_TX_ELST_CFG, BIT_TX_ELST_IR | BIT_RX_ELST_OR);
2167: } else {
2168: WRITE_REG(REG_RX_ELST_CFG, 0x00);
2169: WRITE_REG(REG_TX_ELST_CFG, 0x00);
2170: }
2171:
2172: value = 0x00;
2173: if (IS_E1(&card->fe_te.te_cfg)) {
2174: /* Program the trasmitter framing and line decoding
2175: ** (Reg. 0x80) */
2176: if (te_cfg->lcode == WAN_LC_AMI) {
2177: value |= BIT_E1_TRAN_AMI;
2178: }
2179: if (te_cfg->frame == WAN_FR_CRC4) {
2180: value |= BIT_E1_TRAN_GENCRC;
2181: } else if (te_cfg->frame == WAN_FR_UNFRAMED) {
2182: value |= BIT_E1_TRAN_FDIS;
2183: }
2184: /* E1 TRAN Configuration (Reg 0x80) */
2185: WRITE_REG(REG_E1_TRAN_CFG, value);
2186: /* Configure the receive framer (Reg 0x90) */
2187: value = 0x00;
2188: if (te_cfg->frame == WAN_FR_CRC4) {
2189: value |=
2190: (BIT_E1_FRMR_CRCEN |
2191: BIT_E1_FRMR_CASDIS |
2192: BIT_E1_FRMR_REFCRCEN);
2193: } else if (te_cfg->frame == WAN_FR_NCRC4) {
2194: value |= BIT_E1_FRMR_CASDIS;
2195: }
2196: WRITE_REG(REG_E1_FRMR_CFG, value);
2197: } else {
2198: /* Set framing format & line decoding for transmitter
2199: ** (Reg 0x54) */
2200: if (te_cfg->lcode == WAN_LC_B8ZS) {
2201: value |= BIT_T1_XBAS_B8ZS;
2202: } else {
2203: value |= BIT_T1_XBAS_ZCS0;
2204: }
2205: if (te_cfg->frame == WAN_FR_ESF) {
2206: value |= BIT_T1_XBAS_ESF;
2207: }
2208: WRITE_REG(REG_T1_XBAS_CFG, value);
2209:
2210: /* Program framing format for receiving (Reg. 0x48) */
2211: value = 0x00;
2212: if (te_cfg->frame == WAN_FR_ESF) {
2213: value = BIT_T1_FRMR_ESF | BIT_T1_FRMR_ESFFA;
2214: }
2215: WRITE_REG(REG_T1_FRMR_CFG, value);
2216:
2217: /* Program the transmitter framing format and line deconding
2218: ** (Reg. 0x60) */
2219: value = 0x00;
2220: if (te_cfg->frame == WAN_FR_ESF) {
2221: value = BIT_T1_ALMI_CFG_ESF;
2222: }
2223: WRITE_REG(REG_T1_ALMI_CFG, value);
2224: }
2225:
2226: /* Configure the SIGX configuration register */
2227: if (IS_E1(&card->fe_te.te_cfg)) {
2228: WRITE_REG(REG_SIGX_CFG, 0x00);
2229: } else {
2230: value = READ_REG(REG_SIGX_CFG);
2231: if (te_cfg->frame == WAN_FR_ESF) {
2232: value |= BIT_SIGX_ESF;
2233: }
2234: WRITE_REG(REG_SIGX_CFG, value);
2235: }
2236: /* Program the BTIF for the frame pulse mode */
2237: value = 0x00;
2238: if (IS_E1(&card->fe_te.te_cfg)) {
2239: value |= BIT_BTIF_RATE0;
2240: }
2241: if (te_cfg->lcode == WAN_LC_AMI) {
2242: value |= BIT_BTIF_NXDS0_0;
2243: } else if (te_cfg->frame != WAN_FR_UNFRAMED) {
2244: value |= BIT_BTIF_NXDS0_1;
2245: }
2246:
2247: if (adapter_type & A101_ADPTR_T1E1_MASK) {
2248: value |= (BIT_BTIF_CMODE | BIT_BTIF_DE | BIT_BTIF_FE);
2249: }
2250: WRITE_REG(REG_BTIF_CFG, value);
2251: /* Set the type of frame pulse on the backplane */
2252: value = 0x00;
2253:
2254: if (adapter_type & A101_ADPTR_T1E1_MASK) {
2255: value = BIT_BTIF_FPMODE;
2256: }
2257: WRITE_REG(REG_BTIF_FR_PULSE_CFG, value);
2258:
2259: /* Program the BRIF for the frame pulse mode */
2260: value = 0x00;
2261: if (IS_E1(&card->fe_te.te_cfg)) {
2262: value |= BIT_BRIF_RATE0;
2263: }
2264: if (te_cfg->lcode == WAN_LC_AMI) {
2265: value |= BIT_BRIF_NXDS0_0;
2266: } else if (te_cfg->frame != WAN_FR_UNFRAMED) {
2267: value |= BIT_BRIF_NXDS0_1;
2268: }
2269: if (adapter_type & A101_ADPTR_T1E1_MASK) {
2270: value |= BIT_BRIF_CMODE;
2271: }
2272: WRITE_REG(REG_BRIF_CFG, value);
2273: /* Set the type of frame pulse on the backplane */
2274: value = 0x00;
2275:
2276: if (adapter_type & A101_ADPTR_T1E1_MASK) {
2277: value = BIT_BRIF_FPMODE;
2278: }
2279: WRITE_REG(REG_BRIF_FR_PULSE_CFG, value);
2280: /* Program the data integraty checking on the BRIF */
2281: WRITE_REG(REG_BRIF_DATA_CFG, BIT_BRIF_DATA_TRI_0);
2282:
2283: /* Set TJAT FIFO output clock signal (Reg 0x06) */
2284: if (te_cfg->te_clock == WAN_NORMAL_CLK) {
2285: WRITE_REG(REG_TX_TIMING_OPT, BIT_TX_PLLREF1 | BIT_TX_TXELSTBYP);
2286: } else {
2287: WRITE_REG(REG_TX_TIMING_OPT,
2288: BIT_TX_PLLREF1 | BIT_TX_PLLREF0 | BIT_TX_TXELSTBYP);
2289: }
2290:
2291: /* Set long or short and enable the equalizer (Reg 0xF8) */
2292: WRITE_REG(REG_RLPS_CFG_STATUS, BIT_RLPS_CFG_STATUS_LONGE);
2293:
2294: /* Select ALOS Detection and Clearance Thresholds (Reg 0xF9) */
2295: /* NC: Aug 20 2003:
2296: * Set the correct ALSO Detection/Clearance tresholds
2297: * for T1/E1 lines, to get rid of false ALOS alarms.
2298: *
2299: * Original incorrect value set was 0x00, for both T1/E1 */
2300: if (IS_E1(&card->fe_te.te_cfg)) {
2301: WRITE_REG(REG_RLPS_ALOS_DET_CLR_THR,
2302: BIT_RLPS_ALOS_DET_THR_2|
2303: BIT_RLPS_ALOS_DET_THR_1|
2304: BIT_RLPS_ALOS_DET_THR_0);
2305: } else {
2306: WRITE_REG(REG_RLPS_ALOS_DET_CLR_THR,
2307: BIT_RLPS_ALOS_CLR_THR_2|
2308: BIT_RLPS_ALOS_CLR_THR_0|
2309: BIT_RLPS_ALOS_DET_THR_2|
2310: BIT_RLPS_ALOS_DET_THR_0);
2311: }
2312:
2313: /* Select ALOS Detection period to set the ALOS alarm (Reg 0xFA) */
2314: WRITE_REG(REG_RLPS_ALOS_DET_PER, REG_RLPS_ALOS_DET_PER_0);
2315: /* Select ALOS Clearance period to clear the ALOS alarm (Reg 0xFB) */
2316: WRITE_REG(REG_RLPS_ALOS_CLR_PER, BIT_RLPS_ALOS_CLR_PER_0);
2317: /* Program to 0x00 to initiate a microprocessor access to RAM
2318: ** (Reg 0xFC) */
2319: /* ERRATA WRITE_REG(REG_RLPS_EQ_ADDR, 0x00); */
2320: /* Write the value 0x80 to this register to select a write to the RAM
2321: ** (Reg 0xFD) */
2322: /* ERRATA WRITE_REG(REG_RLPS_EQ_RWB, BIT_RLPS_EQ_RWB); */
2323: /* Program this register to 0x00 to reset the pointer to the RAM
2324: ** (Reg 0xFE) */
2325: WRITE_REG(REG_RLPS_EQ_STATUS, 0x00);
2326: /* Configure the Recive line Equalizer (Reg 0xFF) */
2327: WRITE_REG(REG_RLPS_EQ_CFG,
2328: BIT_RLPS_EQ_RESERVED | BIT_RLPS_EQ_FREQ_1 | BIT_RLPS_EQ_FREQ_0);
2329:
2330: /* Configure the TJAT FIFO (Reg 0x1B) */
2331: WRITE_REG(REG_TJAT_CFG, BIT_TJAT_CENT);
2332:
2333: /* Configure the RJAT FIFO (Reg 0x17) */
2334: WRITE_REG(REG_RJAT_CFG, BIT_RJAT_CENT);
2335: /* Program Receive Options (Reg 0x02) */
2336: if (te_cfg->frame == WAN_FR_UNFRAMED) {
2337: WRITE_REG(REG_RECEIVE_OPT, BIT_RECEIVE_OPT_UNF);
2338: } else {
2339: WRITE_REG(REG_RECEIVE_OPT, 0x00);
2340: }
2341:
2342: /* Configure XLPG Analog Test Positive control (Reg 0xF4) */
2343: WRITE_REG(REG_XLPG_TPC, BIT_XLPG_TPC_0);
2344: /* Configure XLPG Analog Test Negative control (Reg 0xF5) */
2345: WRITE_REG(REG_XLPG_TNC, BIT_XLPG_TNC_0);
2346:
2347: /* Program the RLPS Equalizer Voltage (Reg 0xDC) */
2348: if (IS_E1(&card->fe_te.te_cfg)) {
2349: WRITE_REG(REG_EQ_VREF, 0x34);
2350: } else {
2351: WRITE_REG(REG_EQ_VREF, 0x2C);
2352: }
2353: WRITE_REG(REG_RLPS_FUSE_CTRL_STAT, 0x00);
2354:
2355: /* ERRATA WRITE_REG(REG_RLPS_FUSE_CTRL_STAT, 0x00);*/
2356: /* ERRAT VVV */
2357: WRITE_REG(0xF4, 0x01);
2358: WRITE_REG(0xF4, 0x01);
2359: value = READ_REG(0xF4) & 0xFE;
2360: WRITE_REG(0xF4, value);
2361:
2362: WRITE_REG(0xF5, 0x01);
2363: WRITE_REG(0xF5, 0x01);
2364: value = READ_REG(0xF5) & 0xFE;
2365: WRITE_REG(0xF5, value);
2366:
2367: WRITE_REG(0xF6, 0x01);
2368: /* ERRATA ^^^ */
2369:
2370: InitLineReceiver(card);
2371:
2372: ClearRPSCReg(card);
2373: ClearTPSCReg(card);
2374:
2375:
2376: DisableAllChannels(card);
2377: if (te_cfg->active_ch == ENABLE_ALL_CHANNELS) {
2378: #ifdef DEBUG_INIT
2379: log(LOG_DEBUG, "%s: All channels enabled\n", card->devname);
2380: #endif /* DEBUG_INIT */
2381: EnableAllChannels(card);
2382: } else {
2383: for (i = 1; i <= channel_range; i++) {
2384: if (te_cfg->active_ch & (1 << (i-1))) {
2385: #ifdef DEBUG_INIT
2386: log(LOG_DEBUG, "%s: Enable channel %d\n",
2387: card->devname, i);
2388: #endif /* DEBUG_INIT */
2389: EnableTxChannel(card, i);
2390: EnableRxChannel(card, i);
2391: }
2392: }
2393: }
2394:
2395: /* Initialize and start T1/E1 timer */
2396: card->fe_te.te_timer_cmd = TE_SET_INTR;
2397: bit_clear((u_int8_t*)&card->fe_te.te_critical,TE_TIMER_KILL);
2398: timeout_set(&card->fe_te.te_timer, sdla_te_timer, (void*)card);
2399: sdla_te_enable_timer(card, INTR_TE1_TIMER);
2400:
2401: bit_set((u_int8_t*)&card->fe_te.te_critical, TE_CONFIGURED);
2402:
2403: return 0;
2404: }
2405:
2406: /*
2407: * Enable T1/E1 interrupts.
2408: */
2409: static void
2410: sdla_te_set_intr(sdla_t* card)
2411: {
2412:
2413: /* Enable LOS interrupt */
2414: /* WRITE_REG(REG_CDRC_INT_EN, BIT_CDRC_INT_EN_LOSE);*/
2415: /* Enable ALOS interrupt */
2416: WRITE_REG(REG_RLPS_CFG_STATUS,
2417: READ_REG(REG_RLPS_CFG_STATUS) | BIT_RLPS_CFG_STATUS_ALOSE);
2418: if (IS_T1(&card->fe_te.te_cfg)) {
2419: /* Enable RBOC interrupt */
2420: WRITE_REG(REG_T1_RBOC_ENABLE,
2421: BIT_T1_RBOC_ENABLE_IDLE |
2422: BIT_T1_RBOC_ENABLE_BOCE);
2423: /* Enable interrupt on RED, AIS, YEL alarms */
2424: WRITE_REG(REG_T1_ALMI_INT_EN,
2425: BIT_T1_ALMI_INT_EN_REDE |
2426: BIT_T1_ALMI_INT_EN_AISE |
2427: BIT_T1_ALMI_INT_EN_YELE);
2428: /* Enable interrupt on OOF alarm */
2429: /*WRITE_REG(REG_T1_FRMR_INT_EN, BIT_T1_FRMR_INT_EN_INFRE);*/
2430: } else {
2431: /* Enable interrupt on RED, AIS alarms */
2432: WRITE_REG(REG_E1_FRMR_M_A_INT_EN,
2433: BIT_E1_FRMR_M_A_INT_EN_REDE |
2434: BIT_E1_FRMR_M_A_INT_EN_AISE);
2435: /* Enable OOF Interrupt */
2436: /*WRITE_REG(REG_E1_FRMR_FRM_STAT_INT_EN,
2437: BIT_E1_FRMR_FRM_STAT_INT_EN_OOFE);*/
2438: }
2439:
2440: #if 0
2441: if (card->te_signaling_config == NULL) {
2442: /* Enable SIGE and COSS */
2443: /* log(LOG_INFO,"%s: Enable SIGX interrupt\n",card->devname);*/
2444: WRITE_REG(REG_SIGX_CFG,
2445: READ_REG(REG_SIGX_CFG) | BIT_SIGX_SIGE);
2446: WRITE_REG(REG_SIGX_CFG,
2447: READ_REG(REG_SIGX_CFG) | BIT_SIGX_COSS);
2448: }
2449: #endif
2450: /* Initialize T1/E1 timer */
2451: bit_clear((u_int8_t*)&card->fe_te.te_critical,TE_TIMER_KILL);
2452: /* Start T1/E1 timer */
2453: card->fe_te.te_timer_cmd = TE_LINKDOWN_TIMER;
2454: sdla_te_enable_timer(card, POLLING_TE1_TIMER);
2455: return;
2456: }
2457:
2458: /*
2459: * T1/E1 unconfig.
2460: */
2461: void sdla_te_unconfig(void* card_id)
2462: {
2463: sdla_t* card = (sdla_t*)card_id;
2464:
2465: if (!bit_test((u_int8_t*)&card->fe_te.te_critical, TE_CONFIGURED)) {
2466: return;
2467: }
2468:
2469: bit_clear((u_int8_t*)&card->fe_te.te_critical, TE_CONFIGURED);
2470: bit_set((u_int8_t*)&card->fe_te.te_critical, TE_TIMER_KILL);
2471:
2472: timeout_del(&card->fe_te.te_timer);
2473: return;
2474: }
2475:
2476: /*
2477: * Set T1/E1 status. Enable OOF and LCV interrupt
2478: * if status changed to disconnected.
2479: */
2480: static void
2481: sdla_te_set_status(sdla_t *card, unsigned long alarms)
2482: {
2483:
2484: if (IS_T1(&card->fe_te.te_cfg)) {
2485: if (IS_T1_ALARM(alarms)) {
2486: if (card->front_end_status != FE_DISCONNECTED) {
2487: log(LOG_INFO, "%s: T1 disconnected!\n",
2488: card->devname);
2489: card->front_end_status = FE_DISCONNECTED;
2490: }
2491: } else {
2492: if (card->front_end_status != FE_CONNECTED) {
2493: log(LOG_INFO, "%s: T1 connected!\n",
2494: card->devname);
2495: card->front_end_status = FE_CONNECTED;
2496: }
2497: }
2498: } else {
2499: if (IS_E1_ALARM(alarms)) {
2500: if (!bit_test((u_int8_t*)&card->fe_te.te_critical,
2501: TE_TIMER_RUNNING)) {
2502: card->fe_te.te_timer_cmd = TE_LINKDOWN_TIMER;
2503: sdla_te_enable_timer(card, POLLING_TE1_TIMER);
2504: }
2505: if (card->front_end_status != FE_DISCONNECTED) {
2506: log(LOG_INFO, "%s: E1 disconnected!\n",
2507: card->devname);
2508: card->front_end_status = FE_DISCONNECTED;
2509: }
2510: } else {
2511: if (card->front_end_status != FE_CONNECTED) {
2512: log(LOG_INFO, "%s: E1 connected!\n",
2513: card->devname);
2514: card->front_end_status = FE_CONNECTED;
2515: }
2516: }
2517: }
2518: #if 0
2519: if (card->te_report_alarms) {
2520: card->te_report_alarms(card, alarms);
2521: }
2522: #endif
2523:
2524: #if 0
2525: if (card->front_end_status == FE_CONNECTED) {
2526: WRITE_REG(REG_CDRC_INT_EN,
2527: (READ_REG(REG_CDRC_INT_EN) | BIT_CDRC_INT_EN_LOSE));
2528: } else {
2529: WRITE_REG(REG_CDRC_INT_EN,
2530: (READ_REG(REG_CDRC_INT_EN) & ~BIT_CDRC_INT_EN_LOSE));
2531: }
2532: #endif
2533:
2534: return;
2535: }
2536:
2537: /*
2538: * Read Alram Status for T1/E1 modes.
2539: *
2540: * Arguments:
2541: * Returns: bit 0 - ALOS (E1/T1)
2542: * bit 1 - LOS (E1/T1)
2543: * bit 2 - ALTLOS (E1/T1)
2544: * bit 3 - OOF (E1/T1)
2545: * bit 4 - RED (E1/T1)
2546: * bit 5 - AIS (E1/T1)
2547: * bit 6 - OOSMF (E1)
2548: * bit 7 - OOCMF (E1)
2549: * bit 8 - OOOF (E1)
2550: * bit 9 - RAI (E1)
2551: * bit A - YEL (T1)
2552: */
2553: unsigned long
2554: sdla_te_alarm(void *card_id, int manual_update)
2555: {
2556: sdla_t *card = (sdla_t*)card_id;
2557: unsigned long status = 0x00;
2558:
2559: WAN_ASSERT(card->write_front_end_reg == NULL);
2560: WAN_ASSERT(card->read_front_end_reg == NULL);
2561: /* Check common alarm for E1 and T1 configuration
2562: * 1. ALOS alarm
2563: * Reg 0xFA
2564: * Reg 0xF8 (ALOSI = 1)
2565: */
2566: if (READ_REG(REG_RLPS_ALOS_DET_PER) &&
2567: (READ_REG(REG_RLPS_CFG_STATUS) & BIT_RLPS_CFG_STATUS_ALOSV)) {
2568: status |= BIT_ALOS_ALARM;
2569: }
2570:
2571: /* 2. LOS alarm
2572: * Reg 0x10
2573: * Reg 0xF8 (ALOSI = 1)
2574: */
2575: if ((READ_REG(REG_CDRC_CFG) & (BIT_CDRC_CFG_LOS0|BIT_CDRC_CFG_LOS1)) &&
2576: (READ_REG(REG_CDRC_INT_STATUS) & BIT_CDRC_INT_STATUS_LOSV)) {
2577: status |= BIT_LOS_ALARM;
2578: }
2579:
2580: /* 3. ALTLOS alarm ??????????????????
2581: * Reg 0x13
2582: */
2583: if (READ_REG(REG_ALTLOS_STATUS) & BIT_ALTLOS_STATUS_ALTLOS) {
2584: status |= BIT_ALTLOS_ALARM;
2585: }
2586:
2587: /* Check specific E1 and T1 alarms */
2588: if (IS_E1(&card->fe_te.te_cfg)) {
2589: /* 4. OOF alarm */
2590: if (READ_REG(REG_E1_FRMR_FR_STATUS) &
2591: BIT_E1_FRMR_FR_STATUS_OOFV) {
2592: status |= BIT_OOF_ALARM;
2593: }
2594: /* 5. OOSMF alarm */
2595: if (READ_REG(REG_E1_FRMR_FR_STATUS) &
2596: BIT_E1_FRMR_FR_STATUS_OOSMFV) {
2597: status |= BIT_OOSMF_ALARM;
2598: }
2599: /* 6. OOCMF alarm */
2600: if (READ_REG(REG_E1_FRMR_FR_STATUS) &
2601: BIT_E1_FRMR_FR_STATUS_OOCMFV) {
2602: status |= BIT_OOCMF_ALARM;
2603: }
2604: /* 7. OOOF alarm */
2605: if (READ_REG(REG_E1_FRMR_FR_STATUS) &
2606: BIT_E1_FRMR_FR_STATUS_OOOFV) {
2607: status |= BIT_OOOF_ALARM;
2608: }
2609: /* 8. RAI alarm */
2610: if (READ_REG(REG_E1_FRMR_MAINT_STATUS) &
2611: BIT_E1_FRMR_MAINT_STATUS_RAIV) {
2612: status |= BIT_RAI_ALARM;
2613: }
2614: /* 9. RED alarm
2615: * Reg 0x97 (REDD)
2616: */
2617: if (READ_REG(REG_E1_FRMR_MAINT_STATUS) &
2618: BIT_E1_FRMR_MAINT_STATUS_RED) {
2619: status |= BIT_RED_ALARM;
2620: }
2621: /* 10. AIS alarm
2622: * Reg 0x91 (AISC)
2623: * Reg 0x97 (AIS)
2624: */
2625: if ((READ_REG(REG_E1_FRMR_MAINT_OPT) &
2626: BIT_E1_FRMR_MAINT_OPT_AISC) &&
2627: (READ_REG(REG_E1_FRMR_MAINT_STATUS) &
2628: BIT_E1_FRMR_MAINT_STATUS_AIS)) {
2629: status |= BIT_AIS_ALARM;
2630: }
2631: } else {
2632: /* 4. OOF alarm
2633: * Reg 0x4A (INFR=0 T1 mode)
2634: */
2635: if (!(READ_REG(REG_T1_FRMR_INT_STATUS) &
2636: BIT_T1_FRMR_INT_STATUS_INFR)) {
2637: status |= BIT_OOF_ALARM;
2638: }
2639: /* 5. AIS alarm
2640: * Reg 0x62 (AIS)
2641: * Reg 0x63 (AISD)
2642: */
2643: if ((READ_REG(REG_T1_ALMI_INT_STATUS) &
2644: BIT_T1_ALMI_INT_STATUS_AIS) &&
2645: (READ_REG(REG_T1_ALMI_DET_STATUS) &
2646: BIT_T1_ALMI_DET_STATUS_AISD)) {
2647: status |= BIT_AIS_ALARM;
2648: }
2649: /* 6. RED alarm
2650: * Reg 0x63 (REDD)
2651: */
2652: if (READ_REG(REG_T1_ALMI_DET_STATUS) &
2653: BIT_T1_ALMI_DET_STATUS_REDD) {
2654: status |= BIT_RED_ALARM;
2655: }
2656: /* 7. YEL alarm
2657: * Reg 0x62 (YEL)
2658: * Reg 0x63 (YELD)
2659: */
2660: if ((READ_REG(REG_T1_ALMI_INT_STATUS) &
2661: BIT_T1_ALMI_INT_STATUS_YEL) &&
2662: (READ_REG(REG_T1_ALMI_DET_STATUS) &
2663: BIT_T1_ALMI_DET_STATUS_YELD)) {
2664: status |= BIT_YEL_ALARM;
2665: }
2666: }
2667: if (manual_update) {
2668: sdla_te_set_status(card, status);
2669: }
2670: return status;
2671: }
2672:
2673:
2674: /*
2675: * Read PMC performance monitoring counters
2676: */
2677: void
2678: sdla_te_pmon(void *card_id)
2679: {
2680: sdla_t *card = (sdla_t*)card_id;
2681: pmc_pmon_t *pmon = &card->fe_te.te_pmon;
2682:
2683: WAN_ASSERT1(card->write_front_end_reg == NULL);
2684: WAN_ASSERT1(card->read_front_end_reg == NULL);
2685: /* Update PMON counters */
2686: WRITE_REG(REG_PMON_BIT_ERROR, 0x00);
2687: /* Framing bit for E1/T1 */
2688: pmon->frm_bit_error +=
2689: READ_REG(REG_PMON_BIT_ERROR) & BITS_PMON_BIT_ERROR;
2690:
2691: /* OOF Error for T1 or Far End Block Error for E1 */
2692: pmon->oof_errors +=
2693: ((READ_REG(REG_PMON_OOF_FEB_MSB_ERROR) &
2694: BITS_PMON_OOF_FEB_MSB_ERROR) << 8) |
2695: READ_REG(REG_PMON_OOF_FEB_LSB_ERROR);
2696:
2697: /* Bit Error for T1 or CRC Error for E1 */
2698: pmon->bit_errors +=
2699: ((READ_REG(REG_PMON_BIT_CRC_MSB_ERROR) &
2700: BITS_PMON_BIT_CRC_MSB_ERROR) << 8) |
2701: READ_REG(REG_PMON_BIT_CRC_LSB_ERROR);
2702:
2703: /* LCV Error for E1/T1 */
2704: pmon->lcv += ((READ_REG(REG_PMON_LCV_MSB_COUNT) &
2705: BITS_PMON_LCV_MSB_COUNT) << 8) | READ_REG(REG_PMON_LCV_LSB_COUNT);
2706: return;
2707: }
2708:
2709: /*
2710: * Flush PMC performance monitoring counters
2711: */
2712: void
2713: sdla_flush_te1_pmon(void *card_id)
2714: {
2715: sdla_t *card = (sdla_t*)card_id;
2716: pmc_pmon_t *pmon = &card->fe_te.te_pmon;
2717:
2718: pmon->pmon1 = 0;
2719: pmon->pmon2 = 0;
2720: pmon->pmon3 = 0;
2721: pmon->pmon4 = 0;
2722:
2723: return;
2724: }
2725:
2726: static int
2727: SetLoopBackChannel(sdla_t *card, int channel, unsigned char mode)
2728: {
2729: /* Set IND bit to 1 in TPSC to enable indirect access to TPSC
2730: ** register */
2731: WRITE_REG(REG_TPSC_CFG, BIT_TPSC_IND);
2732:
2733: /* Set LOOP to 1 for an IDLE code byte (the transmit data is
2734: * overwritten with the corresponding channel data from the receive
2735: * line. */
2736: if (mode == LINELB_ACTIVATE_CODE) {
2737: WRITE_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel,
2738: ((READ_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel) &
2739: MASK_TPSC_DATA_CTRL_BYTE) |
2740: BIT_TPSC_DATA_CTRL_BYTE_LOOP));
2741: } else {
2742: WRITE_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel,
2743: ((READ_TPSC_REG(REG_TPSC_DATA_CTRL_BYTE, channel) &
2744: MASK_TPSC_DATA_CTRL_BYTE) &
2745: ~BIT_TPSC_DATA_CTRL_BYTE_LOOP));
2746: }
2747:
2748: /* Set PCCE bit to 1 in TPSC to enable modifing the TPSC register */
2749: WRITE_REG(REG_TPSC_CFG,
2750: ((READ_REG(REG_TPSC_CFG) & MASK_TPSC_CFG) | BIT_TPSC_PCCE));
2751:
2752: return 0;
2753: }
2754:
2755: /*
2756: * Check interrupt type.
2757: * Arguments: card - pointer to device structure.
2758: * Returns: None.
2759: */
2760: void
2761: sdla_te_intr(void *arg)
2762: {
2763: sdla_t *card = (sdla_t*)arg;
2764:
2765: WAN_ASSERT1(card->write_front_end_reg == NULL);
2766: WAN_ASSERT1(card->read_front_end_reg == NULL);
2767: sdla_te_tx_intr(card);
2768: sdla_te_rx_intr(card);
2769: sdla_te_set_status(card, card->fe_te.te_alarm);
2770: }
2771:
2772: /*
2773: * Read tx interrupt.
2774: *
2775: * Arguments: card - pointer to device structure.
2776: * Returns: None.
2777: */
2778: static void
2779: sdla_te_tx_intr(sdla_t *card)
2780: {
2781: unsigned char intr_src1 = 0x00, intr_src2 = 0x00, intr_src3 = 0x00;
2782:
2783: intr_src1 = READ_REG(REG_INT_SRC_1);
2784: intr_src2 = READ_REG(REG_INT_SRC_2);
2785: intr_src3 = READ_REG(REG_INT_SRC_3);
2786:
2787: if (intr_src1 == 0 && intr_src2 == 0 && intr_src3 == 0) {
2788: log(LOG_DEBUG, "%s: Unknown %s interrupt!\n",
2789: card->devname,
2790: IS_T1(&card->fe_te.te_cfg) ? "T1" : "E1");
2791: }
2792: if (!(intr_src1 & BITS_TX_INT_SRC_1 ||
2793: intr_src2 & BITS_TX_INT_SRC_2 ||
2794: intr_src3 & BITS_TX_INT_SRC_3)) {
2795: return;
2796: }
2797:
2798: #if 0
2799: if (intr_src1 & BIT_INT_SRC_1_TJAT) {
2800: }
2801: if (intr_src1 & BIT_INT_SRC_1_APRM) {
2802: }
2803: if (intr_src2 & BIT_INT_SRC_2_TX_ELST) {
2804: }
2805: if (intr_src2 & BIT_INT_SRC_2_TDPR_1) {
2806: }
2807: if (intr_src2 & BIT_INT_SRC_2_TDPR_2) {
2808: }
2809: if (intr_src2 & BIT_INT_SRC_2_TDPR_3) {
2810: }
2811: if (intr_src3 & BIT_INT_SRC_3_TRAN) {
2812: }
2813: if (intr_src3 & BIT_INT_SRC_3_XPDE) {
2814: }
2815: if (intr_src3 & BIT_INT_SRC_3_BTIF) {
2816: }
2817: #endif
2818: return;
2819: }
2820:
2821:
2822: /*
2823: * Read rx interrupt.
2824: *
2825: * Arguments: card - pointer to device structure.
2826: * Returns: None.
2827: */
2828: static void
2829: sdla_te_rx_intr(sdla_t *card)
2830: {
2831: if (IS_T1(&card->fe_te.te_cfg)) {
2832: sdla_t1_rx_intr(card);
2833: } else {
2834: sdla_e1_rx_intr(card);
2835: }
2836: return;
2837: }
2838:
2839: /*
2840: * Read tx interrupt.
2841: *
2842: * Arguments: card - pointer to device structure.
2843: * Returns: None.
2844: */
2845: static void
2846: sdla_t1_rx_intr(sdla_t *card)
2847: {
2848: unsigned char intr_src1 = 0x00, intr_src2 = 0x00, intr_src3 = 0x00;
2849: unsigned char status = 0x00;
2850:
2851: intr_src1 = READ_REG(REG_INT_SRC_1);
2852: intr_src2 = READ_REG(REG_INT_SRC_2);
2853: intr_src3 = READ_REG(REG_INT_SRC_3);
2854:
2855: if (!(intr_src1 & BITS_RX_INT_SRC_1 ||
2856: intr_src2 & BITS_RX_INT_SRC_2 ||
2857: intr_src3 & BITS_RX_INT_SRC_3)) {
2858: return;
2859: }
2860:
2861: /* 3. PDVD */
2862: if (intr_src3 & BIT_INT_SRC_3_PDVD) {
2863: status = READ_REG(REG_PDVD_INT_EN_STATUS);
2864: if ((status & BIT_PDVD_INT_EN_STATUS_PDVE) &&
2865: (status & BIT_PDVD_INT_EN_STATUS_PDVI)) {
2866: if (status & BIT_PDVD_INT_EN_STATUS_PDV) {
2867: log(LOG_INFO, "%s: T1 pulse density "
2868: "violation detected!\n", card->devname);
2869: }
2870: }
2871: if ((status & BIT_PDVD_INT_EN_STATUS_Z16DE) &&
2872: (status & BIT_PDVD_INT_EN_STATUS_Z16DI)) {
2873: log(LOG_INFO, "%s: T1 16 consecutive zeros detected!\n",
2874: card->devname);
2875: }
2876: }
2877:
2878: /* 6. ALMI */
2879: if (intr_src3 & BIT_INT_SRC_3_ALMI) {
2880: status = READ_REG(REG_T1_ALMI_INT_STATUS);
2881: if (status & BIT_T1_ALMI_INT_STATUS_YELI) {
2882: if (status & BIT_T1_ALMI_INT_STATUS_YEL) {
2883: if (!(card->fe_te.te_alarm & BIT_YEL_ALARM)) {
2884: log(LOG_INFO, "%s: T1 YELLOW ON\n",
2885: card->devname);
2886: card->fe_te.te_alarm |= BIT_YEL_ALARM;
2887: }
2888: } else {
2889: if (card->fe_te.te_alarm & BIT_YEL_ALARM) {
2890: log(LOG_INFO, "%s: T1 YELLOW OFF\n",
2891: card->devname);
2892: card->fe_te.te_alarm &= ~BIT_YEL_ALARM;
2893: }
2894: }
2895: }
2896: if (status & BIT_T1_ALMI_INT_STATUS_REDI) {
2897: if (status & BIT_T1_ALMI_INT_STATUS_RED) {
2898: if (!(card->fe_te.te_alarm & BIT_RED_ALARM)) {
2899: log(LOG_INFO, "%s: T1 RED ON\n",
2900: card->devname);
2901: card->fe_te.te_alarm |= BIT_RED_ALARM;
2902: }
2903: } else {
2904: if (card->fe_te.te_alarm & BIT_RED_ALARM) {
2905: log(LOG_INFO, "%s: T1 RED OFF\n",
2906: card->devname);
2907: card->fe_te.te_alarm &= ~BIT_RED_ALARM;
2908: }
2909: }
2910: }
2911: if (status & BIT_T1_ALMI_INT_STATUS_AISI) {
2912: if (status & BIT_T1_ALMI_INT_STATUS_AIS) {
2913: if (!(card->fe_te.te_alarm & BIT_AIS_ALARM)) {
2914: log(LOG_INFO, "%s: T1 AIS ON\n",
2915: card->devname);
2916: card->fe_te.te_alarm |= BIT_AIS_ALARM;
2917: }
2918: } else {
2919: if (card->fe_te.te_alarm & BIT_AIS_ALARM) {
2920: log(LOG_INFO, "%s: T1 AIS OFF\n",
2921: card->devname);
2922: card->fe_te.te_alarm &= ~BIT_AIS_ALARM;
2923: }
2924: }
2925: }
2926:
2927: #if 0
2928: if (status &
2929: (BIT_T1_ALMI_INT_STATUS_YELI |
2930: BIT_T1_ALMI_INT_STATUS_REDI |
2931: BIT_T1_ALMI_INT_STATUS_AISI)) {
2932: if (status & (BIT_T1_ALMI_INT_STATUS_YEL |
2933: BIT_T1_ALMI_INT_STATUS_RED |
2934: BIT_T1_ALMI_INT_STATUS_AIS)) {
2935:
2936: /* Update T1/E1 alarm status */
2937: if (!(card->fe_te.te_alarm & BIT_YEL_ALARM) &&
2938: (status & BIT_T1_ALMI_INT_STATUS_YEL)) {
2939: log(LOG_INFO, "%s: T1 YELLOW ON\n",
2940: card->devname);
2941: card->fe_te.te_alarm |= BIT_YEL_ALARM;
2942: }
2943: if (!(card->fe_te.te_alarm & BIT_RED_ALARM) &&
2944: (status & BIT_T1_ALMI_INT_STATUS_RED)) {
2945: log(LOG_INFO, "%s: T1 RED ON\n",
2946: card->devname);
2947: card->fe_te.te_alarm |= BIT_RED_ALARM;
2948: }
2949: if (!(card->fe_te.te_alarm & BIT_AIS_ALARM) &&
2950: (status & BIT_T1_ALMI_INT_STATUS_AIS)) {
2951: log(LOG_INFO, "%s: T1 AIS ON\n",
2952: card->devname);
2953: card->fe_te.te_alarm |= BIT_AIS_ALARM;
2954: }
2955: } else {
2956: /* Update T1/E1 alarm status */
2957: if ((card->fe_te.te_alarm & BIT_YEL_ALARM) &&
2958: !(status & BIT_T1_ALMI_INT_STATUS_YEL)) {
2959: log(LOG_INFO, "%s: T1 YELLOW OFF\n",
2960: card->devname);
2961: card->fe_te.te_alarm &= ~BIT_YEL_ALARM;
2962: }
2963: if ((card->fe_te.te_alarm & BIT_RED_ALARM) &&
2964: !(status & BIT_T1_ALMI_INT_STATUS_RED)) {
2965: log(LOG_INFO, "%s: T1 RED OFF\n",
2966: card->devname);
2967: card->fe_te.te_alarm &= ~BIT_RED_ALARM;
2968: }
2969: if ((card->fe_te.te_alarm & BIT_AIS_ALARM) &&
2970: !(status & BIT_T1_ALMI_INT_STATUS_AIS)) {
2971: log(LOG_INFO, "%s: T1 ALMI OFF\n",
2972: card->devname);
2973: card->fe_te.te_alarm &= ~BIT_AIS_ALARM;
2974: }
2975: }
2976: }
2977: #endif
2978: }
2979:
2980: /* 8. RBOC */
2981: if (intr_src3 & BIT_INT_SRC_3_RBOC) {
2982: status = READ_REG(REG_T1_RBOC_CODE_STATUS);
2983: if (status & BIT_T1_RBOC_CODE_STATUS_BOCI) {
2984: struct timeval tv;
2985: unsigned long time;
2986:
2987: microtime(&tv);
2988: time = tv.tv_sec / 1000;
2989: status &= MASK_T1_RBOC_CODE_STATUS;
2990: switch (status) {
2991: case LINELB_ACTIVATE_CODE:
2992: case LINELB_DEACTIVATE_CODE:
2993: if (bit_test((u_int8_t *)
2994: &card->fe_te.te_critical, LINELB_WAITING) &&
2995: bit_test((u_int8_t *)
2996: &card->fe_te.te_critical,
2997: LINELB_CODE_BIT)) {
2998: bit_clear((u_int8_t *)
2999: &card->fe_te.te_critical,
3000: LINELB_CODE_BIT);
3001: break;
3002: }
3003:
3004: log(LOG_DEBUG, "%s: T1 LB %s code received.\n",
3005: card->devname,
3006: (status == LINELB_ACTIVATE_CODE) ?
3007: "activation" : "deactivation");
3008: card->fe_te.te_rx_lb_cmd = status;
3009: card->fe_te.te_rx_lb_time = time;
3010: break;
3011:
3012: case LINELB_DS1LINE_ALL:
3013: if (bit_test(
3014: (u_int8_t *)&card->fe_te.te_critical,
3015: LINELB_WAITING) &&
3016: bit_test(
3017: (u_int8_t *)&card->fe_te.te_critical,
3018: LINELB_CHANNEL_BIT)) {
3019: bit_clear((u_int8_t *)
3020: &card->fe_te.te_critical,
3021: LINELB_CHANNEL_BIT);
3022: bit_clear((u_int8_t*)
3023: &card->fe_te.te_critical,
3024: LINELB_WAITING);
3025: break;
3026: }
3027: if (!card->fe_te.te_rx_lb_cmd)
3028: break;
3029: if ((time - card->fe_te.te_rx_lb_time) <
3030: LINELB_TE1_TIMER) {
3031: log(LOG_INFO, "%s: T1 LB %s cancel!\n",
3032: card->devname,
3033: (card->fe_te.te_rx_lb_cmd ==
3034: LINELB_ACTIVATE_CODE)?
3035: "activatation":
3036: "deactivation");
3037: } else {
3038: unsigned char reg;
3039: if (card->fe_te.te_rx_lb_cmd ==
3040: LINELB_ACTIVATE_CODE) {
3041: log(LOG_INFO,
3042: "%s: T1 LB activated.\n",
3043: card->devname);
3044: reg=READ_REG(REG_MASTER_DIAG);
3045: reg|=BIT_MASTER_DIAG_LINELB;
3046: WRITE_REG(REG_MASTER_DIAG,reg);
3047: } else {
3048: log(LOG_INFO,
3049: "%s: T1 LB deactivated.\n",
3050: card->devname);
3051: reg=READ_REG(REG_MASTER_DIAG);
3052: reg&=~BIT_MASTER_DIAG_LINELB;
3053: WRITE_REG(REG_MASTER_DIAG,reg);
3054: }
3055: }
3056: card->fe_te.te_rx_lb_cmd = 0x00;
3057: card->fe_te.te_rx_lb_time = 0x00;
3058: break;
3059:
3060: case LINELB_DS3LINE:
3061: break;
3062:
3063: case LINELB_DS1LINE_1:
3064: case LINELB_DS1LINE_2:
3065: case LINELB_DS1LINE_3:
3066: case LINELB_DS1LINE_4:
3067: case LINELB_DS1LINE_5:
3068: case LINELB_DS1LINE_6:
3069: case LINELB_DS1LINE_7:
3070: case LINELB_DS1LINE_8:
3071: case LINELB_DS1LINE_9:
3072: case LINELB_DS1LINE_10:
3073: case LINELB_DS1LINE_11:
3074: case LINELB_DS1LINE_12:
3075: case LINELB_DS1LINE_13:
3076: case LINELB_DS1LINE_14:
3077: case LINELB_DS1LINE_15:
3078: case LINELB_DS1LINE_16:
3079: case LINELB_DS1LINE_17:
3080: case LINELB_DS1LINE_18:
3081: case LINELB_DS1LINE_19:
3082: case LINELB_DS1LINE_20:
3083: case LINELB_DS1LINE_21:
3084: case LINELB_DS1LINE_22:
3085: case LINELB_DS1LINE_23:
3086: case LINELB_DS1LINE_24:
3087: case LINELB_DS1LINE_25:
3088: case LINELB_DS1LINE_26:
3089: case LINELB_DS1LINE_27:
3090: case LINELB_DS1LINE_28:
3091: if (!card->fe_te.te_rx_lb_cmd)
3092: break;
3093: if ((time - card->fe_te.te_rx_lb_time) <
3094: LINELB_TE1_TIMER) {
3095: log(LOG_DEBUG, "%s: T1 LB %s cancel!\n",
3096: card->devname,
3097: (card->fe_te.te_rx_lb_cmd ==
3098: LINELB_ACTIVATE_CODE) ?
3099: "activatation": "deactivation");
3100: } else {
3101: int channel;
3102:
3103: channel = status & LINELB_DS1LINE_MASK;
3104: log(LOG_INFO, "%s: T1 LB %s ts %d\n",
3105: card->devname,
3106: (card->fe_te.te_rx_lb_cmd ==
3107: LINELB_ACTIVATE_CODE) ?
3108: "activated" : "deactivated",
3109: channel);
3110: SetLoopBackChannel(card, channel,
3111: card->fe_te.te_rx_lb_cmd);
3112: }
3113: card->fe_te.te_rx_lb_cmd = 0x00;
3114: card->fe_te.te_rx_lb_time = 0x00;
3115: break;
3116:
3117: default:
3118: log(LOG_DEBUG, "%s: Unknown signal (%02x).\n",
3119: card->devname, status);
3120: break;
3121: }
3122: }
3123: }
3124:
3125: /* 7. FRMR */
3126: if (intr_src1 & BIT_INT_SRC_1_FRMR) {
3127: status = READ_REG(REG_T1_FRMR_INT_STATUS);
3128: if ((READ_REG(REG_T1_FRMR_INT_EN) & BIT_T1_FRMR_INT_EN_INFRE) &&
3129: (status & BIT_T1_FRMR_INT_STATUS_INFRI)) {
3130: if (status & BIT_T1_FRMR_INT_STATUS_INFR) {
3131: if (!(card->fe_te.te_alarm & BIT_OOF_ALARM)) {
3132: log(LOG_INFO, "%s: T1 OOF ON!\n",
3133: card->devname);
3134: card->fe_te.te_alarm |= BIT_OOF_ALARM;
3135: }
3136: } else {
3137: if (card->fe_te.te_alarm & BIT_OOF_ALARM) {
3138: log(LOG_INFO, "%s: T1 OOF OFF!\n",
3139: card->devname);
3140: card->fe_te.te_alarm &= ~BIT_OOF_ALARM;
3141: }
3142: }
3143: }
3144: }
3145:
3146: /* 1. RLPS */
3147: if (intr_src3 & BIT_INT_SRC_3_RLPS) {
3148: status = READ_REG(REG_RLPS_CFG_STATUS);
3149: if ((status & BIT_RLPS_CFG_STATUS_ALOSE) &&
3150: (status & BIT_RLPS_CFG_STATUS_ALOSI)) {
3151: if (status & BIT_RLPS_CFG_STATUS_ALOSV) {
3152: if (!(card->fe_te.te_alarm & BIT_ALOS_ALARM)) {
3153: log(LOG_INFO, "%s: T1 ALOS ON\n",
3154: card->devname);
3155: card->fe_te.te_alarm |= BIT_ALOS_ALARM;
3156: }
3157: } else {
3158: if (card->fe_te.te_alarm & BIT_ALOS_ALARM) {
3159: log(LOG_INFO, "%s: T1 ALOS OFF\n",
3160: card->devname);
3161: card->fe_te.te_alarm &= ~BIT_ALOS_ALARM;
3162: }
3163: }
3164: }
3165: }
3166:
3167: /* 2. CDRC */
3168: if (intr_src1 & BIT_INT_SRC_1_CDRC) {
3169: status = READ_REG(REG_CDRC_INT_STATUS);
3170: if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_LOSE) &&
3171: (status & BIT_CDRC_INT_STATUS_LOSI)) {
3172: if (status & BIT_CDRC_INT_STATUS_LOSV) {
3173: if (!(card->fe_te.te_alarm & BIT_LOS_ALARM)) {
3174: log(LOG_INFO, "%s: T1 LOS ON\n",
3175: card->devname);
3176: card->fe_te.te_alarm |= BIT_LOS_ALARM;
3177: }
3178: } else {
3179: if (card->fe_te.te_alarm & BIT_LOS_ALARM) {
3180: log(LOG_INFO, "%s: T1 LOS OFF\n",
3181: card->devname);
3182: card->fe_te.te_alarm &= ~BIT_LOS_ALARM;
3183: }
3184: }
3185: }
3186: if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_LCVE) &&
3187: (status & BIT_CDRC_INT_STATUS_LCVI)) {
3188: log(LOG_INFO, "%s: T1 line code violation!\n",
3189: card->devname);
3190: }
3191: if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_LCSDE) &&
3192: (status & BIT_CDRC_INT_STATUS_LCSDI)) {
3193: log(LOG_INFO, "%s: T1 line code signature detected!\n",
3194: card->devname);
3195: }
3196: if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_ZNDE) &&
3197: (status & BIT_CDRC_INT_STATUS_ZNDI)) {
3198: log(LOG_INFO, "%s: T1 consecutive zeros detected!\n",
3199: card->devname);
3200: }
3201: status = READ_REG(REG_ALTLOS_STATUS);
3202: if ((status & BIT_ALTLOS_STATUS_ALTLOSI) &&
3203: (status & BIT_ALTLOS_STATUS_ALTLOSE)) {
3204: if (status & BIT_ALTLOS_STATUS_ALTLOS) {
3205: if (!(card->fe_te.te_alarm &
3206: BIT_ALTLOS_ALARM)) {
3207: log(LOG_INFO, "%s: T1 ALTLOS ON\n",
3208: card->devname);
3209: card->fe_te.te_alarm |=
3210: BIT_ALTLOS_ALARM;
3211: }
3212: } else {
3213: if (card->fe_te.te_alarm & BIT_ALTLOS_ALARM) {
3214: log(LOG_INFO, "%s: T1 ALTLOS OFF\n",
3215: card->devname);
3216: card->fe_te.te_alarm &=
3217: ~BIT_ALTLOS_ALARM;
3218: }
3219: }
3220: }
3221: }
3222:
3223: /* 14. PMON */
3224: if (intr_src1 & BIT_INT_SRC_1_PMON) {
3225: status = READ_REG(REG_PMON_INT_EN_STATUS);
3226: if (status & BIT_PMON_INT_EN_STATUS_XFER) {
3227: log(LOG_DEBUG, "%s: T1 Updating PMON counters...\n",
3228: card->devname);
3229: sdla_te_pmon(card);
3230: }
3231: }
3232:
3233: /* 9. SIGX */
3234: if (intr_src1 & BIT_INT_SRC_1_SIGX) {
3235: unsigned char SIGX_chg_30_25;
3236: unsigned char SIGX_chg_24_17;
3237: unsigned char SIGX_chg_16_9;
3238: unsigned char SIGX_chg_8_1;
3239:
3240: SIGX_chg_30_25 = READ_REG(REG_SIGX_CFG);
3241: SIGX_chg_24_17= READ_REG(REG_SIGX_TIMESLOT_IND_STATUS);
3242: SIGX_chg_16_9 = READ_REG(REG_SIGX_TIMESLOT_IND_ACCESS);
3243: SIGX_chg_8_1 = READ_REG(REG_SIGX_TIMESLOT_IND_DATA_BUFFER);
3244:
3245: }
3246:
3247: /* 5. IBCD */
3248: card->fe_te.te_alarm &= ~(BIT_LOOPUP_CODE|BIT_LOOPDOWN_CODE);
3249: if (intr_src3 & BIT_INT_SRC_3_IBCD) {
3250: status = READ_REG(REG_IBCD_INT_EN_STATUS);
3251: if (status & BIT_IBCD_INT_EN_STATUS_LBAI) {
3252: card->fe_te.te_alarm |= BIT_LOOPUP_CODE;
3253: }
3254: if (status & BIT_IBCD_INT_EN_STATUS_LBDI) {
3255: card->fe_te.te_alarm |= BIT_LOOPDOWN_CODE;
3256: }
3257: }
3258: #if 0
3259: /* 4. RJAT */
3260: if (intr_src1 & BIT_INT_SRC_1_RJAT) {
3261: }
3262: /* 10. RX-ELST */
3263: if (intr_src2 & BIT_INT_SRC_2_RX_ELST) {
3264: }
3265: /* 11. RDLC-1 */
3266: if (intr_src2 & BIT_INT_SRC_2_RDLC_1) {
3267: }
3268: /* 12. RDLC-2 */
3269: if (intr_src2 & BIT_INT_SRC_2_RDLC_2) {
3270: }
3271: /* 13. RDLC-3 */
3272: if (intr_src2 & BIT_INT_SRC_2_RDLC_3) {
3273: }
3274: #endif
3275:
3276: return;
3277: }
3278:
3279:
3280: /*
3281: * Read tx interrupt.
3282: *
3283: * Arguments: card - pointer to device structure.
3284: * Returns: None.
3285: */
3286: static void
3287: sdla_e1_rx_intr(sdla_t *card)
3288: {
3289: unsigned char intr_src1 = 0x00, intr_src2 = 0x00, intr_src3 = 0x00;
3290: unsigned char int_status = 0x00, status = 0x00;
3291:
3292: intr_src1 = READ_REG(REG_INT_SRC_1);
3293: intr_src2 = READ_REG(REG_INT_SRC_2);
3294: intr_src3 = READ_REG(REG_INT_SRC_3);
3295: if (!(intr_src1 & BITS_RX_INT_SRC_1 ||
3296: intr_src2 & BITS_RX_INT_SRC_2 ||
3297: intr_src3 & BITS_RX_INT_SRC_3))
3298: return;
3299:
3300: /* 4. FRMR */
3301: if (intr_src1 & BIT_INT_SRC_1_FRMR) {
3302: /* Register 0x94h E1 FRMR */
3303: int_status = READ_REG(REG_E1_FRMR_FRM_STAT_INT_IND);
3304: /* Register 0x96h E1 FRMR Status */
3305: status = READ_REG(REG_E1_FRMR_FR_STATUS);
3306: if ((READ_REG(REG_E1_FRMR_FRM_STAT_INT_EN) &
3307: BIT_E1_FRMR_FRM_STAT_INT_EN_OOFE) &&
3308: (int_status & BIT_E1_FRMR_FRM_STAT_INT_IND_OOFI)) {
3309: if (status & BIT_E1_FRMR_FR_STATUS_OOFV) {
3310: if (!(card->fe_te.te_alarm & BIT_OOF_ALARM)) {
3311: log(LOG_INFO, "%s: E1 OOF ON\n",
3312: card->devname);
3313: card->fe_te.te_alarm |= BIT_OOF_ALARM;
3314: }
3315: } else {
3316: if (card->fe_te.te_alarm & BIT_OOF_ALARM) {
3317: log(LOG_INFO, "%s: E1 OOF OFF\n",
3318: card->devname);
3319: card->fe_te.te_alarm &= ~BIT_OOF_ALARM;
3320: }
3321: }
3322: }
3323:
3324: if ((READ_REG(REG_E1_FRMR_FRM_STAT_INT_EN) &
3325: BIT_E1_FRMR_FRM_STAT_INT_EN_OOSMFE) &&
3326: (int_status & BIT_E1_FRMR_FRM_STAT_INT_IND_OOSMFI)) {
3327: if (status & BIT_E1_FRMR_FR_STATUS_OOSMFV) {
3328: log(LOG_INFO, "%s: E1 OOSMF ON\n",
3329: card->devname);
3330: card->fe_te.te_alarm |= BIT_OOSMF_ALARM;
3331: } else {
3332: log(LOG_INFO, "%s: E1 OOSMF OFF\n",
3333: card->devname);
3334: card->fe_te.te_alarm &= ~BIT_OOSMF_ALARM;
3335: }
3336: }
3337:
3338: if ((READ_REG(REG_E1_FRMR_FRM_STAT_INT_EN) &
3339: BIT_E1_FRMR_FRM_STAT_INT_EN_OOCMFE) &&
3340: (int_status & BIT_E1_FRMR_FRM_STAT_INT_IND_OOCMFI)) {
3341: if (status & BIT_E1_FRMR_FR_STATUS_OOCMFV) {
3342: log(LOG_INFO, "%s: E1 OOCMF ON\n",
3343: card->devname);
3344: card->fe_te.te_alarm |= BIT_OOCMF_ALARM;
3345: } else {
3346: log(LOG_INFO, "%s: E1 OOCMF OFF\n",
3347: card->devname);
3348: card->fe_te.te_alarm &= ~BIT_OOCMF_ALARM;
3349: }
3350: }
3351:
3352: /* Register 0x9Fh E1 FRMR */
3353: status = READ_REG(REG_E1_FRMR_P_A_INT_STAT);
3354: if ((READ_REG(REG_E1_FRMR_P_A_INT_EN) &
3355: BIT_E1_FRMR_P_A_INT_EN_OOOFE) &&
3356: (status & BIT_E1_FRMR_P_A_INT_STAT_OOOFI)) {
3357: if (READ_REG(REG_E1_FRMR_FR_STATUS) &
3358: BIT_E1_FRMR_FR_STATUS_OOOFV) {
3359: log(LOG_INFO, "%s: E1 OOOF ON\n",
3360: card->devname);
3361: card->fe_te.te_alarm |= BIT_OOOF_ALARM;
3362: } else {
3363: log(LOG_INFO, "%s: E1 OOOF OFF\n",
3364: card->devname);
3365: card->fe_te.te_alarm &= ~BIT_OOOF_ALARM;
3366: }
3367: }
3368:
3369: /* Register 0x95h E1 FRMR */
3370: int_status = READ_REG(REG_E1_FRMR_M_A_INT_IND);
3371: if (int_status & (BIT_E1_FRMR_M_A_INT_IND_REDI |
3372: BIT_E1_FRMR_M_A_INT_IND_AISI)) {
3373: status = READ_REG(REG_E1_FRMR_MAINT_STATUS);
3374: if ((READ_REG(REG_E1_FRMR_M_A_INT_EN) &
3375: BIT_E1_FRMR_M_A_INT_EN_REDE) &&
3376: (int_status & BIT_E1_FRMR_M_A_INT_IND_REDI)) {
3377: if (status & BIT_E1_FRMR_MAINT_STATUS_RED) {
3378: log(LOG_INFO, "%s: E1 RED ON\n",
3379: card->devname);
3380: card->fe_te.te_alarm |= BIT_RED_ALARM;
3381: } else {
3382: log(LOG_INFO, "%s: E1 RED OFF\n",
3383: card->devname);
3384: card->fe_te.te_alarm &= ~BIT_RED_ALARM;
3385: }
3386: }
3387: if ((READ_REG(REG_E1_FRMR_M_A_INT_EN) &
3388: BIT_E1_FRMR_M_A_INT_EN_AISE) &&
3389: (int_status & BIT_E1_FRMR_M_A_INT_IND_AISI)) {
3390: if (status & BIT_E1_FRMR_MAINT_STATUS_AIS) {
3391: log(LOG_INFO, "%s: E1 AIS ON\n",
3392: card->devname);
3393: card->fe_te.te_alarm |= BIT_AIS_ALARM;
3394: } else {
3395: log(LOG_INFO, "%s: E1 AIS OFF\n",
3396: card->devname);
3397: card->fe_te.te_alarm &= ~BIT_AIS_ALARM;
3398: }
3399: }
3400: if ((READ_REG(REG_E1_FRMR_M_A_INT_EN) &
3401: BIT_E1_FRMR_M_A_INT_EN_RAIE) &&
3402: (int_status & BIT_E1_FRMR_M_A_INT_IND_RAII)) {
3403: if (status & BIT_E1_FRMR_MAINT_STATUS_RAIV) {
3404: log(LOG_INFO, "%s: E1 RAI ON\n",
3405: card->devname);
3406: card->fe_te.te_alarm |= BIT_RAI_ALARM;
3407: } else {
3408: log(LOG_INFO, "%s: E1 RAI OFF\n",
3409: card->devname);
3410: card->fe_te.te_alarm &= ~BIT_RAI_ALARM;
3411: }
3412: }
3413: }
3414: }
3415:
3416: /* 1. RLPS */
3417: if (intr_src3 & BIT_INT_SRC_3_RLPS) {
3418: status = READ_REG(REG_RLPS_CFG_STATUS);
3419: if ((status & BIT_RLPS_CFG_STATUS_ALOSE) &&
3420: (status & BIT_RLPS_CFG_STATUS_ALOSI)) {
3421: if (status & BIT_RLPS_CFG_STATUS_ALOSV) {
3422: if (!(card->fe_te.te_alarm & BIT_ALOS_ALARM)) {
3423: log(LOG_INFO, "%s: E1 ALOS ON\n",
3424: card->devname);
3425: card->fe_te.te_alarm |= BIT_ALOS_ALARM;
3426: }
3427: } else {
3428: if (card->fe_te.te_alarm & BIT_ALOS_ALARM) {
3429: log(LOG_INFO, "%s: E1 ALOS is OFF\n",
3430: card->devname);
3431: card->fe_te.te_alarm &=
3432: ~BIT_ALOS_ALARM;
3433: }
3434: }
3435: }
3436: }
3437:
3438: /* 2. CDRC */
3439: if (intr_src1 & BIT_INT_SRC_1_CDRC) {
3440: status = READ_REG(REG_CDRC_INT_STATUS);
3441: if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_LOSE) &&
3442: (status & BIT_CDRC_INT_STATUS_LOSI)) {
3443: if (status & BIT_CDRC_INT_STATUS_LOSV) {
3444: if (!(card->fe_te.te_alarm & BIT_LOS_ALARM)) {
3445: log(LOG_INFO, "%s: E1 LOS is ON\n",
3446: card->devname);
3447: card->fe_te.te_alarm |= BIT_LOS_ALARM;
3448: }
3449: } else {
3450: if (card->fe_te.te_alarm & BIT_LOS_ALARM) {
3451: log(LOG_INFO, "%s: E1 LOS is OFF\n",
3452: card->devname);
3453: card->fe_te.te_alarm &= ~BIT_LOS_ALARM;
3454: }
3455: }
3456: }
3457: if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_LCVE) &&
3458: (status & BIT_CDRC_INT_STATUS_LCVI)) {
3459: log(LOG_INFO, "%s: E1 line code violation!\n",
3460: card->devname);
3461: }
3462: if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_LCSDE) &&
3463: (status & BIT_CDRC_INT_STATUS_LCSDI)) {
3464: log(LOG_INFO, "%s: E1 line code signature detected!\n",
3465: card->devname);
3466: }
3467: if ((READ_REG(REG_CDRC_INT_EN) & BIT_CDRC_INT_EN_ZNDE) &&
3468: (status & BIT_CDRC_INT_STATUS_ZNDI)) {
3469: log(LOG_INFO, "%s: E1 consecutive zeros detected!\n",
3470: card->devname);
3471: }
3472: status = READ_REG(REG_ALTLOS_STATUS);
3473: if ((status & BIT_ALTLOS_STATUS_ALTLOSI) &&
3474: (status & BIT_ALTLOS_STATUS_ALTLOSE)) {
3475: if (status & BIT_ALTLOS_STATUS_ALTLOS) {
3476: if (!(card->fe_te.te_alarm &
3477: BIT_ALTLOS_ALARM)) {
3478: log(LOG_INFO, "%s: E1 ALTLOS is ON\n",
3479: card->devname);
3480: card->fe_te.te_alarm |=
3481: BIT_ALTLOS_ALARM;
3482: }
3483: } else {
3484: if (card->fe_te.te_alarm & BIT_ALTLOS_ALARM) {
3485: log(LOG_INFO, "%s: E1 ALTLOS is OFF\n",
3486: card->devname);
3487: card->fe_te.te_alarm &=
3488: ~BIT_ALTLOS_ALARM;
3489: }
3490: }
3491: }
3492: }
3493: /* 11. PMON */
3494: if (intr_src1 & BIT_INT_SRC_1_PMON) {
3495: status = READ_REG(REG_PMON_INT_EN_STATUS);
3496: if (status & BIT_PMON_INT_EN_STATUS_XFER) {
3497: sdla_te_pmon(card);
3498: }
3499: }
3500: #if 0
3501: /* 3. RJAT */
3502: if (intr_src1 & BIT_INT_SRC_1_RJAT) {
3503: }
3504: /* 5. SIGX */
3505: if (intr_src1 & BIT_INT_SRC_1_SIGX) {
3506: }
3507: /* 6. RX-ELST */
3508: if (intr_src2 & BIT_INT_SRC_2_RX_ELST) {
3509: }
3510: /* 7. PRGD */
3511: if (intr_src1 & BIT_INT_SRC_1_PRGD) {
3512: }
3513: /* 8. RDLC-1 */
3514: if (intr_src2 & BIT_INT_SRC_2_RDLC_1) {
3515: }
3516: /* 9. RDLC-2 */
3517: if (intr_src2 & BIT_INT_SRC_2_RDLC_2) {
3518: }
3519: /* 10. RDLC-3 */
3520: if (intr_src2 & BIT_INT_SRC_2_RDLC_3) {
3521: }
3522: #endif
3523: if (!(READ_REG(REG_RLPS_CFG_STATUS) & BIT_RLPS_CFG_STATUS_ALOSV)) {
3524: card->fe_te.te_alarm &= ~BIT_ALOS_ALARM;
3525: }
3526: return;
3527: }
3528:
3529: /*
3530: * Set T1/E1 loopback modes.
3531: */
3532: int
3533: sdla_set_te1_lb_modes(void *arg, unsigned char type, unsigned char mode)
3534: {
3535: sdla_t *card = (sdla_t*)arg;
3536: int err = 1;
3537:
3538: WAN_ASSERT(card->write_front_end_reg == NULL);
3539: WAN_ASSERT(card->read_front_end_reg == NULL);
3540: switch (type) {
3541: case WAN_TE1_LINELB_MODE:
3542: err = sdla_te_linelb(card, mode);
3543: break;
3544: case WAN_TE1_PAYLB_MODE:
3545: err = sdla_te_paylb(card, mode);
3546: break;
3547: case WAN_TE1_DDLB_MODE:
3548: err = sdla_te_ddlb(card, mode);
3549: break;
3550: case WAN_TE1_TX_LB_MODE:
3551: err = sdla_te_lb(card, mode);
3552: break;
3553: }
3554:
3555: return err;
3556: }
3557:
3558: /*
3559: * Activate/Deactivate Line Loopback mode.
3560: */
3561: static int
3562: sdla_te_linelb(sdla_t *card, unsigned char mode)
3563: {
3564: WAN_ASSERT(card->write_front_end_reg == NULL);
3565: WAN_ASSERT(card->read_front_end_reg == NULL);
3566: if (mode == WAN_TE1_ACTIVATE_LB) {
3567: log(LOG_INFO, "%s: %s Line Loopback mode activated.\n",
3568: card->devname,
3569: (IS_T1(&card->fe_te.te_cfg) ? "T1" : "E1"));
3570: WRITE_REG(REG_MASTER_DIAG,
3571: READ_REG(REG_MASTER_DIAG) | BIT_MASTER_DIAG_LINELB);
3572: } else {
3573: log(LOG_INFO, "%s: %s Line Loopback mode deactivated.\n",
3574: card->devname,
3575: (IS_T1(&card->fe_te.te_cfg) ? "T1" : "E1"));
3576: WRITE_REG(REG_MASTER_DIAG,
3577: READ_REG(REG_MASTER_DIAG) & ~BIT_MASTER_DIAG_LINELB);
3578: }
3579: return 0;
3580: }
3581:
3582: /*
3583: * Activate/Deactivate Payload loopback mode.
3584: */
3585: static int
3586: sdla_te_paylb(sdla_t *card, unsigned char mode)
3587: {
3588: WAN_ASSERT(card->write_front_end_reg == NULL);
3589: WAN_ASSERT(card->read_front_end_reg == NULL);
3590: if (mode == WAN_TE1_ACTIVATE_LB) {
3591: log(LOG_INFO, "%s: %s Payload Loopback mode activated.\n",
3592: card->devname, (IS_T1(&card->fe_te.te_cfg) ? "T1" : "E1"));
3593: WRITE_REG(REG_MASTER_DIAG,
3594: READ_REG(REG_MASTER_DIAG) | BIT_MASTER_DIAG_PAYLB);
3595: } else {
3596: log(LOG_INFO, "%s: %s Payload Loopback mode deactivated.\n",
3597: card->devname, (IS_T1(&card->fe_te.te_cfg) ? "T1" : "E1"));
3598: WRITE_REG(REG_MASTER_DIAG,
3599: READ_REG(REG_MASTER_DIAG) & ~BIT_MASTER_DIAG_PAYLB);
3600: }
3601: return 0;
3602: }
3603:
3604: /*
3605: * Description: Activate/Deactivate Diagnostic Digital loopback mode.
3606: */
3607: static int
3608: sdla_te_ddlb(sdla_t *card, unsigned char mode)
3609: {
3610: WAN_ASSERT(card->write_front_end_reg == NULL);
3611: WAN_ASSERT(card->read_front_end_reg == NULL);
3612: if (mode == WAN_TE1_ACTIVATE_LB) {
3613: log(LOG_INFO, "%s: %s Diagnostic Dig. LB mode activated.\n",
3614: card->devname, (IS_T1(&card->fe_te.te_cfg) ? "T1" : "E1"));
3615: WRITE_REG(REG_MASTER_DIAG,
3616: READ_REG(REG_MASTER_DIAG) | BIT_MASTER_DIAG_DDLB);
3617: } else {
3618: log(LOG_INFO, "%s: %s Diagnostic Dig. LB mode deactivated.\n",
3619: card->devname, (IS_T1(&card->fe_te.te_cfg) ? "T1" : "E1"));
3620: WRITE_REG(REG_MASTER_DIAG,
3621: READ_REG(REG_MASTER_DIAG) & ~BIT_MASTER_DIAG_DDLB);
3622: }
3623: return 0;
3624: }
3625:
3626: void
3627: sdla_te_timer(void *card_id)
3628: {
3629: sdla_t *card = (sdla_t*)card_id;
3630:
3631: if (bit_test((u_int8_t*)&card->fe_te.te_critical,TE_TIMER_KILL)) {
3632: bit_clear((u_int8_t*)&card->fe_te.te_critical,TE_TIMER_RUNNING);
3633: return;
3634: }
3635: /*WAN_ASSERT1(card->te_enable_timer == NULL); */
3636: /* Enable hardware interrupt for TE1 */
3637: if (card->te_enable_timer) {
3638: card->te_enable_timer(card);
3639: } else {
3640: sdla_te_polling(card);
3641: }
3642:
3643: return;
3644: }
3645:
3646: /*
3647: * Enable software timer interrupt in delay ms.
3648: */
3649: static void
3650: sdla_te_enable_timer(sdla_t *card, unsigned long delay)
3651: {
3652:
3653: WAN_ASSERT1(card == NULL);
3654: if (bit_test((u_int8_t*)&card->fe_te.te_critical, TE_TIMER_KILL)) {
3655: bit_clear((u_int8_t*)&card->fe_te.te_critical,
3656: TE_TIMER_RUNNING);
3657: return;
3658: }
3659: bit_set((u_int8_t*)&card->fe_te.te_critical, TE_TIMER_RUNNING);
3660:
3661: timeout_add(&card->fe_te.te_timer, delay * hz / 1000);
3662: return;
3663: }
3664:
3665: /*
3666: * Description: Process T1/E1 polling function.
3667: */
3668: void
3669: sdla_te_polling(void *card_id)
3670: {
3671: sdla_t* card = (sdla_t*)card_id;
3672:
3673: WAN_ASSERT1(card->write_front_end_reg == NULL);
3674: WAN_ASSERT1(card->read_front_end_reg == NULL);
3675: bit_clear((u_int8_t*)&card->fe_te.te_critical, TE_TIMER_RUNNING);
3676: switch (card->fe_te.te_timer_cmd) {
3677: case TE_LINELB_TIMER:
3678: if (IS_T1(&card->fe_te.te_cfg)) {
3679: /* Sending T1 activation/deactivation LB signal */
3680: if (card->fe_te.te_tx_lb_cnt > 10) {
3681: WRITE_REG(REG_T1_XBOC_CODE,
3682: (card->fe_te.te_tx_lb_cmd ==
3683: WAN_TE1_ACTIVATE_LB) ?
3684: LINELB_ACTIVATE_CODE :
3685: LINELB_DEACTIVATE_CODE);
3686: } else {
3687: WRITE_REG(REG_T1_XBOC_CODE,
3688: LINELB_DS1LINE_ALL);
3689: }
3690: if (--card->fe_te.te_tx_lb_cnt) {
3691: sdla_te_enable_timer(card, LINELB_TE1_TIMER);
3692: } else {
3693: log(LOG_DEBUG, "%s: TX T1 LB %s signal.\n",
3694: card->devname,
3695: (card->fe_te.te_tx_lb_cmd ==
3696: WAN_TE1_ACTIVATE_LB) ?
3697: "activation" : "deactivation");
3698: card->fe_te.te_tx_lb_cmd = 0x00;
3699: bit_clear((u_int8_t*)&card->fe_te.te_critical,
3700: TE_TIMER_RUNNING);
3701: }
3702: }
3703: break;
3704:
3705: case TE_SET_INTR:
3706: sdla_te_set_intr(card);
3707: break;
3708:
3709: case TE_LINKDOWN_TIMER:
3710: if ((READ_REG(REG_RLPS_ALOS_DET_PER) &&
3711: (READ_REG(REG_RLPS_CFG_STATUS) &
3712: BIT_RLPS_CFG_STATUS_ALOSV)) ||
3713: (IS_E1(&card->fe_te.te_cfg) &&
3714: (READ_REG(REG_E1_FRMR_FR_STATUS) &
3715: BIT_E1_FRMR_FR_STATUS_OOFV)) ||
3716: (IS_T1(&card->fe_te.te_cfg) &&
3717: (READ_REG(REG_T1_FRMR_INT_STATUS) &
3718: ~BIT_T1_FRMR_INT_STATUS_INFR))) {
3719: sdla_te_enable_timer(card, POLLING_TE1_TIMER);
3720: } else {
3721: /* All other interrupt reports status changed
3722: * through interrupts, we don't need to read
3723: * these values here */
3724: sdla_te_set_status(card, card->fe_te.te_alarm);
3725: if (card->front_end_status == FE_CONNECTED) {
3726: card->fe_te.te_timer_cmd = TE_LINKUP_TIMER;
3727: sdla_te_enable_timer(card, POLLING_TE1_TIMER);
3728: }
3729: }
3730: break;
3731:
3732: case TE_LINKUP_TIMER:
3733: /* ALEX:
3734: * Do not update protocol front end state from
3735: * TE_LINKDOWN_TIMER because it cause to stay
3736: * more longer in interrupt handler (critical for XILINX
3737: * code) */
3738: if (card->te_link_state) {
3739: card->te_link_state(card);
3740: }
3741: break;
3742: }
3743: return;
3744: }
3745:
3746: /*
3747: * Description: Transmit loopback signal to remote side.
3748: */
3749: static int
3750: sdla_te_lb(sdla_t *card, unsigned char mode)
3751: {
3752: WAN_ASSERT(card->write_front_end_reg == NULL);
3753: WAN_ASSERT(card->read_front_end_reg == NULL);
3754:
3755: if (!IS_T1(&card->fe_te.te_cfg)) {
3756: return 1;
3757: }
3758: if (card->front_end_status != FE_CONNECTED) {
3759: return 1;
3760: }
3761: if (bit_test((u_int8_t*)&card->fe_te.te_critical,TE_TIMER_RUNNING))
3762: return 1;
3763: if (bit_test((u_int8_t*)&card->fe_te.te_critical,LINELB_WAITING)) {
3764: log(LOG_DEBUG, "%s: Waiting for loopback signal!\n",
3765: card->devname);
3766: }
3767: log(LOG_DEBUG, "%s: Sending %s loopback %s signal...\n",
3768: card->devname, (IS_T1(&card->fe_te.te_cfg) ? "T1" : "E1"),
3769: (mode == WAN_TE1_ACTIVATE_LB) ? "activation" : "deactivation");
3770: card->fe_te.te_tx_lb_cmd = mode;
3771: card->fe_te.te_tx_lb_cnt = LINELB_CODE_CNT + LINELB_CHANNEL_CNT;
3772: card->fe_te.te_timer_cmd = TE_LINELB_TIMER;
3773: bit_set((u_int8_t*)&card->fe_te.te_critical, LINELB_WAITING);
3774: bit_set((u_int8_t*)&card->fe_te.te_critical, LINELB_CODE_BIT);
3775: bit_set((u_int8_t*)&card->fe_te.te_critical, LINELB_CHANNEL_BIT);
3776: sdla_te_enable_timer(card, LINELB_TE1_TIMER);
3777:
3778: return 0;
3779: }
3780:
3781: int
3782: sdla_te_udp(void *card_id, void *cmd, unsigned char *data)
3783: {
3784: sdla_t *card = (sdla_t*)card_id;
3785: wan_cmd_t *udp_cmd = (wan_cmd_t*)cmd;
3786: int err = 0;
3787:
3788: switch (udp_cmd->wan_cmd_command) {
3789: case WAN_GET_MEDIA_TYPE:
3790: data[0] =
3791: IS_T1(&card->fe_te.te_cfg) ? WAN_MEDIA_T1 :
3792: IS_E1(&card->fe_te.te_cfg) ? WAN_MEDIA_E1 :
3793: WAN_MEDIA_NONE;
3794: udp_cmd->wan_cmd_return_code = WAN_CMD_OK;
3795: udp_cmd->wan_cmd_data_len = sizeof(unsigned char);
3796: break;
3797:
3798: case WAN_FE_SET_LB_MODE:
3799: /* Activate/Deactivate Line Loopback modes */
3800: err = sdla_set_te1_lb_modes(card, data[0], data[1]);
3801: udp_cmd->wan_cmd_return_code =
3802: (!err) ? WAN_CMD_OK : WAN_UDP_FAILED_CMD;
3803: udp_cmd->wan_cmd_data_len = 0x00;
3804: break;
3805:
3806: case WAN_FE_GET_STAT:
3807: /* TE1_56K Read T1/E1/56K alarms */
3808: *(unsigned long *)&data[0] = sdla_te_alarm(card, 0);
3809: /* TE1 Update T1/E1 perfomance counters */
3810: sdla_te_pmon(card);
3811: memcpy(&data[sizeof(unsigned long)],
3812: &card->fe_te.te_pmon, sizeof(pmc_pmon_t));
3813: udp_cmd->wan_cmd_return_code = WAN_CMD_OK;
3814: udp_cmd->wan_cmd_data_len =
3815: sizeof(unsigned long) + sizeof(pmc_pmon_t);
3816:
3817: break;
3818:
3819: case WAN_FE_FLUSH_PMON:
3820: /* TE1 Flush T1/E1 pmon counters */
3821: sdla_flush_te1_pmon(card);
3822: udp_cmd->wan_cmd_return_code = WAN_CMD_OK;
3823: break;
3824:
3825: case WAN_FE_GET_CFG:
3826: /* Read T1/E1 configuration */
3827: memcpy(&data[0], &card->fe_te.te_cfg, sizeof(sdla_te_cfg_t));
3828: udp_cmd->wan_cmd_return_code = WAN_CMD_OK;
3829: udp_cmd->wan_cmd_data_len = sizeof(sdla_te_cfg_t);
3830: break;
3831:
3832: default:
3833: udp_cmd->wan_cmd_return_code = WAN_UDP_INVALID_CMD;
3834: udp_cmd->wan_cmd_data_len = 0;
3835: break;
3836: }
3837: return 0;
3838: }
3839:
3840:
3841: void
3842: aft_green_led_ctrl(void *card_id, int mode)
3843: {
3844: sdla_t *card = (sdla_t*)card_id;
3845: unsigned char led;
3846:
3847: if (!card->read_front_end_reg ||
3848: !card->write_front_end_reg) {
3849: return;
3850: }
3851:
3852: led= READ_REG(REG_GLOBAL_CFG);
3853:
3854: if (mode == AFT_LED_ON) {
3855: led&=~(BIT_GLOBAL_PIO);
3856: } else if (mode == AFT_LED_OFF) {
3857: led|=BIT_GLOBAL_PIO;
3858: } else {
3859: if (led&BIT_GLOBAL_PIO) {
3860: led&=~(BIT_GLOBAL_PIO);
3861: } else {
3862: led|=BIT_GLOBAL_PIO;
3863: }
3864: }
3865:
3866: WRITE_REG(REG_GLOBAL_CFG,led);
3867: }
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