Annotation of sys/dev/pci/if_nfereg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: if_nfereg.h,v 1.21 2007/01/08 18:39:27 damien Exp $ */
2:
3: /*-
4: * Copyright (c) 2005 Jonathan Gray <jsg@openbsd.org>
5: *
6: * Permission to use, copy, modify, and distribute this software for any
7: * purpose with or without fee is hereby granted, provided that the above
8: * copyright notice and this permission notice appear in all copies.
9: *
10: * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11: * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12: * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13: * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14: * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15: * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16: * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17: */
18:
19: #define NFE_PCI_BA 0x10
20:
21: #define NFE_RX_RING_COUNT 128
22: #define NFE_TX_RING_COUNT 256
23:
24: #define NFE_JUMBO_FRAMELEN 9018
25: #define NFE_JUMBO_MTU (NFE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
26:
27: #define NFE_JBYTES (NFE_JUMBO_FRAMELEN + ETHER_ALIGN)
28: #define NFE_JPOOL_COUNT (NFE_RX_RING_COUNT + 64)
29: #define NFE_JPOOL_SIZE (NFE_JPOOL_COUNT * NFE_JBYTES)
30:
31: #define NFE_MAX_SCATTER (NFE_TX_RING_COUNT - 2)
32:
33: #define NFE_IRQ_STATUS 0x000
34: #define NFE_IRQ_MASK 0x004
35: #define NFE_SETUP_R6 0x008
36: #define NFE_IMTIMER 0x00c
37: #define NFE_MISC1 0x080
38: #define NFE_TX_CTL 0x084
39: #define NFE_TX_STATUS 0x088
40: #define NFE_RXFILTER 0x08c
41: #define NFE_RXBUFSZ 0x090
42: #define NFE_RX_CTL 0x094
43: #define NFE_RX_STATUS 0x098
44: #define NFE_RNDSEED 0x09c
45: #define NFE_SETUP_R1 0x0a0
46: #define NFE_SETUP_R2 0x0a4
47: #define NFE_MACADDR_HI 0x0a8
48: #define NFE_MACADDR_LO 0x0ac
49: #define NFE_MULTIADDR_HI 0x0b0
50: #define NFE_MULTIADDR_LO 0x0b4
51: #define NFE_MULTIMASK_HI 0x0b8
52: #define NFE_MULTIMASK_LO 0x0bc
53: #define NFE_PHY_IFACE 0x0c0
54: #define NFE_TX_RING_ADDR_LO 0x100
55: #define NFE_RX_RING_ADDR_LO 0x104
56: #define NFE_RING_SIZE 0x108
57: #define NFE_TX_UNK 0x10c
58: #define NFE_LINKSPEED 0x110
59: #define NFE_SETUP_R5 0x130
60: #define NFE_SETUP_R3 0x13C
61: #define NFE_SETUP_R7 0x140
62: #define NFE_RXTX_CTL 0x144
63: #define NFE_TX_RING_ADDR_HI 0x148
64: #define NFE_RX_RING_ADDR_HI 0x14c
65: #define NFE_PHY_STATUS 0x180
66: #define NFE_SETUP_R4 0x184
67: #define NFE_STATUS 0x188
68: #define NFE_PHY_SPEED 0x18c
69: #define NFE_PHY_CTL 0x190
70: #define NFE_PHY_DATA 0x194
71: #define NFE_WOL_CTL 0x200
72: #define NFE_PATTERN_CRC 0x204
73: #define NFE_PATTERN_MASK 0x208
74: #define NFE_PWR_CAP 0x268
75: #define NFE_PWR_STATE 0x26c
76: #define NFE_VTAG_CTL 0x300
77:
78: #define NFE_PHY_ERROR 0x00001
79: #define NFE_PHY_WRITE 0x00400
80: #define NFE_PHY_BUSY 0x08000
81: #define NFE_PHYADD_SHIFT 5
82:
83: #define NFE_STATUS_MAGIC 0x140000
84:
85: #define NFE_R1_MAGIC 0x16070f
86: #define NFE_R2_MAGIC 0x16
87: #define NFE_R4_MAGIC 0x08
88: #define NFE_R6_MAGIC 0x03
89: #define NFE_WOL_ENABLE 0x1111
90: #define NFE_RX_START 0x01
91: #define NFE_TX_START 0x01
92:
93: #define NFE_IRQ_RXERR 0x0001
94: #define NFE_IRQ_RX 0x0002
95: #define NFE_IRQ_RX_NOBUF 0x0004
96: #define NFE_IRQ_TXERR 0x0008
97: #define NFE_IRQ_TX_DONE 0x0010
98: #define NFE_IRQ_TIMER 0x0020
99: #define NFE_IRQ_LINK 0x0040
100: #define NFE_IRQ_TXERR2 0x0080
101: #define NFE_IRQ_TX1 0x0100
102:
103: #define NFE_IRQ_WANTED \
104: (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX | \
105: NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE | \
106: NFE_IRQ_LINK)
107:
108: #define NFE_RXTX_KICKTX 0x0001
109: #define NFE_RXTX_BIT1 0x0002
110: #define NFE_RXTX_BIT2 0x0004
111: #define NFE_RXTX_RESET 0x0010
112: #define NFE_RXTX_VTAG_STRIP 0x0040
113: #define NFE_RXTX_VTAG_INSERT 0x0080
114: #define NFE_RXTX_RXCSUM 0x0400
115: #define NFE_RXTX_V2MAGIC 0x2100
116: #define NFE_RXTX_V3MAGIC 0x2200
117: #define NFE_RXFILTER_MAGIC 0x007f0008
118: #define NFE_U2M (1 << 5)
119: #define NFE_PROMISC (1 << 7)
120:
121: /* default interrupt moderation timer of 128us */
122: #define NFE_IM_DEFAULT ((128 * 100) / 1024)
123:
124: #define NFE_VTAG_ENABLE (1 << 13)
125:
126: #define NFE_PWR_VALID (1 << 8)
127: #define NFE_PWR_WAKEUP (1 << 15)
128:
129: #define NFE_MEDIA_SET 0x10000
130: #define NFE_MEDIA_1000T 0x00032
131: #define NFE_MEDIA_100TX 0x00064
132: #define NFE_MEDIA_10T 0x003e8
133:
134: #define NFE_PHY_100TX (1 << 0)
135: #define NFE_PHY_1000T (1 << 1)
136: #define NFE_PHY_HDX (1 << 8)
137:
138: #define NFE_MISC1_MAGIC 0x003b0f3c
139: #define NFE_MISC1_HDX (1 << 1)
140:
141: #define NFE_SEED_MASK 0x0003ff00
142: #define NFE_SEED_10T 0x00007f00
143: #define NFE_SEED_100TX 0x00002d00
144: #define NFE_SEED_1000T 0x00007400
145:
146: /* Rx/Tx descriptor */
147: struct nfe_desc32 {
148: uint32_t physaddr;
149: uint16_t length;
150: uint16_t flags;
151: #define NFE_RX_FIXME_V1 0x6004
152: #define NFE_RX_VALID_V1 (1 << 0)
153: #define NFE_TX_ERROR_V1 0x7808
154: #define NFE_TX_LASTFRAG_V1 (1 << 0)
155: } __packed;
156:
157: #define NFE_V1_TXERR "\020" \
158: "\14TXERROR\13UNDERFLOW\12LATECOLLISION\11LOSTCARRIER\10DEFERRED" \
159: "\08FORCEDINT\03RETRY\00LASTPACKET"
160:
161: /* V2 Rx/Tx descriptor */
162: struct nfe_desc64 {
163: uint32_t physaddr[2];
164: uint32_t vtag;
165: #define NFE_RX_VTAG (1 << 16)
166: #define NFE_TX_VTAG (1 << 18)
167: uint16_t length;
168: uint16_t flags;
169: #define NFE_RX_FIXME_V2 0x4300
170: #define NFE_RX_VALID_V2 (1 << 13)
171: #define NFE_TX_ERROR_V2 0x5c04
172: #define NFE_TX_LASTFRAG_V2 (1 << 13)
173: } __packed;
174:
175: #define NFE_V2_TXERR "\020" \
176: "\14FORCEDINT\13LASTPACKET\12UNDERFLOW\10LOSTCARRIER\09DEFERRED\02RETRY"
177:
178: /* flags common to V1/V2 descriptors */
179: #define NFE_RX_UDP_CSUMOK (1 << 10)
180: #define NFE_RX_TCP_CSUMOK (1 << 11)
181: #define NFE_RX_IP_CSUMOK (1 << 12)
182: #define NFE_RX_ERROR (1 << 14)
183: #define NFE_RX_READY (1 << 15)
184: #define NFE_TX_TCP_UDP_CSUM (1 << 10)
185: #define NFE_TX_IP_CSUM (1 << 11)
186: #define NFE_TX_VALID (1 << 15)
187:
188: #define NFE_READ(sc, reg) \
189: bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (reg))
190:
191: #define NFE_WRITE(sc, reg, val) \
192: bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (reg), (val))
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