![[BACK]](/icons/back.gif){kind=icon}
Return to if_myxreg.h CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / dev / pci|
Return to if_myxreg.h CVS log | Up to [local] / sys / dev / pci |
1.1 nbrk 1: /* $OpenBSD: if_myxreg.h,v 1.2 2007/06/01 18:07:08 reyk Exp $ */
2:
3: /*
4: * Copyright (c) 2007 Reyk Floeter <reyk@openbsd.org>
5: *
6: * Permission to use, copy, modify, and distribute this software for any
7: * purpose with or without fee is hereby granted, provided that the above
8: * copyright notice and this permission notice appear in all copies.
9: *
10: * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11: * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12: * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13: * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14: * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15: * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16: * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17: */
18:
19: /*
20: * Register definitions for the Myricom Myri-10G Lanai-Z8E Ethernet chipsets.
21: */
22:
23: #ifndef _MYX_REG_H
24: #define _MYX_REG_H
25:
26: /*
27: * Common definitions
28: */
29:
30: #define MYXBAR0 PCI_MAPREG_START
31:
32: #define MYX_NRXDESC 256
33: #define MYX_NTXDESC_MIN 2
34: #define MYX_IRQCOALDELAY 30
35: #define MYX_IRQDEASSERTWAIT 1
36: #define MYX_MAX_MTU_SMALL (ETHERMTU + ETHER_HDR_LEN + 4)
37: #define MYX_MAX_MTU_BIG PAGE_SIZE
38:
39: #define MYXALIGN_CMD 64
40: #define MYXALIGN_DATA PAGE_SIZE
41:
42: #define MYX_ADDRHIGH(_v) ((_v >> 32) & 0xffffffff)
43: #define MYX_ADDRLOW(_v) (_v & 0xffffffff)
44:
45: /*
46: * PCI memory/register layout
47: */
48:
49: #define MYX_SRAM 0x00000000 /* SRAM offset */
50: #define MYX_SRAM_SIZE 0x001dff00 /* SRAM size */
51: #define MYX_HEADER_POS 0x0000003c /* Header position offset */
52: #define MYX_HEADER_POS_SIZE 0x00000004 /* Header position size */
53: #define MYX_FW 0x00100000 /* Firmware offset */
54: #define MYX_FW_BOOT 0x00100008 /* Firmware boot offset */
55: #define MYX_EEPROM 0x001dfe00 /* EEPROM offset */
56: #define MYX_EEPROM_SIZE 0x00000100 /* EEPROM size */
57: #define MYX_BOOT 0x00fc0000 /* Boot handoff */
58: #define MYX_RDMA 0x00fc01c0 /* Dummy RDMA */
59: #define MYX_CMD 0x00f80000 /* Command offset */
60:
61: /*
62: * Firmware definitions
63: */
64:
65: #define MYXFW_ALIGNED "myx-eth_z8e"
66: #define MYXFW_UNALIGNED "myx-ethp_z8e"
67: #define MYXFW_TYPE_ETH 0x45544820
68: #define MYXFW_VER "1.4." /* stored as a string... */
69:
70: #define MYXFW_MIN_LEN (MYX_HEADER_POS + MYX_HEADER_POS_SIZE)
71:
72: struct myx_firmware_hdr {
73: u_int32_t fw_hdrlength;
74: u_int32_t fw_type;
75: u_int8_t fw_version[128];
76: u_int32_t fw_sram_size;
77: u_int32_t fw_specs;
78: u_int32_t fw_specs_len;
79: } __packed;
80:
81:
82: /*
83: * Commands, descriptors, and DMA structures
84: */
85:
86: struct myx_cmd {
87: u_int32_t mc_cmd;
88: u_int32_t mc_data0;
89: u_int32_t mc_data1;
90: u_int32_t mc_data2;
91: u_int32_t mc_addr_high;
92: u_int32_t mc_addr_low;
93: u_int8_t mc_pad[40]; /* pad up to 64 bytes */
94: } __packed;
95:
96: struct myx_response {
97: u_int32_t mr_data;
98: u_int32_t mr_result;
99: } __packed;
100:
101: struct myx_bootcmd {
102: u_int32_t bc_addr_high;
103: u_int32_t bc_addr_low;
104: u_int32_t bc_result;
105: u_int32_t bc_offset;
106: u_int32_t bc_length;
107: u_int32_t bc_copyto;
108: u_int32_t bc_jumpto;
109: u_int8_t bc_pad[36]; /* pad up to 64 bytes */
110: } __packed;
111:
112: struct myx_rdmacmd {
113: u_int32_t rc_addr_high;
114: u_int32_t rc_addr_low;
115: u_int32_t rc_result;
116: u_int32_t rc_rdma_high;
117: u_int32_t rc_rdma_low;
118: u_int32_t rc_enable;
119: #define MYXRDMA_ON 1
120: #define MYXRDMA_OFF 0
121: u_int8_t rc_pad[40]; /* pad up to 64 bytes */
122: } __packed;
123:
124: struct myx_status {
125: u_int32_t ms_reserved;
126: u_int32_t ms_dropped_pause;
127: u_int32_t ms_dropped_unicast;
128: u_int32_t ms_dropped_crc32err;
129: u_int32_t ms_dropped_phyerr;
130: u_int32_t ms_dropped_mcast;
131: u_int32_t ms_txdonecnt;
132: u_int32_t ms_linkstate;
133: #define MYXSTS_LINKDOWN 0
134: #define MYXSTS_LINKUP 1
135: #define MYXSTS_LINKMYRINET 2
136: #define MYXSTS_LINKUNKNOWN 3
137: u_int32_t ms_dropped_linkoverflow;
138: u_int32_t ms_dropped_linkerror;
139: u_int32_t ms_dropped_runt;
140: u_int32_t ms_dropped_overrun;
141: u_int32_t ms_dropped_smallbufunderrun;
142: u_int32_t ms_dropped_bigbufunderrun;
143: u_int32_t ms_rdmatags_available;
144: #define MYXSTS_RDMAON 1
145: #define MYXSTS_RDMAOFF 0
146: u_int8_t ms_txstopped;
147: u_int8_t ms_linkdowncnt;
148: u_int8_t ms_statusupdated;
149: u_int8_t ms_isvalid;
150: } __packed;
151:
152: struct myx_rxdesc {
153: u_int16_t rx_csum;
154: u_int16_t rx_length;
155: } __packed;
156:
157: struct myx_rxbufdesc {
158: u_int32_t rb_addr_high;
159: u_int32_t rb_addr_low;
160: } __packed;
161:
162: struct myx_txdesc {
163: u_int32_t tx_addr_high;
164: u_int32_t tx_addr_low;
165: u_int16_t tx_hdr_offset;
166: u_int16_t tx_length;
167: u_int8_t tx_pad;
168: u_int8_t tx_nsegs;
169: u_int8_t tx_cksum_offset;
170: u_int8_t tx_flags;
171: #define MYXTXD_FLAGS_SMALL (1<<0)
172: #define MYXTXD_FLAGS_FIRST (1<<1)
173: #define MYXTXD_FLAGS_ALIGN_ODD (1<<2)
174: #define MYXTXD_FLAGS_CKSUM (1<<3)
175: #define MYXTXD_FLAGS_NO_TSO (1<<4)
176:
177: #define MYXTXD_FLAGS_TSO_HDR (1<<0)
178: #define MYXTXD_FLAGS_TSO_LAST (1<<3)
179: #define MYXTXD_FLAGS_TSO_CHOP (1<<4)
180: #define MYXTXD_FLAGS_TSO_PLD (1<<5)
181: } __packed;
182:
183: enum {
184: MYXCMD_NONE = 0,
185: MYXCMD_RESET = 1,
186: MYXCMD_GET_VERSION = 2,
187: MYXCMD_SET_INTRQDMA = 3,
188: MYXCMD_SET_BIGBUFSZ = 4,
189: MYXCMD_SET_SMALLBUFSZ = 5,
190: MYXCMD_GET_TXRINGOFF = 6,
191: MYXCMD_GET_RXSMALLRINGOFF = 7,
192: MYXCMD_GET_RXBIGRINGOFF = 8,
193: MYXCMD_GET_INTRACKOFF = 9,
194: MYXCMD_GET_INTRDEASSERTOFF = 10,
195: MYXCMD_GET_TXRINGSZ = 11,
196: MYXCMD_GET_RXRINGSZ = 12,
197: MYXCMD_SET_INTRQSZ = 13,
198: MYXCMD_SET_IFUP = 14,
199: MYXCMD_SET_IFDOWN = 15,
200: MYXCMD_SET_MTU = 16,
201: MYXCMD_GET_INTRCOALDELAYOFF = 17,
202: MYXCMD_SET_STATSINTVL = 18,
203: MYXCMD_SET_STATSDMA_OLD = 19,
204: MYXCMD_SET_PROMISC = 20,
205: MYXCMD_UNSET_PROMISC = 21,
206: MYXCMD_SET_LLADDR = 22,
207: MYXCMD_SET_FC = 23,
208: MYXCMD_UNSET_FC = 24,
209: #define MYXCMD_FC_DEFAULT MYXCMD_SET_FC /* set flow control */
210: MYXCMD_DMA_TEST = 25,
211: MYXCMD_SET_ALLMULTI = 26,
212: MYXCMD_UNSET_ALLMULTI = 27,
213: MYXCMD_SET_MCASTGROUP = 28,
214: MYXCMD_UNSET_MCASTGROUP = 29,
215: MYXCMD_UNSET_MCAST = 30,
216: MYXCMD_SET_STATSDMA = 31,
217: MYXCMD_UNALIGNED_DMA_TEST = 32,
218: MYXCMD_GET_UNALIGNED_STATUS = 33,
219: MYXCMD_MAX = 34
220: };
221:
222: enum {
223: MYXCMD_OK = 0,
224: MYXCMD_UNKNOWN = 1,
225: MYXCMD_ERR_RANGE = 2,
226: MYXCMD_ERR_BUSY = 3,
227: MYXCMD_ERR_EMPTY = 4,
228: MYXCMD_ERR_CLOSED = 5,
229: MYXCMD_ERR_HASH = 6,
230: MYXCMD_ERR_BADPORT = 7,
231: MYXCMD_ERR_RES = 8,
232: MYXCMD_ERR_MULTICAST = 9,
233: MYXCMD_ERR_UNALIGNED = 10
234: };
235:
236: #endif /* _MYX_REG_H */