Annotation of sys/dev/pci/if_lmcvar.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: if_lmcvar.h,v 1.10 2006/03/25 22:41:45 djm Exp $ */
2: /* $NetBSD: if_lmcvar.h,v 1.1 1999/03/25 03:32:43 explorer Exp $ */
3:
4: /*-
5: * Copyright (c) 1997-1999 LAN Media Corporation (LMC)
6: * All rights reserved. www.lanmedia.com
7: *
8: * This code is written by Michael Graff <graff@vix.com> for LMC.
9: * The code is derived from permitted modifications to software created
10: * by Matt Thomas (matt@3am-software.com).
11: *
12: * Redistribution and use in source and binary forms, with or without
13: * modification, are permitted provided that the following conditions
14: * are met:
15: * 1. Redistributions of source code must retain the above copyright
16: * notice, this list of conditions and the following disclaimer.
17: * 2. Redistributions in binary form must reproduce the above
18: * copyright notice, this list of conditions and the following disclaimer
19: * in the documentation and/or other materials provided with the
20: * distribution.
21: * 3. All marketing or advertising materials mentioning features or
22: * use of this software must display the following acknowledgement:
23: * This product includes software developed by LAN Media Corporation
24: * and its contributors.
25: * 4. Neither the name of LAN Media Corporation nor the names of its
26: * contributors may be used to endorse or promote products derived
27: * from this software without specific prior written permission.
28: *
29: * THIS SOFTWARE IS PROVIDED BY LAN MEDIA CORPORATION AND CONTRIBUTORS
30: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
31: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
32: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
33: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
34: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
37: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39: * THE POSSIBILITY OF SUCH DAMAGE.
40: */
41:
42: /*-
43: * Copyright (c) 1994-1997 Matt Thomas (matt@3am-software.com)
44: * All rights reserved.
45: *
46: * Redistribution and use in source and binary forms, with or without
47: * modification, are permitted provided that the following conditions
48: * are met:
49: * 1. Redistributions of source code must retain the above copyright
50: * notice, this list of conditions and the following disclaimer.
51: * 2. The name of the author may not be used to endorse or promote products
52: * derived from this software without specific prior written permission
53: *
54: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
55: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
56: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
57: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
58: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
59: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
60: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
61: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
62: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
63: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
64: */
65:
66: #define LMC_MTU 1500
67: #define PPP_HEADER_LEN 4
68: #define BIG_PACKET
69: #define LMC_DATA_PER_DESC 2032
70:
71: /*
72: * This turns on all sort of debugging stuff and make the
73: * driver much larger.
74: */
75: #if 0
76: #define LMC_DEBUG
77: typedef enum {
78: LMC_21040_GENERIC, /* Generic 21040 (works with most any board) */
79: LMC_21140_ISV, /* Digital Semicondutor 21140 ISV SROM Format */
80: LMC_21142_ISV, /* Digital Semicondutor 21142 ISV SROM Format */
81: LMC_21143_ISV, /* Digital Semicondutor 21143 ISV SROM Format */
82: LMC_21140_DEC_EB, /* Digital Semicondutor 21140 Evaluation Board */
83: LMC_21140_MII, /* 21140[A] with MII */
84: LMC_21140_DEC_DE500, /* Digital DE500-?? 10/100 */
85: LMC_21140_SMC_9332, /* SMC 9332 */
86: LMC_21140_COGENT_EM100, /* Cogent EM100 100 only */
87: LMC_21140_ZNYX_ZX34X, /* ZNYX ZX342 10/100 */
88: LMC_21140_ASANTE, /* AsanteFast 10/100 */
89: LMC_21140_EN1207, /* Accton EN2107 10/100 BNC */
90: LMC_21041_GENERIC /* Generic 21041 card */
91: } lmc_board_t;
92:
93: typedef enum {
94: LMC_MEDIAPOLL_TIMER, /* 100ms timer fired */
95: LMC_MEDIAPOLL_FASTTIMER, /* <100ms timer fired */
96: LMC_MEDIAPOLL_LINKFAIL, /* called from interrupt routine */
97: LMC_MEDIAPOLL_LINKPASS, /* called from interrupt routine */
98: LMC_MEDIAPOLL_START, /* start a media probe (called from reset) */
99: LMC_MEDIAPOLL_TXPROBE_OK, /* txprobe succeeded */
100: LMC_MEDIAPOLL_TXPROBE_FAILED, /* txprobe failed */
101: LMC_MEDIAPOLL_MAX
102: } lmc_mediapoll_event_t;
103: #define DP(x) printf x
104: #else
105: #define DP(x)
106: #endif
107:
108: /*
109: * the dec chip has its own idea of what a receive error is, but we don't
110: * want to use it, as it will get the crc error wrong when 16-bit
111: * crcs are used. So, we only care about certain conditions.
112: */
113: #ifndef TULIP_DSTS_RxMIIERR
114: #define TULIP_DSTS_RxMIIERR 0x00000008
115: #endif
116: #define LMC_DSTS_ERRSUM (TULIP_DSTS_RxMIIERR)
117:
118: /*
119: * This is the PCI configuration support.
120: */
121: #define PCI_CFID 0x00 /* Configuration ID */
122: #define PCI_CFCS 0x04 /* Configurtion Command/Status */
123: #define PCI_CFRV 0x08 /* Configuration Revision */
124: #define PCI_CFLT 0x0c /* Configuration Latency Timer */
125: #define PCI_CBIO 0x10 /* Configuration Base IO Address */
126: #define PCI_CBMA 0x14 /* Configuration Base Memory Address */
127: #define PCI_SSID 0x2c /* subsystem config register */
128: #define PCI_CFIT 0x3c /* Configuration Interrupt */
129: #define PCI_CFDA 0x40 /* Configuration Driver Area */
130:
131: #define LMC_HZ 10
132:
133: #ifndef TULIP_GP_PINSET
134: #define TULIP_GP_PINSET 0x00000100L
135: #endif
136: #ifndef TULIP_BUSMODE_READMULTIPLE
137: #define TULIP_BUSMODE_READMULTIPLE 0x00200000L
138: #endif
139:
140: #define LMC_CSR_READ(sc, csr) \
141: bus_space_read_4((sc)->lmc_bustag, (sc)->lmc_bushandle, (sc)->lmc_csrs.csr)
142: #define LMC_CSR_WRITE(sc, csr, val) \
143: bus_space_write_4((sc)->lmc_bustag, (sc)->lmc_bushandle, (sc)->lmc_csrs.csr, (val))
144:
145: #define LMC_CSR_READBYTE(sc, csr) \
146: bus_space_read_1((sc)->lmc_bustag, (sc)->lmc_bushandle, (sc)->lmc_csrs.csr)
147: #define LMC_CSR_WRITEBYTE(sc, csr, val) \
148: bus_space_write_1((sc)->lmc_bustag, (sc)->lmc_bushandle, (sc)->lmc_csrs.csr, (val))
149:
150: #define LMC_PCI_CSRSIZE 8
151: #define LMC_PCI_CSROFFSET 0
152:
153: /*
154: * This structure contains "pointers" for the registers on
155: * the various 21x4x chips.
156: */
157: typedef struct {
158: lmc_csrptr_t csr_busmode; /* CSR0 */
159: lmc_csrptr_t csr_txpoll; /* CSR1 */
160: lmc_csrptr_t csr_rxpoll; /* CSR2 */
161: lmc_csrptr_t csr_rxlist; /* CSR3 */
162: lmc_csrptr_t csr_txlist; /* CSR4 */
163: lmc_csrptr_t csr_status; /* CSR5 */
164: lmc_csrptr_t csr_command; /* CSR6 */
165: lmc_csrptr_t csr_intr; /* CSR7 */
166: lmc_csrptr_t csr_missed_frames; /* CSR8 */
167: lmc_csrptr_t csr_9; /* CSR9 */
168: lmc_csrptr_t csr_10; /* CSR10 */
169: lmc_csrptr_t csr_11; /* CSR11 */
170: lmc_csrptr_t csr_12; /* CSR12 */
171: lmc_csrptr_t csr_13; /* CSR13 */
172: lmc_csrptr_t csr_14; /* CSR14 */
173: lmc_csrptr_t csr_15; /* CSR15 */
174: } lmc_regfile_t;
175:
176: #define csr_enetrom csr_9 /* 21040 */
177: #define csr_reserved csr_10 /* 21040 */
178: #define csr_full_duplex csr_11 /* 21040 */
179: #define csr_bootrom csr_10 /* 21041/21140A/?? */
180: #define csr_gp csr_12 /* 21140* */
181: #define csr_watchdog csr_15 /* 21140* */
182: #define csr_gp_timer csr_11 /* 21041/21140* */
183: #define csr_srom_mii csr_9 /* 21041/21140* */
184: #define csr_sia_status csr_12 /* 2104x */
185: #define csr_sia_connectivity csr_13 /* 2104x */
186: #define csr_sia_tx_rx csr_14 /* 2104x */
187: #define csr_sia_general csr_15 /* 2104x */
188:
189: /*
190: * While 21x4x allows chaining of its descriptors, this driver
191: * doesn't take advantage of it. We keep the descriptors in a
192: * traditional FIFO ring.
193: */
194: struct lmc_ringinfo {
195: lmc_desc_t *ri_first; /* first entry in ring */
196: lmc_desc_t *ri_last; /* one after last entry */
197: lmc_desc_t *ri_nextin; /* next to processed by host */
198: lmc_desc_t *ri_nextout; /* next to processed by adapter */
199: int ri_max;
200: int ri_free;
201: };
202:
203: /*
204: * The 21040 has a stupid restriction in that the receive
205: * buffers must be longword aligned. But since Ethernet
206: * headers are not a multiple of longwords in size this forces
207: * the data to non-longword aligned. Since IP requires the
208: * data to be longword aligned, we need to copy it after it has
209: * been DMA'ed in our memory.
210: *
211: * Since we have to copy it anyways, we might as well as allocate
212: * dedicated receive space for the input. This allows to use a
213: * small receive buffer size and more ring entries to be able to
214: * better keep with a flood of tiny Ethernet packets.
215: *
216: * The receive space MUST ALWAYS be a multiple of the page size.
217: * And the number of receive descriptors multiplied by the size
218: * of the receive buffers must equal the recevive space. This
219: * is so that we can manipulate the page tables so that even if a
220: * packet wraps around the end of the receive space, we can
221: * treat it as virtually contiguous.
222: *
223: * The above used to be true (the stupid restriction is still true)
224: * but we gone to directly DMA'ing into MBUFs (unless it's on an
225: * architecture which can't handle unaligned accesses) because with
226: * 100Mb/s cards the copying is just too much of a hit.
227: */
228:
229: #define LMC_RXDESCS 48
230: #define LMC_TXDESCS 128
231: #define LMC_RXQ_TARGET 32
232: #if LMC_RXQ_TARGET >= LMC_RXDESCS
233: #error LMC_RXQ_TARGET must be less than LMC_RXDESCS
234: #endif
235:
236: #define LMC_RX_BUFLEN ((MCLBYTES < 2048 ? MCLBYTES : 2048) - 16)
237:
238: #define LMC_LINK_UP 1
239: #define LMC_LINK_DOWN 0
240:
241: typedef enum {
242: LMC_21140, LMC_21140A,
243: LMC_CHIPID_UNKNOWN
244: } lmc_chipid_t;
245:
246: #define LMC_BIT(b) (1L << ((int)(b)))
247:
248: typedef struct {
249: /*
250: * Transmit Statistics
251: */
252: u_int32_t dot3StatsSingleCollisionFrames;
253: u_int32_t dot3StatsMultipleCollisionFrames;
254: u_int32_t dot3StatsSQETestErrors;
255: u_int32_t dot3StatsDeferredTransmissions;
256: u_int32_t dot3StatsLateCollisions;
257: u_int32_t dot3StatsExcessiveCollisions;
258: u_int32_t dot3StatsCarrierSenseErrors;
259: u_int32_t dot3StatsInternalMacTransmitErrors;
260: u_int32_t dot3StatsInternalTransmitUnderflows; /* not in rfc1650! */
261: u_int32_t dot3StatsInternalTransmitBabbles; /* not in rfc1650! */
262: /*
263: * Receive Statistics
264: */
265: u_int32_t dot3StatsMissedFrames; /* not in rfc1650! */
266: u_int32_t dot3StatsAlignmentErrors;
267: u_int32_t dot3StatsFCSErrors;
268: u_int32_t dot3StatsFrameTooLongs;
269: u_int32_t dot3StatsInternalMacReceiveErrors;
270: } lmc_dot3_stats_t;
271:
272: /*
273: * Now to important stuff. This is softc structure (where does softc
274: * come from??? No idea) for the tulip device.
275: *
276: */
277: struct lmc___softc {
278: struct device lmc_dev; /* base device */
279: void *lmc_ih; /* intrrupt vectoring */
280: void *lmc_ats; /* shutdown hook */
281: bus_space_tag_t lmc_bustag;
282: bus_space_handle_t lmc_bushandle; /* CSR region handle */
283: pci_chipset_tag_t lmc_pc;
284:
285: struct sppp lmc_sppp;
286: #define lmc_if lmc_sppp.pp_if
287:
288: u_int8_t lmc_enaddr[6]; /* yes, a small hack... */
289: lmc_regfile_t lmc_csrs;
290: volatile u_int32_t lmc_txtick;
291: volatile u_int32_t lmc_rxtick;
292: u_int32_t lmc_flags;
293:
294: u_int32_t lmc_features; /* static bits indicating features of chip */
295: u_int32_t lmc_intrmask; /* our copy of csr_intr */
296: u_int32_t lmc_cmdmode; /* our copy of csr_cmdmode */
297: u_int32_t lmc_last_system_error : 3; /* last system error (only value is LMC_SYSTEMERROR is also set) */
298: u_int32_t lmc_system_errors; /* number of system errors encountered */
299: u_int32_t lmc_statusbits; /* status bits from CSR5 that may need to be printed */
300:
301: u_int8_t lmc_revinfo; /* revision of chip */
302: u_int8_t lmc_cardtype; /* LMC_CARDTYPE_HSSI or ..._DS3 */
303: u_int32_t lmc_gpio_io; /* state of in/out settings */
304: u_int32_t lmc_gpio; /* state of outputs */
305: u_int8_t lmc_gp;
306:
307: lmc_chipid_t lmc_chipid; /* type of chip we are using */
308: u_int32_t lmc_miireg16;
309: struct ifqueue lmc_txq;
310: struct ifqueue lmc_rxq;
311: lmc_dot3_stats_t lmc_dot3stats;
312: lmc_ringinfo_t lmc_rxinfo;
313: lmc_ringinfo_t lmc_txinfo;
314: u_int8_t lmc_rombuf[128];
315: lmc_media_t *lmc_media;
316: lmc_ctl_t ictl;
317:
318: bus_dma_tag_t lmc_dmatag; /* bus DMA tag */
319: bus_dmamap_t lmc_setupmap;
320: bus_dmamap_t lmc_txdescmap;
321: bus_dmamap_t lmc_txmaps[LMC_TXDESCS];
322: unsigned lmc_txmaps_free;
323: bus_dmamap_t lmc_rxdescmap;
324: bus_dmamap_t lmc_rxmaps[LMC_RXDESCS];
325: unsigned lmc_rxmaps_free;
326:
327: struct device *lmc_pci_busno; /* needed for multiport boards */
328: u_int8_t lmc_pci_devno; /* needed for multiport boards */
329: lmc_desc_t *lmc_rxdescs;
330: lmc_desc_t *lmc_txdescs;
331:
332: u_int32_t lmc_crcSize;
333: u_int32_t tx_clockState;
334: char lmc_yel, lmc_blue, lmc_red; /* for T1 and DS3 */
335: char lmc_timing; /* for HSSI and SSI */
336: u_int16_t t1_alarm1_status;
337: u_int16_t t1_alarm2_status;
338: #if defined(LMC_DEBUG)
339: /*
340: * Debugging/Statistical information
341: */
342: struct {
343: lmc_media_t dbg_last_media;
344: u_int32_t dbg_intrs;
345: u_int32_t dbg_media_probes;
346: u_int32_t dbg_txprobe_nocarr;
347: u_int32_t dbg_txprobe_exccoll;
348: u_int32_t dbg_link_downed;
349: u_int32_t dbg_link_suspected;
350: u_int32_t dbg_link_intrs;
351: u_int32_t dbg_link_pollintrs;
352: u_int32_t dbg_link_failures;
353: u_int32_t dbg_nway_starts;
354: u_int32_t dbg_nway_failures;
355: u_int16_t dbg_phyregs[32][4];
356: u_int32_t dbg_rxlowbufs;
357: u_int32_t dbg_rxintrs;
358: u_int32_t dbg_last_rxintrs;
359: u_int32_t dbg_high_rxintrs_hz;
360: u_int32_t dbg_no_txmaps;
361: u_int32_t dbg_txput_finishes[8];
362: u_int32_t dbg_txprobes_ok;
363: u_int32_t dbg_txprobes_failed;
364: u_int32_t dbg_events[LMC_MEDIAPOLL_MAX];
365: u_int32_t dbg_rxpktsperintr[LMC_RXDESCS];
366: } lmc_dbg;
367: #endif
368: };
369:
370: /*
371: * lmc_flags
372: */
373: #define LMC_IFUP 0x00000001
374: #define LMC_00000002 0x00000002
375: #define LMC_00000004 0x00000004
376: #define LMC_00000008 0x00000008
377: #define LMC_00000010 0x00000010
378: #define LMC_MODEMOK 0x00000020
379: #define LMC_00000040 0x00000040
380: #define LMC_00000080 0x00000080
381: #define LMC_RXACT 0x00000100
382: #define LMC_INRESET 0x00000200
383: #define LMC_NEEDRESET 0x00000400
384: #define LMC_00000800 0x00000800
385: #define LMC_00001000 0x00001000
386: #define LMC_00002000 0x00002000
387: #define LMC_WANTTXSTART 0x00004000
388: #define LMC_NEWTXTHRESH 0x00008000
389: #define LMC_NOAUTOSENSE 0x00010000
390: #define LMC_PRINTLINKUP 0x00020000
391: #define LMC_LINKUP 0x00040000
392: #define LMC_RXBUFSLOW 0x00080000
393: #define LMC_NOMESSAGES 0x00100000
394: #define LMC_SYSTEMERROR 0x00200000
395: #define LMC_TIMEOUTPENDING 0x00400000
396: #define LMC_00800000 0x00800000
397: #define LMC_01000000 0x01000000
398: #define LMC_02000000 0x02000000
399: #define LMC_RXIGNORE 0x04000000
400: #define LMC_08000000 0x08000000
401: #define LMC_10000000 0x10000000
402: #define LMC_20000000 0x20000000
403: #define LMC_40000000 0x40000000
404: #define LMC_80000000 0x80000000
405:
406: /*
407: * lmc_features
408: */
409: #define LMC_HAVE_GPR 0x00000001 /* have gp register (140[A]) */
410: #define LMC_HAVE_RXBADOVRFLW 0x00000002 /* RX corrupts on overflow */
411: #define LMC_HAVE_POWERMGMT 0x00000004 /* Snooze/sleep modes */
412: #define LMC_HAVE_MII 0x00000008 /* Some medium on MII */
413: #define LMC_HAVE_SIANWAY 0x00000010 /* SIA does NWAY */
414: #define LMC_HAVE_DUALSENSE 0x00000020 /* SIA senses both AUI & TP */
415: #define LMC_HAVE_SIAGP 0x00000040 /* SIA has a GP port */
416: #define LMC_HAVE_BROKEN_HASH 0x00000080 /* Broken Multicast Hash */
417: #define LMC_HAVE_ISVSROM 0x00000100 /* uses ISV SROM Format */
418: #define LMC_HAVE_BASEROM 0x00000200 /* Board ROM can be cloned */
419: #define LMC_HAVE_SLAVEDROM 0x00000400 /* Board ROM cloned */
420: #define LMC_HAVE_SLAVEDINTR 0x00000800 /* Board slaved interrupt */
421: #define LMC_HAVE_SHAREDINTR 0x00001000 /* Board shares interrupts */
422: #define LMC_HAVE_OKROM 0x00002000 /* ROM was recognized */
423: #define LMC_HAVE_NOMEDIA 0x00004000 /* did not detect any media */
424: #define LMC_HAVE_STOREFWD 0x00008000 /* have CMD_STOREFWD */
425: #define LMC_HAVE_SIA100 0x00010000 /* has LS100 in SIA status */
426:
427: #if 0
428: static const char * const lmc_status_bits[] = {
429: NULL,
430: "transmit process stopped",
431: NULL,
432: "transmit jabber timeout",
433:
434: NULL,
435: "transmit underflow",
436: NULL,
437: "receive underflow",
438:
439: "receive process stopped",
440: "receive watchdog timeout",
441: NULL,
442: NULL,
443:
444: "link failure",
445: NULL,
446: NULL,
447: };
448: #endif
449:
450: /*
451: * This driver supports a maximum of 32 devices.
452: */
453: #define LMC_MAX_DEVICES 32
454:
455: #define LMC_RXDESC_PRESYNC(sc, di, s) \
456: bus_dmamap_sync((sc)->lmc_dmatag, (sc)->lmc_rxdescmap, \
457: (caddr_t) di - (caddr_t) (sc)->lmc_rxdescs, \
458: (s), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)
459: #define LMC_RXDESC_POSTSYNC(sc, di, s) \
460: bus_dmamap_sync((sc)->lmc_dmatag, (sc)->lmc_rxdescmap, \
461: (caddr_t) di - (caddr_t) (sc)->lmc_rxdescs, \
462: (s), BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)
463: #define LMC_RXMAP_PRESYNC(sc, map) \
464: bus_dmamap_sync((sc)->lmc_dmatag, (map), 0, (map)->dm_mapsize, \
465: BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)
466: #define LMC_RXMAP_POSTSYNC(sc, map) \
467: bus_dmamap_sync((sc)->lmc_dmatag, (map), 0, (map)->dm_mapsize, \
468: BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)
469: #define LMC_RXMAP_CREATE(sc, mapp) \
470: bus_dmamap_create((sc)->lmc_dmatag, LMC_RX_BUFLEN, 2, \
471: LMC_DATA_PER_DESC, 0, \
472: BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, (mapp))
473:
474: #define LMC_TXDESC_PRESYNC(sc, di, s) \
475: bus_dmamap_sync((sc)->lmc_dmatag, (sc)->lmc_txdescmap, \
476: (caddr_t) di - (caddr_t) (sc)->lmc_txdescs, \
477: (s), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)
478: #define LMC_TXDESC_POSTSYNC(sc, di, s) \
479: bus_dmamap_sync((sc)->lmc_dmatag, (sc)->lmc_txdescmap, \
480: (caddr_t) di - (caddr_t) (sc)->lmc_txdescs, \
481: (s), BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)
482: #define LMC_TXMAP_PRESYNC(sc, map) \
483: bus_dmamap_sync((sc)->lmc_dmatag, (map), 0, (map)->dm_mapsize, \
484: BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)
485: #define LMC_TXMAP_POSTSYNC(sc, map) \
486: bus_dmamap_sync((sc)->lmc_dmatag, (map), 0, (map)->dm_mapsize, \
487: BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)
488: #define LMC_TXMAP_CREATE(sc, mapp) \
489: bus_dmamap_create((sc)->lmc_dmatag, LMC_DATA_PER_DESC, \
490: LMC_MAX_TXSEG, LMC_DATA_PER_DESC, \
491: 0, BUS_DMA_NOWAIT, (mapp))
492:
493: typedef void ifnet_ret_t;
494: typedef u_long ioctl_cmd_t;
495: extern struct cfattach lmc_ca;
496: extern struct cfdriver lmc_cd;
497: #define LMC_UNIT_TO_SOFTC(unit) ((lmc_softc_t *) lmc_cd.cd_devs[unit])
498: #define LMC_IFP_TO_SOFTC(ifp) ((lmc_softc_t *)((ifp)->if_softc))
499: #define lmc_unit lmc_dev.dv_unit
500: #define lmc_xname lmc_if.if_xname
501: #define LMC_RAISESPL() splnet()
502: #define LMC_RAISESOFTSPL() splsoftnet()
503: #define LMC_RESTORESPL(s) splx(s)
504: /* #define lmc_enaddr lmc_enaddr */
505: #define loudprintf printf
506: #define LMC_PRINTF_FMT "%s"
507: #define LMC_PRINTF_ARGS sc->lmc_xname
508:
509: #ifndef LMC_PRINTF_FMT
510: #define LMC_PRINTF_FMT "%s%d"
511: #endif
512: #ifndef LMC_PRINTF_ARGS
513: #define LMC_PRINTF_ARGS sc->lmc_name, sc->lmc_unit
514: #endif
515:
516: #ifndef LMC_BURSTSIZE
517: #define LMC_BURSTSIZE(unit) 3
518: #endif
519:
520: #ifndef lmc_unit
521: #define lmc_unit lmc_sppp.pp_if.if_unit
522: #endif
523:
524: #ifndef lmc_name
525: #define lmc_name lmc_sppp.pp_if.if_name
526: #endif
527:
528: #if !defined(lmc_bpf)
529: #define lmc_bpf lmc_sppp.pp_if.if_bpf
530: #endif
531:
532: #ifndef LMC_RAISESPL
533: #define LMC_RAISESPL() splnet()
534: #endif
535: #ifndef LMC_RAISESOFTSPL
536: #define LMC_RAISESOFTSPL() splnet()
537: #endif
538: #ifndef TULUP_RESTORESPL
539: #define LMC_RESTORESPL(s) splx(s)
540: #endif
541:
542: /*
543: * While I think FreeBSD's 2.2 change to the bpf is a nice simplification,
544: * it does add yet more conditional code to this driver. Sigh.
545: */
546: #if !defined(LMC_BPF_MTAP) && NBPFILTER > 0
547: #define LMC_BPF_MTAP(sc, m, d) bpf_mtap((sc)->lmc_bpf, m, d)
548: #define LMC_BPF_TAP(sc, p, l, d) bpf_tap((sc)->lmc_bpf, p, l, d)
549: #define LMC_BPF_ATTACH(sc) bpfattach(&(sc)->lmc_bpf, &(sc)->lmc_sppp.pp_if, DLT_PPP, PPP_HEADER_LEN)
550: #endif
551:
552: /*
553: * However, this change to FreeBSD I am much less enamored with.
554: */
555: #if !defined(LMC_EADDR_FMT)
556: #define LMC_EADDR_FMT "%s"
557: #define LMC_EADDR_ARGS(addr) ether_sprintf(addr)
558: #endif
559:
560: #define LMC_CRC32_POLY 0xEDB88320UL /* CRC-32 Poly -- Little Endian */
561: #define LMC_MAX_TXSEG 30
562:
563: #define LMC_ADDREQUAL(a1, a2) \
564: (((u_int16_t *)a1)[0] == ((u_int16_t *)a2)[0] \
565: && ((u_int16_t *)a1)[1] == ((u_int16_t *)a2)[1] \
566: && ((u_int16_t *)a1)[2] == ((u_int16_t *)a2)[2])
567: #define LMC_ADDRBRDCST(a1) \
568: (((u_int16_t *)a1)[0] == 0xFFFFU \
569: && ((u_int16_t *)a1)[1] == 0xFFFFU \
570: && ((u_int16_t *)a1)[2] == 0xFFFFU)
571:
572: typedef int lmc_spl_t;
573:
574: #define LMC_GETCTX(m, t) ((t) (m)->m_pkthdr.rcvif + 0)
575: #define LMC_SETCTX(m, c) ((void) ((m)->m_pkthdr.rcvif = (void *) (c)))
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