Annotation of sys/dev/pci/if_lmcioctl.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: if_lmcioctl.h,v 1.6 2005/11/07 00:29:21 brad Exp $ */
2: /* $Id: if_lmcioctl.h,v 1.6 2005/11/07 00:29:21 brad Exp $ */
3:
4: /*
5: * Copyright (c) 1997-1999 LAN Media Corporation (LMC)
6: * All rights reserved. www.lanmedia.com
7: *
8: * This code is written by Michael Graff <graff@vix.com> for LMC.
9: * The code is derived from permitted modifications to software created
10: * by Matt Thomas (matt@3am-software.com).
11: *
12: * Redistribution and use in source and binary forms, with or without
13: * modification, are permitted provided that the following conditions
14: * are met:
15: * 1. Redistributions of source code must retain the above copyright
16: * notice, this list of conditions and the following disclaimer.
17: * 2. Redistributions in binary form must reproduce the above
18: * copyright notice, this list of conditions and the following disclaimer
19: * in the documentation and/or other materials provided with the
20: * distribution.
21: * 3. All marketing or advertising materials mentioning features or
22: * use of this software must display the following acknowledgement:
23: * This product includes software developed by LAN Media Corporation
24: * and its contributors.
25: * 4. Neither the name of LAN Media Corporation nor the names of its
26: * contributors may be used to endorse or promote products derived
27: * from this software without specific prior written permission.
28: *
29: * THIS SOFTWARE IS PROVIDED BY LAN MEDIA CORPORATION AND CONTRIBUTORS
30: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
31: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
32: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
33: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
34: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
37: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39: * THE POSSIBILITY OF SUCH DAMAGE.
40: */
41:
42: /*
43: * IOCTLs for the sane world.
44: */
45: #define LMCIOCGINFO _IOW('i', 240, struct ifreq)
46: #define LMCIOCSINFO _IOWR('i', 241, struct ifreq)
47:
48: typedef struct {
49: u_int32_t n;
50: u_int32_t m;
51: u_int32_t v;
52: u_int32_t x;
53: u_int32_t r;
54: u_int32_t f;
55: u_int32_t exact;
56: } lmc_av9110_t;
57:
58: /*
59: * Common structure passed to the ioctl code.
60: */
61: struct lmc___ctl {
62: u_int32_t cardtype;
63: u_int32_t clock_source; /* HSSI, T1 */
64: u_int32_t clock_rate; /* T1 */
65: u_int32_t crc_length;
66: u_int32_t cable_length; /* DS3 */
67: u_int32_t scrambler_onoff; /* DS3 */
68: u_int32_t cable_type; /* T1 */
69: u_int32_t keepalive_onoff; /* protocol */
70: u_int32_t ticks; /* ticks/sec */
71: union {
72: lmc_av9110_t ssi;
73: } cardspec;
74: u_int32_t circuit_type; /* T1 or E1 */
75: };
76:
77: #define LMC_CARDTYPE_UNKNOWN -1
78: #define LMC_CARDTYPE_HSSI 1 /* probed card is a HSSI card */
79: #define LMC_CARDTYPE_DS3 2 /* probed card is a DS3 card */
80: #define LMC_CARDTYPE_SSI 3 /* probed card is a SSI card */
81: #define LMC_CARDTYPE_T1 4 /* probed card is a T1 card */
82:
83: #define LMC_CTL_CARDTYPE_LMC5200 0 /* HSSI */
84: #define LMC_CTL_CARDTYPE_LMC5245 1 /* DS3 */
85: #define LMC_CTL_CARDTYPE_LMC1000 2 /* SSI, V.35 */
86: #define LMC_CTL_CARDTYPE_LMC1200 3 /* DS1 */
87:
88: #define LMC_CTL_OFF 0 /* generic OFF value */
89: #define LMC_CTL_ON 1 /* generic ON value */
90:
91: #define LMC_CTL_CLOCK_SOURCE_EXT 0 /* clock off line */
92: #define LMC_CTL_CLOCK_SOURCE_INT 1 /* internal clock */
93:
94: #define LMC_CTL_CRC_LENGTH_16 16
95: #define LMC_CTL_CRC_LENGTH_32 32
96: #define LMC_CTL_CRC_BYTESIZE_2 2
97: #define LMC_CTL_CRC_BYTESIZE_4 4
98:
99: #define LMC_CTL_CABLE_LENGTH_LT_100FT 0 /* DS3 cable < 100 feet */
100: #define LMC_CTL_CABLE_LENGTH_GT_100FT 1 /* DS3 cable >= 100 feet */
101:
102: #define LMC_CTL_CIRCUIT_TYPE_E1 0
103: #define LMC_CTL_CIRCUIT_TYPE_T1 1
104:
105: /*
106: * These are not in the least IOCTL related, but I want them common.
107: */
108: /*
109: * assignments for the GPIO register on the DEC chip (common)
110: */
111: #define LMC_GEP_INIT 0x01 /* 0: */
112: #define LMC_GEP_RESET 0x02 /* 1: */
113: #define LMC_GEP_LOAD 0x10 /* 4: */
114: #define LMC_GEP_DP 0x20 /* 5: */
115: #define LMC_GEP_SERIAL 0x40 /* 6: serial out */
116: #define LMC_GEP_SERIALCLK 0x80 /* 7: serial clock */
117:
118: /*
119: * HSSI GPIO assignments
120: */
121: #define LMC_GEP_HSSI_ST 0x04 /* 2: receive timing sense (deprecated) */
122: #define LMC_GEP_HSSI_CLOCK 0x08 /* 3: clock source */
123:
124: /*
125: * T1 GPIO assignments
126: */
127: #define LMC_GEP_SSI_GENERATOR 0x04 /* 2: enable prog freq gen serial i/f */
128: #define LMC_GEP_SSI_TXCLOCK 0x08 /* 3: provide clock on TXCLOCK output */
129:
130: /*
131: * Common MII16 bits
132: */
133: #define LMC_MII16_LED0 0x0080
134: #define LMC_MII16_LED1 0x0100
135: #define LMC_MII16_LED2 0x0200
136: #define LMC_MII16_LED3 0x0400 /* Error, and the red one */
137: #define LMC_MII16_LED_ALL 0x0780 /* LED bit mask */
138: #define LMC_MII16_FIFO_RESET 0x0800
139:
140: /*
141: * definitions for HSSI
142: */
143: #define LMC_MII16_HSSI_TA 0x0001
144: #define LMC_MII16_HSSI_CA 0x0002
145: #define LMC_MII16_HSSI_LA 0x0004
146: #define LMC_MII16_HSSI_LB 0x0008
147: #define LMC_MII16_HSSI_LC 0x0010
148: #define LMC_MII16_HSSI_TM 0x0020
149: #define LMC_MII16_HSSI_CRC 0x0040
150:
151: /*
152: * assignments for the MII register 16 (DS3)
153: */
154: #define LMC_MII16_DS3_ZERO 0x0001
155: #define LMC_MII16_DS3_TRLBK 0x0002
156: #define LMC_MII16_DS3_LNLBK 0x0004
157: #define LMC_MII16_DS3_RAIS 0x0008
158: #define LMC_MII16_DS3_TAIS 0x0010
159: #define LMC_MII16_DS3_BIST 0x0020
160: #define LMC_MII16_DS3_DLOS 0x0040
161: #define LMC_MII16_DS3_CRC 0x1000
162: #define LMC_MII16_DS3_SCRAM 0x2000
163:
164: /* Note: 2 pairs of LEDs where swapped by mistake
165: * in Xilinx code for DS3 & DS1 adapters */
166: #define LMC_DS3_LED0 0x0100 /* bit 08 yellow */
167: #define LMC_DS3_LED1 0x0080 /* bit 07 blue */
168: #define LMC_DS3_LED2 0x0400 /* bit 10 green */
169: #define LMC_DS3_LED3 0x0200 /* bit 09 red */
170:
171: /*
172: * framer register 0 and 7 (7 is latched and reset on read)
173: */
174: #define LMC_FRAMER_REG0_DLOS 0x80 /* digital loss of service */
175: #define LMC_FRAMER_REG0_OOFS 0x40 /* out of frame sync */
176: #define LMC_FRAMER_REG0_AIS 0x20 /* alarm indication signal */
177: #define LMC_FRAMER_REG0_CIS 0x10 /* channel idle */
178: #define LMC_FRAMER_REG0_LOC 0x08 /* loss of clock */
179:
180: /*
181: * And SSI, LMC1000
182: */
183: #define LMC_MII16_SSI_DTR 0x0001 /* DTR output RW */
184: #define LMC_MII16_SSI_DSR 0x0002 /* DSR input RO */
185: #define LMC_MII16_SSI_RTS 0x0004 /* RTS output RW */
186: #define LMC_MII16_SSI_CTS 0x0008 /* CTS input RO */
187: #define LMC_MII16_SSI_DCD 0x0010 /* DCD input RO */
188: #define LMC_MII16_SSI_RI 0x0020 /* RI input RO */
189: #define LMC_MII16_SSI_CRC 0x1000 /* CRC select - RW */
190:
191: /*
192: * bits 0x0080 through 0x0800 are generic, and described
193: * above with LMC_MII16_LED[0123] _LED_ALL, and _FIFO_RESET
194: */
195: #define LMC_MII16_SSI_LL 0x1000 /* LL output RW */
196: #define LMC_MII16_SSI_RL 0x2000 /* RL output RW */
197: #define LMC_MII16_SSI_TM 0x4000 /* TM input RO */
198: #define LMC_MII16_SSI_LOOP 0x8000 /* loopback enable RW */
199:
200: /*
201: * Some of the MII16 bits are mirrored in the MII17 register as well,
202: * but let's keep thing separate for now, and get only the cable from
203: * the MII17.
204: */
205: #define LMC_MII17_SSI_CABLE_MASK 0x0038 /* mask to extract the cable type */
206: #define LMC_MII17_SSI_CABLE_SHIFT 3 /* shift to extract the cable type */
207:
208: /*
209: * And T1, LMC1200
210: */
211: #define LMC_MII16_T1_UNUSED1 0x0003
212: #define LMC_MII16_T1_XOE 0x0004
213: #define LMC_MII16_T1_RST 0x0008 /* T1 chip reset - RW */
214: #define LMC_MII16_T1_Z 0x0010 /* output impedance T1=1, E1=0 output - RW */
215: #define LMC_MII16_T1_INTR 0x0020 /* interrupt from 8370 - RO */
216: #define LMC_MII16_T1_ONESEC 0x0040 /* one second square wave - ro */
217:
218: #define LMC_MII16_T1_LED0 0x0100
219: #define LMC_MII16_T1_LED1 0x0080
220: #define LMC_MII16_T1_LED2 0x0400
221: #define LMC_MII16_T1_LED3 0x0200
222: #define LMC_MII16_T1_FIFO_RESET 0x0800
223:
224: #define LMC_MII16_T1_CRC 0x1000 /* CRC select - RW */
225: #define LMC_MII16_T1_UNUSED2 0xe000
226:
227: /* 8370 framer registers */
228:
229: #define T1FRAMER_ALARM1_STATUS 0x47
230: #define T1FRAMER_ALARM2_STATUS 0x48
231: #define T1FRAMER_FERR_LSB 0x50
232: #define T1FRAMER_FERR_MSB 0x51 /* framing bit error counter */
233: #define T1FRAMER_LCV_LSB 0x54
234: #define T1FRAMER_LCV_MSB 0x55 /* line code violation counter */
235: #define T1FRAMER_AERR 0x5A
236:
237: /* mask for the above AERR register */
238: #define T1FRAMER_LOF_MASK (0x0f0) /* receive loss of frame */
239: #define T1FRAMER_COFA_MASK (0x0c0) /* change of frame alignment */
240: #define T1FRAMER_SEF_MASK (0x03) /* severely errored frame */
241:
242: /* 8370 framer register ALM1 (0x47) values
243: * used to determine link status
244: */
245:
246: #define T1F_SIGFRZ 0x01 /* signaling freeze */
247: #define T1F_RLOF 0x02 /* receive loss of frame alignment */
248: #define T1F_RLOS 0x04 /* receive loss of signal */
249: #define T1F_RALOS 0x08 /* receive analog loss of signal or RCKI loss of clock */
250: #define T1F_RAIS 0x10 /* receive alarm indication signal */
251: #define T1F_UNUSED 0x20
252: #define T1F_RYEL 0x40 /* receive yellow alarm */
253: #define T1F_RMYEL 0x80 /* receive multiframe yellow alarm */
254:
255: /* ------------------ end T1 defs ------------------- */
256:
257: #define LMC_MII_LedMask 0x0780
258: #define LMC_MII_LedBitPos 7
259:
260: #if defined(_KERNEL)
261: /*
262: * media independent methods to check on media status, link, light LEDs,
263: * etc.
264: */
265: struct lmc___media {
266: void (* init)(lmc_softc_t * const);
267: void (* defaults)(lmc_softc_t * const);
268: void (* set_status)(lmc_softc_t * const, lmc_ctl_t *);
269: void (* set_clock_source)(lmc_softc_t * const, int);
270: void (* set_speed)(lmc_softc_t * const, lmc_ctl_t *);
271: void (* set_cable_length)(lmc_softc_t * const, int);
272: void (* set_scrambler)(lmc_softc_t * const, int);
273: int (* get_link_status)(lmc_softc_t * const);
274: void (* set_link_status)(lmc_softc_t * const, int);
275: void (* set_crc_length)(lmc_softc_t * const, int);
276: void (* set_circuit_type)(lmc_softc_t * const, int);
277: void (* watchdog)(lmc_softc_t * const);
278: };
279:
280: u_int32_t lmc_mii_readreg(lmc_softc_t * const sc, u_int32_t devaddr,
281: u_int32_t regno);
282: void lmc_mii_writereg(lmc_softc_t * const sc, u_int32_t devaddr,
283: u_int32_t regno, u_int32_t data);
284: void lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base,
285: size_t csr_size);
286: void lmc_dec_reset(lmc_softc_t * const sc);
287: void lmc_reset(lmc_softc_t * const sc);
288: void lmc_led_on(lmc_softc_t * const sc, u_int32_t led);
289: void lmc_led_off(lmc_softc_t * const sc, u_int32_t led);
290: void lmc_gpio_mkinput(lmc_softc_t * const sc, u_int32_t bits);
291: void lmc_gpio_mkoutput(lmc_softc_t * const sc, u_int32_t bits);
292: lmc_intrfunc_t lmc_intr_normal(void *);
293: int lmc_read_macaddr(lmc_softc_t * const sc);
294: void lmc_attach(lmc_softc_t * const sc);
295: void lmc_initring(lmc_softc_t * const sc, lmc_ringinfo_t * const ri,
296: lmc_desc_t *descs, int ndescs);
297: #endif /* _KERNEL */
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