Annotation of sys/dev/pci/if_ipwreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: if_ipwreg.h,v 1.14 2006/02/26 19:14:40 damien Exp $ */
2:
3: /*-
4: * Copyright (c) 2004-2006
5: * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice unmodified, this list of conditions, and the following
12: * disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: *
17: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20: * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27: * SUCH DAMAGE.
28: */
29:
30: #define IPW_NTBD 128
31: #define IPW_TBD_SZ (IPW_NTBD * sizeof (struct ipw_bd))
32: #define IPW_NDATA (IPW_NTBD / 2)
33: #define IPW_NRBD 128
34: #define IPW_RBD_SZ (IPW_NRBD * sizeof (struct ipw_bd))
35: #define IPW_STATUS_SZ (IPW_NRBD * sizeof (struct ipw_status))
36:
37: #define IPW_CSR_INTR 0x0008
38: #define IPW_CSR_INTR_MASK 0x000c
39: #define IPW_CSR_INDIRECT_ADDR 0x0010
40: #define IPW_CSR_INDIRECT_DATA 0x0014
41: #define IPW_CSR_AUTOINC_ADDR 0x0018
42: #define IPW_CSR_AUTOINC_DATA 0x001c
43: #define IPW_CSR_RST 0x0020
44: #define IPW_CSR_CTL 0x0024
45: #define IPW_CSR_IO 0x0030
46: #define IPW_CSR_TX_BD_BASE 0x0200
47: #define IPW_CSR_TX_BD_SIZE 0x0204
48: #define IPW_CSR_RX_BD_BASE 0x0240
49: #define IPW_CSR_RX_STATUS_BASE 0x0244
50: #define IPW_CSR_RX_BD_SIZE 0x0248
51: #define IPW_CSR_TX_READ_INDEX 0x0280
52: #define IPW_CSR_RX_READ_INDEX 0x02a0
53: #define IPW_CSR_TABLE1_BASE 0x0380
54: #define IPW_CSR_TABLE2_BASE 0x0384
55: #define IPW_CSR_TX_WRITE_INDEX 0x0f80
56: #define IPW_CSR_RX_WRITE_INDEX 0x0fa0
57:
58: /* possible flags for register IPW_CSR_INTR */
59: #define IPW_INTR_TX_TRANSFER 0x00000001
60: #define IPW_INTR_RX_TRANSFER 0x00000002
61: #define IPW_INTR_STATUS_CHANGE 0x00000010
62: #define IPW_INTR_COMMAND_DONE 0x00010000
63: #define IPW_INTR_FW_INIT_DONE 0x01000000
64: #define IPW_INTR_FATAL_ERROR 0x40000000
65: #define IPW_INTR_PARITY_ERROR 0x80000000
66:
67: #define IPW_INTR_MASK \
68: (IPW_INTR_TX_TRANSFER | IPW_INTR_RX_TRANSFER | \
69: IPW_INTR_STATUS_CHANGE | IPW_INTR_COMMAND_DONE | \
70: IPW_INTR_FW_INIT_DONE | IPW_INTR_FATAL_ERROR | \
71: IPW_INTR_PARITY_ERROR)
72:
73: /* possible flags for register IPW_CSR_RST */
74: #define IPW_RST_PRINCETON_RESET 0x00000001
75: #define IPW_RST_SW_RESET 0x00000080
76: #define IPW_RST_MASTER_DISABLED 0x00000100
77: #define IPW_RST_STOP_MASTER 0x00000200
78:
79: /* possible flags for register IPW_CSR_CTL */
80: #define IPW_CTL_CLOCK_READY 0x00000001
81: #define IPW_CTL_ALLOW_STANDBY 0x00000002
82: #define IPW_CTL_INIT 0x00000004
83:
84: /* possible flags for register IPW_CSR_IO */
85: #define IPW_IO_GPIO1_ENABLE 0x00000008
86: #define IPW_IO_GPIO1_MASK 0x0000000c
87: #define IPW_IO_GPIO3_MASK 0x000000c0
88: #define IPW_IO_LED_OFF 0x00002000
89: #define IPW_IO_RADIO_DISABLED 0x00010000
90:
91: #define IPW_STATE_ASSOCIATED 0x0004
92: #define IPW_STATE_ASSOCIATION_LOST 0x0008
93: #define IPW_STATE_SCAN_COMPLETE 0x0020
94: #define IPW_STATE_RADIO_DISABLED 0x0100
95: #define IPW_STATE_DISABLED 0x0200
96: #define IPW_STATE_SCANNING 0x0800
97:
98: /* table1 offsets */
99: #define IPW_INFO_LOCK 480
100: #define IPW_INFO_APS_CNT 604
101: #define IPW_INFO_APS_BASE 608
102: #define IPW_INFO_CARD_DISABLED 628
103: #define IPW_INFO_CURRENT_CHANNEL 756
104: #define IPW_INFO_CURRENT_TX_RATE 768
105:
106: /* table2 offsets */
107: #define IPW_INFO_CURRENT_SSID 48
108: #define IPW_INFO_CURRENT_BSSID 112
109:
110: /* supported rates */
111: #define IPW_RATE_DS1 1
112: #define IPW_RATE_DS2 2
113: #define IPW_RATE_DS5 4
114: #define IPW_RATE_DS11 8
115:
116: /* firmware binary image header */
117: struct ipw_firmware_hdr {
118: uint32_t version;
119: uint32_t main_size; /* firmware size */
120: uint32_t ucode_size; /* microcode size */
121: } __packed;
122:
123: /* buffer descriptor */
124: struct ipw_bd {
125: uint32_t physaddr;
126: uint32_t len;
127: uint8_t flags;
128: #define IPW_BD_FLAG_TX_FRAME_802_3 0x00
129: #define IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT 0x01
130: #define IPW_BD_FLAG_TX_FRAME_COMMAND 0x02
131: #define IPW_BD_FLAG_TX_FRAME_802_11 0x04
132: #define IPW_BD_FLAG_TX_LAST_FRAGMENT 0x08
133: uint8_t nfrag; /* number of fragments */
134: uint8_t reserved[6];
135: } __packed;
136:
137: /* status */
138: struct ipw_status {
139: uint32_t len;
140: uint16_t code;
141: #define IPW_STATUS_CODE_COMMAND 0
142: #define IPW_STATUS_CODE_NEWSTATE 1
143: #define IPW_STATUS_CODE_DATA_802_11 2
144: #define IPW_STATUS_CODE_DATA_802_3 3
145: #define IPW_STATUS_CODE_NOTIFICATION 4
146: uint8_t flags;
147: #define IPW_STATUS_FLAG_DECRYPTED 0x01
148: #define IPW_STATUS_FLAG_WEP_ENCRYPTED 0x02
149: uint8_t rssi; /* received signal strength indicator */
150: } __packed;
151:
152: /* data header */
153: struct ipw_hdr {
154: uint32_t type;
155: #define IPW_HDR_TYPE_SEND 33
156: uint32_t subtype;
157: uint8_t encrypted;
158: uint8_t encrypt;
159: uint8_t keyidx;
160: uint8_t keysz;
161: uint8_t key[IEEE80211_KEYBUF_SIZE];
162: uint8_t reserved[10];
163: uint8_t src_addr[IEEE80211_ADDR_LEN];
164: uint8_t dst_addr[IEEE80211_ADDR_LEN];
165: uint16_t fragmentsz;
166: } __packed;
167:
168: /* command */
169: struct ipw_cmd {
170: uint32_t type;
171: #define IPW_CMD_ENABLE 2
172: #define IPW_CMD_SET_CONFIGURATION 6
173: #define IPW_CMD_SET_ESSID 8
174: #define IPW_CMD_SET_MANDATORY_BSSID 9
175: #define IPW_CMD_SET_MAC_ADDRESS 11
176: #define IPW_CMD_SET_MODE 12
177: #define IPW_CMD_SET_CHANNEL 14
178: #define IPW_CMD_SET_RTS_THRESHOLD 15
179: #define IPW_CMD_SET_FRAG_THRESHOLD 16
180: #define IPW_CMD_SET_POWER_MODE 17
181: #define IPW_CMD_SET_TX_RATES 18
182: #define IPW_CMD_SET_BASIC_TX_RATES 19
183: #define IPW_CMD_SET_WEP_KEY 20
184: #define IPW_CMD_SET_WEP_KEY_INDEX 25
185: #define IPW_CMD_SET_WEP_FLAGS 26
186: #define IPW_CMD_ADD_MULTICAST 27
187: #define IPW_CMD_SET_BEACON_INTERVAL 29
188: #define IPW_CMD_SET_TX_POWER_INDEX 36
189: #define IPW_CMD_BROADCAST_SCAN 43
190: #define IPW_CMD_DISABLE 44
191: #define IPW_CMD_SET_DESIRED_BSSID 45
192: #define IPW_CMD_SET_SCAN_OPTIONS 46
193: #define IPW_CMD_PREPARE_POWER_DOWN 58
194: #define IPW_CMD_DISABLE_PHY 61
195: #define IPW_CMD_SET_SECURITY_INFORMATION 67
196: uint32_t subtype;
197: uint32_t seq;
198: uint32_t len;
199: uint8_t data[400];
200: uint32_t status;
201: uint8_t reserved[68];
202: } __packed;
203:
204: /* possible values for command IPW_CMD_SET_POWER_MODE */
205: #define IPW_POWER_MODE_CAM 0
206: #define IPW_POWER_AUTOMATIC 6
207:
208: /* possible values for command IPW_CMD_SET_MODE */
209: #define IPW_MODE_BSS 0
210: #define IPW_MODE_IBSS 1
211: #define IPW_MODE_MONITOR 2
212:
213: /* possible flags for command IPW_CMD_SET_WEP_FLAGS */
214: #define IPW_WEPON 0x8
215:
216: /* structure for command IPW_CMD_SET_WEP_KEY */
217: struct ipw_wep_key {
218: uint8_t idx;
219: uint8_t len;
220: uint8_t key[13];
221: } __packed;
222:
223: /* structure for command IPW_CMD_SET_SECURITY_INFORMATION */
224: struct ipw_security {
225: uint32_t ciphers;
226: #define IPW_CIPHER_NONE 0x00000001
227: #define IPW_CIPHER_WEP40 0x00000002
228: #define IPW_CIPHER_WEP104 0x00000020
229: uint16_t reserved1;
230: uint8_t authmode;
231: #define IPW_AUTH_OPEN 0
232: #define IPW_AUTH_SHARED 1
233: uint16_t reserved2;
234: } __packed;
235:
236: /* structure for command IPW_CMD_SET_SCAN_OPTIONS */
237: struct ipw_scan_options {
238: uint32_t flags;
239: #define IPW_SCAN_DO_NOT_ASSOCIATE 0x00000001
240: #define IPW_SCAN_PASSIVE 0x00000008
241: uint32_t channels;
242: } __packed;
243:
244: /* structure for command IPW_CMD_SET_CONFIGURATION */
245: struct ipw_configuration {
246: uint32_t flags;
247: #define IPW_CFG_PROMISCUOUS 0x00000004
248: #define IPW_CFG_PREAMBLE_AUTO 0x00000010
249: #define IPW_CFG_IBSS_AUTO_START 0x00000020
250: #define IPW_CFG_802_1x_ENABLE 0x00004000
251: #define IPW_CFG_BSS_MASK 0x00008000
252: #define IPW_CFG_IBSS_MASK 0x00010000
253: uint32_t bss_chan;
254: uint32_t ibss_chan;
255: } __packed;
256:
257: /* EEPROM = Electrically Erasable Programmable Read-Only Memory */
258:
259: #define IPW_MEM_EEPROM_CTL 0x00300040
260:
261: #define IPW_EEPROM_MAC 0x21
262:
263: #define IPW_EEPROM_DELAY 1 /* minimum hold time (microsecond) */
264:
265: #define IPW_EEPROM_C (1 << 0) /* Serial Clock */
266: #define IPW_EEPROM_S (1 << 1) /* Chip Select */
267: #define IPW_EEPROM_D (1 << 2) /* Serial data input */
268: #define IPW_EEPROM_Q (1 << 4) /* Serial data output */
269:
270: #define IPW_EEPROM_SHIFT_D 2
271: #define IPW_EEPROM_SHIFT_Q 4
272:
273: /*
274: * control and status registers access macros
275: */
276: #define CSR_READ_1(sc, reg) \
277: bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
278:
279: #define CSR_READ_2(sc, reg) \
280: bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
281:
282: #define CSR_READ_4(sc, reg) \
283: bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
284:
285: #define CSR_WRITE_1(sc, reg, val) \
286: bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
287:
288: #define CSR_WRITE_2(sc, reg, val) \
289: bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
290:
291: #define CSR_WRITE_4(sc, reg, val) \
292: bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
293:
294: #define CSR_WRITE_MULTI_1(sc, reg, buf, len) \
295: bus_space_write_multi_1((sc)->sc_st, (sc)->sc_sh, (reg), \
296: (buf), (len))
297:
298: /*
299: * indirect memory space access macros
300: */
301: #define MEM_WRITE_1(sc, addr, val) do { \
302: CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
303: CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \
304: } while (/* CONSTCOND */0)
305:
306: #define MEM_WRITE_2(sc, addr, val) do { \
307: CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
308: CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \
309: } while (/* CONSTCOND */0)
310:
311: #define MEM_WRITE_4(sc, addr, val) do { \
312: CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
313: CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \
314: } while (/* CONSTCOND */0)
315:
316: #define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \
317: CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
318: CSR_WRITE_MULTI_1((sc), IPW_CSR_INDIRECT_DATA, (buf), (len)); \
319: } while (/* CONSTCOND */0)
320:
321: /*
322: * EEPROM access macro
323: */
324: #define IPW_EEPROM_CTL(sc, val) do { \
325: MEM_WRITE_4((sc), IPW_MEM_EEPROM_CTL, (val)); \
326: DELAY(IPW_EEPROM_DELAY); \
327: } while (0)
328:
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