Annotation of sys/dev/pci/hifn7751reg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: hifn7751reg.h,v 1.45 2005/09/06 18:27:54 jolan Exp $ */
2:
3: /*
4: * Invertex AEON / Hifn 7751 driver
5: * Copyright (c) 1999 Invertex Inc. All rights reserved.
6: * Copyright (c) 1999 Theo de Raadt
7: * Copyright (c) 2000-2001 Network Security Technologies, Inc.
8: * http://www.netsec.net
9: *
10: * Please send any comments, feedback, bug-fixes, or feature requests to
11: * software@invertex.com.
12: *
13: * Redistribution and use in source and binary forms, with or without
14: * modification, are permitted provided that the following conditions
15: * are met:
16: *
17: * 1. Redistributions of source code must retain the above copyright
18: * notice, this list of conditions and the following disclaimer.
19: * 2. Redistributions in binary form must reproduce the above copyright
20: * notice, this list of conditions and the following disclaimer in the
21: * documentation and/or other materials provided with the distribution.
22: * 3. The name of the author may not be used to endorse or promote products
23: * derived from this software without specific prior written permission.
24: *
25: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
26: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
27: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
29: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
30: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
34: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35: *
36: * Effort sponsored in part by the Defense Advanced Research Projects
37: * Agency (DARPA) and Air Force Research Laboratory, Air Force
38: * Materiel Command, USAF, under agreement number F30602-01-2-0537.
39: *
40: */
41: #ifndef __HIFN_H__
42: #define __HIFN_H__
43:
44: #include <machine/endian.h>
45:
46: /*
47: * Some PCI configuration space offset defines. The names were made
48: * identical to the names used by the Linux kernel.
49: */
50: #define HIFN_BAR0 (PCI_MAPREG_START + 0) /* PUC register map */
51: #define HIFN_BAR1 (PCI_MAPREG_START + 4) /* DMA register map */
52: #define HIFN_RETRY_TIMEOUT 0x41
53: #define HIFN_TRDY_TIMEOUT 0x40
54:
55: /*
56: * The values below should multiple of 4 -- and be large enough to handle
57: * any command the driver implements.
58: *
59: * MAX_COMMAND = base command + mac command + encrypt command +
60: * mac-key + rc4-key
61: * MAX_RESULT = base result + comp result + mac result + mac + encrypt result
62: *
63: *
64: */
65: #define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260)
66: #define HIFN_MAX_RESULT (8 + 4 + 4 + 20 + 4)
67:
68: /*
69: * hifn_desc_t
70: *
71: * Holds an individual descriptor for any of the rings.
72: */
73: struct hifn_desc {
74: volatile u_int32_t l; /* length and status bits */
75: volatile u_int32_t p;
76: };
77:
78: /*
79: * Masks for the "length" field of struct hifn_desc.
80: */
81: #define HIFN_D_LENGTH 0x0000ffff /* length bit mask */
82: #define HIFN_D_MASKDONEIRQ 0x02000000 /* mask the done interrupt */
83: #define HIFN_D_DESTOVER 0x04000000 /* destination overflow */
84: #define HIFN_D_OVER 0x08000000 /* overflow */
85: #define HIFN_D_LAST 0x20000000 /* last descriptor in chain */
86: #define HIFN_D_JUMP 0x40000000 /* jump descriptor */
87: #define HIFN_D_VALID 0x80000000 /* valid bit */
88:
89: /*
90: * Processing Unit Registers (offset from BASEREG0)
91: */
92: #define HIFN_0_PUDATA 0x00 /* Processing Unit Data */
93: #define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */
94: #define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */
95: #define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */
96: #define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */
97: #define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */
98: #define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */
99: #define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */
100: #define HIFN_0_SPACESIZE 0x20 /* Register space size */
101:
102: /* Processing Unit Control Register (HIFN_0_PUCTRL) */
103: #define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */
104: #define HIFN_PUCTRL_STOP 0x0008 /* stop pu */
105: #define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */
106: #define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */
107: #define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */
108:
109: /* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */
110: #define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */
111: #define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */
112: #define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
113: #define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
114: #define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */
115: #define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */
116: #define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */
117: #define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */
118: #define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */
119: #define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */
120:
121: /* Processing Unit Configuration Register (HIFN_0_PUCNFG) */
122: #define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */
123: #define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */
124: #define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */
125: #define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */
126: #define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */
127: #define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */
128: #define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */
129: #define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */
130: #define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */
131: #define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */
132: #define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */
133: #define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */
134: #define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */
135: #define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */
136: #define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */
137: #define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */
138: #define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */
139: #define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */
140: #define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */
141: #define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */
142: #define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */
143: #define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */
144: #define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */
145:
146: /* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */
147: #define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */
148: #define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */
149: #define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
150: #define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
151: #define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */
152: #define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */
153: #define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */
154: #define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */
155: #define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */
156: #define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */
157:
158: /* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */
159: #define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */
160: #define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */
161: #define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
162: #define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
163: #define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */
164: #define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */
165: #define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */
166: #define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */
167: #define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */
168: #define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */
169: #define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */
170: #define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */
171: #define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */
172: #define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */
173: #define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */
174: #define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */
175: #define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */
176:
177: /* FIFO Status Register (HIFN_0_FIFOSTAT) */
178: #define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */
179: #define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */
180:
181: /* FIFO Configuration Register (HIFN_0_FIFOCNFG) */
182: #define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as 1 */
183:
184: /*
185: * DMA Interface Registers (offset from BASEREG1)
186: */
187: #define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */
188: #define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */
189: #define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */
190: #define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */
191: #define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */
192: #define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */
193: #define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */
194: #define HIFN_1_PLL 0x4c /* 795x: PLL config */
195: #define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */
196: #define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */
197: #define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */
198: #define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */
199: #define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */
200: #define HIFN_1_REVID 0x98 /* Revision ID */
201: #define HIFN_1_UNLOCK_SECRET1 0xf4
202: #define HIFN_1_UNLOCK_SECRET2 0xfc
203: #define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */
204: #define HIFN_1_PUB_BASE 0x300 /* Public Base Address */
205: #define HIFN_1_PUB_OPLEN 0x304 /* Public Operand Length */
206: #define HIFN_1_PUB_OP 0x308 /* Public Operand */
207: #define HIFN_1_PUB_STATUS 0x30c /* Public Status */
208: #define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */
209: #define HIFN_1_RNG_CONFIG 0x314 /* RNG config */
210: #define HIFN_1_RNG_DATA 0x318 /* RNG data */
211: #define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */
212: #define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */
213:
214: /* DMA Status and Control Register (HIFN_1_DMA_CSR) */
215: #define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */
216: #define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */
217: #define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */
218: #define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */
219: #define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */
220: #define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */
221: #define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */
222: #define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */
223: #define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */
224: #define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */
225: #define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */
226: #define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */
227: #define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */
228: #define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */
229: #define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */
230: #define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */
231: #define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */
232: #define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */
233: #define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */
234: #define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */
235: #define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */
236: #define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */
237: #define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */
238: #define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */
239: #define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */
240: #define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */
241: #define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */
242: #define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */
243: #define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */
244: #define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */
245: #define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */
246: #define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */
247: #define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */
248: #define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */
249: #define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */
250: #define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */
251: #define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */
252: #define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */
253:
254: /* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */
255: #define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */
256: #define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */
257: #define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */
258: #define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */
259: #define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */
260: #define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */
261: #define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */
262: #define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */
263: #define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */
264: #define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */
265: #define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */
266: #define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */
267: #define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */
268: #define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */
269: #define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */
270: #define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */
271: #define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */
272: #define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */
273: #define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */
274: #define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */
275: #define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */
276: #define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */
277:
278: /* DMA Configuration Register (HIFN_1_DMA_CNFG) */
279: #define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */
280: #define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */
281: #define HIFN_DMACNFG_UNLOCK 0x00000800
282: #define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */
283: #define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */
284: #define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */
285: #define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */
286: #define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */
287:
288: /* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */
289: #define HIFN_7811_RNGENA_ENA 0x00000001 /* enable RNG */
290:
291: /* 7811 RNG Config Register (HIFN_1_7811_RNGCFG) */
292: #define HIFN_7811_RNGCFG_PRE1 0x00000f00 /* first prescalar */
293: #define HIFN_7811_RNGCFG_OPRE 0x00000080 /* output prescalar */
294: #define HIFN_7811_RNGCFG_DEFL 0x00000f80 /* 2 words/ 1/100 sec */
295:
296: /* 7811 RNG Status Register (HIFN_1_7811_RNGSTS) */
297: #define HIFN_7811_RNGSTS_RDY 0x00004000 /* two numbers in FIFO */
298: #define HIFN_7811_RNGSTS_UFL 0x00001000 /* rng underflow */
299:
300: /* 7811 MIPS Reset Register (HIFN_1_7811_MIPSRST) */
301: #define HIFN_MIPSRST_BAR2SIZE 0xffff0000 /* sdram size */
302: #define HIFN_MIPSRST_GPRAMINIT 0x00008000 /* gpram can be accessed */
303: #define HIFN_MIPSRST_CRAMINIT 0x00004000 /* ctxram can be accessed */
304: #define HIFN_MIPSRST_LED2 0x00000400 /* external LED2 */
305: #define HIFN_MIPSRST_LED1 0x00000200 /* external LED1 */
306: #define HIFN_MIPSRST_LED0 0x00000100 /* external LED0 */
307: #define HIFN_MIPSRST_MIPSDIS 0x00000004 /* disable MIPS */
308: #define HIFN_MIPSRST_MIPSRST 0x00000002 /* warm reset MIPS */
309: #define HIFN_MIPSRST_MIPSCOLD 0x00000001 /* cold reset MIPS */
310:
311: /* PLL config register (HIFN_1_PLL) */
312: #define HIFN_PLL_7956 0x00001d18 /* 7956 PLL config value */
313:
314: /* Revision ID */
315: #define HIFN_REVID_7811_PB3_2 0x00000002 /* 7811PB3/2 */
316:
317: /* Public key reset register (HIFN_1_PUB_RESET) */
318: #define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */
319:
320: /* Public base address register (HIFN_1_PUB_BASE) */
321: #define HIFN_PUBBASE_ADDR 0x00003fff /* base address */
322:
323: /* Public operand length register (HIFN_1_PUB_OPLEN) */
324: #define HIFN_PUBOPLEN_MOD_M 0x0000007f /* modulus length mask */
325: #define HIFN_PUBOPLEN_MOD_S 0 /* modulus length shift */
326: #define HIFN_PUBOPLEN_EXP_M 0x0003ff80 /* exponent length mask */
327: #define HIFN_PUBOPLEN_EXP_S 7 /* exponent length shift */
328: #define HIFN_PUBOPLEN_RED_M 0x003c0000 /* reducend length mask */
329: #define HIFN_PUBOPLEN_RED_S 18 /* reducend length shift */
330:
331: /* Public operation register (HIFN_1_PUB_OP) */
332: #define HIFN_PUBOP_AOFFSET_M 0x0000007f /* A offset mask */
333: #define HIFN_PUBOP_AOFFSET_S 0 /* A offset shift */
334: #define HIFN_PUBOP_BOFFSET_M 0x00000f80 /* B offset mask */
335: #define HIFN_PUBOP_BOFFSET_S 7 /* B offset shift */
336: #define HIFN_PUBOP_MOFFSET_M 0x0003f000 /* M offset mask */
337: #define HIFN_PUBOP_MOFFSET_S 12 /* M offset shift */
338: #define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */
339: #define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */
340: #define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */
341: #define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */
342: #define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */
343: #define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */
344: #define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */
345: #define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */
346: #define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */
347: #define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */
348: #define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */
349: #define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */
350: #define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular RED */
351: #define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular EXP */
352:
353: /* Public status register (HIFN_1_PUB_STATUS) */
354: #define HIFN_PUBSTS_DONE 0x00000001 /* operation done */
355: #define HIFN_PUBSTS_CARRY 0x00000002 /* carry */
356:
357: /* Public interrupt enable register (HIFN_1_PUB_IEN) */
358: #define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */
359:
360: /* Random number generator config register (HIFN_1_RNG_CONFIG) */
361: #define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */
362:
363: /*********************************************************************
364: * Structs for board commands
365: *
366: *********************************************************************/
367:
368: /*
369: * Structure to help build up the command data structure.
370: */
371: struct hifn_base_command {
372: volatile u_int16_t masks;
373: volatile u_int16_t session_num;
374: volatile u_int16_t total_source_count;
375: volatile u_int16_t total_dest_count;
376: };
377:
378: #define HIFN_BASE_CMD_COMP 0x0100 /* enable compression engine */
379: #define HIFN_BASE_CMD_PAD 0x0200 /* enable padding engine */
380: #define HIFN_BASE_CMD_MAC 0x0400 /* enable MAC engine */
381: #define HIFN_BASE_CMD_CRYPT 0x0800 /* enable crypt engine */
382: #define HIFN_BASE_CMD_DECODE 0x2000
383: #define HIFN_BASE_CMD_SRCLEN_M 0xc000
384: #define HIFN_BASE_CMD_SRCLEN_S 14
385: #define HIFN_BASE_CMD_DSTLEN_M 0x3000
386: #define HIFN_BASE_CMD_DSTLEN_S 12
387: #define HIFN_BASE_CMD_LENMASK_HI 0x30000
388: #define HIFN_BASE_CMD_LENMASK_LO 0x0ffff
389:
390: /*
391: * Structure to help build up the command data structure.
392: */
393: struct hifn_crypt_command {
394: volatile u_int16_t masks;
395: volatile u_int16_t header_skip;
396: volatile u_int16_t source_count;
397: volatile u_int16_t reserved;
398: };
399:
400: #define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */
401: #define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */
402: #define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */
403: #define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */
404: #define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */
405: #define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */
406: #define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */
407: #define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */
408: #define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */
409: #define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */
410: #define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */
411: #define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */
412: #define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */
413: #define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */
414: #define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */
415: #define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */
416: #define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */
417: #define HIFN_CRYPT_CMD_SRCLEN_M 0xc000
418: #define HIFN_CRYPT_CMD_SRCLEN_S 14
419:
420: /*
421: * Structure to help build up the command data structure.
422: */
423: struct hifn_mac_command {
424: volatile u_int16_t masks;
425: volatile u_int16_t header_skip;
426: volatile u_int16_t source_count;
427: volatile u_int16_t reserved;
428: };
429:
430: #define HIFN_MAC_CMD_ALG_MASK 0x0001
431: #define HIFN_MAC_CMD_ALG_SHA1 0x0000
432: #define HIFN_MAC_CMD_ALG_MD5 0x0001
433: #define HIFN_MAC_CMD_MODE_MASK 0x000c
434: #define HIFN_MAC_CMD_MODE_HMAC 0x0000
435: #define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004
436: #define HIFN_MAC_CMD_MODE_HASH 0x0008
437: #define HIFN_MAC_CMD_MODE_FULL 0x0004
438: #define HIFN_MAC_CMD_TRUNC 0x0010
439: #define HIFN_MAC_CMD_RESULT 0x0020
440: #define HIFN_MAC_CMD_APPEND 0x0040
441: #define HIFN_MAC_CMD_SRCLEN_M 0xc000
442: #define HIFN_MAC_CMD_SRCLEN_S 14
443:
444: /*
445: * MAC POS IPsec initiates authentication after encryption on encodes
446: * and before decryption on decodes.
447: */
448: #define HIFN_MAC_CMD_POS_IPSEC 0x0200
449: #define HIFN_MAC_CMD_NEW_KEY 0x0800
450:
451: struct hifn_comp_command {
452: volatile u_int16_t masks;
453: volatile u_int16_t header_skip;
454: volatile u_int16_t source_count;
455: volatile u_int16_t reserved;
456: };
457:
458: #define HIFN_COMP_CMD_SRCLEN_M 0xc000
459: #define HIFN_COMP_CMD_SRCLEN_S 14
460: #define HIFN_COMP_CMD_ONE 0x0100 /* must be one */
461: #define HIFN_COMP_CMD_CLEARHIST 0x0010 /* clear history */
462: #define HIFN_COMP_CMD_UPDATEHIST 0x0008 /* update history */
463: #define HIFN_COMP_CMD_LZS_STRIP0 0x0004 /* LZS: strip zero */
464: #define HIFN_COMP_CMD_MPPC_RESTART 0x0004 /* MPPC: restart */
465: #define HIFN_COMP_CMD_ALG_MASK 0x0001 /* compression mode: */
466: #define HIFN_COMP_CMD_ALG_MPPC 0x0001 /* MPPC */
467: #define HIFN_COMP_CMD_ALG_LZS 0x0000 /* LZS */
468:
469: struct hifn_base_result {
470: volatile u_int16_t flags;
471: volatile u_int16_t session;
472: volatile u_int16_t src_cnt; /* 15:0 of source count */
473: volatile u_int16_t dst_cnt; /* 15:0 of dest count */
474: };
475:
476: #define HIFN_BASE_RES_DSTOVERRUN 0x0200 /* destination overrun */
477: #define HIFN_BASE_RES_SRCLEN_M 0xc000 /* 17:16 of source count */
478: #define HIFN_BASE_RES_SRCLEN_S 14
479: #define HIFN_BASE_RES_DSTLEN_M 0x3000 /* 17:16 of dest count */
480: #define HIFN_BASE_RES_DSTLEN_S 12
481:
482: struct hifn_comp_result {
483: volatile u_int16_t flags;
484: volatile u_int16_t crc;
485: };
486:
487: #define HIFN_COMP_RES_LCB_M 0xff00 /* longitudinal check byte */
488: #define HIFN_COMP_RES_LCB_S 8
489: #define HIFN_COMP_RES_RESTART 0x0004 /* MPPC: restart */
490: #define HIFN_COMP_RES_ENDMARKER 0x0002 /* LZS: end marker seen */
491: #define HIFN_COMP_RES_SRC_NOTZERO 0x0001 /* source expired */
492:
493: struct hifn_mac_result {
494: volatile u_int16_t flags;
495: volatile u_int16_t reserved;
496: /* followed by 0, 6, 8, or 10 u_int16_t's of the MAC, then crypt */
497: };
498:
499: #define HIFN_MAC_RES_MISCOMPARE 0x0002 /* compare failed */
500: #define HIFN_MAC_RES_SRC_NOTZERO 0x0001 /* source expired */
501:
502: struct hifn_crypt_result {
503: volatile u_int16_t flags;
504: volatile u_int16_t reserved;
505: };
506:
507: #define HIFN_CRYPT_RES_SRC_NOTZERO 0x0001 /* source expired */
508:
509: /*
510: * The poll frequency and poll scalar defines are unshifted values used
511: * to set fields in the DMA Configuration Register.
512: */
513: #ifndef HIFN_POLL_FREQUENCY
514: #define HIFN_POLL_FREQUENCY 0x1
515: #endif
516:
517: #ifndef HIFN_POLL_SCALAR
518: #define HIFN_POLL_SCALAR 0x0
519: #endif
520:
521: #define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */
522: #define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */
523: #endif /* __HIFN_H__ */
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