Annotation of sys/dev/pci/emuxkireg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: emuxkireg.h,v 1.5 2006/02/06 22:12:39 jmc Exp $ */
! 2: /* $NetBSD: emuxkireg.h,v 1.1 2001/10/17 18:39:41 jdolecek Exp $ */
! 3:
! 4: /*-
! 5: * Copyright (c) 2001 The NetBSD Foundation, Inc.
! 6: * All rights reserved.
! 7: *
! 8: * This code is derived from software contributed to The NetBSD Foundation
! 9: * by Yannick Montulet.
! 10: *
! 11: * Redistribution and use in source and binary forms, with or without
! 12: * modification, are permitted provided that the following conditions
! 13: * are met:
! 14: * 1. Redistributions of source code must retain the above copyright
! 15: * notice, this list of conditions and the following disclaimer.
! 16: * 2. Redistributions in binary form must reproduce the above copyright
! 17: * notice, this list of conditions and the following disclaimer in the
! 18: * documentation and/or other materials provided with the distribution.
! 19: * 3. All advertising materials mentioning features or use of this software
! 20: * must display the following acknowledgement:
! 21: * This product includes software developed by the NetBSD
! 22: * Foundation, Inc. and its contributors.
! 23: * 4. Neither the name of The NetBSD Foundation nor the names of its
! 24: * contributors may be used to endorse or promote products derived
! 25: * from this software without specific prior written permission.
! 26: *
! 27: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
! 28: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
! 29: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
! 30: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
! 31: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
! 32: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
! 33: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
! 34: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
! 35: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
! 36: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 37: * POSSIBILITY OF SUCH DAMAGE.
! 38: */
! 39:
! 40: #ifndef _DEV_PCI_EMUXKIREG_H_
! 41: #define _DEV_PCI_EMUXKIREG_H_
! 42:
! 43: /*
! 44: * Register values for Creative EMU10000. The register values have been
! 45: * taken from GPLed SBLive! header file published by Creative. The comments
! 46: * have been stripped to avoid GPL pollution in kernel. The Creative version
! 47: * including comments is available in Linux 2.4.* kernel as file
! 48: * drivers/sound/emu10k1/8010.h
! 49: */
! 50:
! 51: /*
! 52: * Audigy specific registers contain an '_A_'
! 53: * Audigy2 specific registers contain an '_A2_'
! 54: */
! 55:
! 56: #define EMU_MKSUBREG(sz, idx, reg) (((sz) << 24) | ((idx) << 16) | (reg))
! 57:
! 58: #define EMU_PTR 0x00
! 59: #define EMU_PTR_CHNO_MASK 0x0000003f
! 60: #define EMU_PTR_ADDR_MASK 0x07ff0000
! 61: #define EMU_A_PTR_ADDR_MASK 0x0fff0000
! 62:
! 63: #define EMU_DATA 0x04
! 64:
! 65: #define EMU_IPR 0x08
! 66: #define EMU_IPR_RATETRCHANGE 0x01000000
! 67: #define EMU_IPR_FXDSP 0x00800000
! 68: #define EMU_IPR_FORCEINT 0x00400000
! 69: #define EMU_PCIERROR 0x00200000
! 70: #define EMU_IPR_VOLINCR 0x00100000
! 71: #define EMU_IPR_VOLDECR 0x00080000
! 72: #define EMU_IPR_MUTE 0x00040000
! 73: #define EMU_IPR_MICBUFFULL 0x00020000
! 74: #define EMU_IPR_MICBUFHALFFULL 0x00010000
! 75: #define EMU_IPR_ADCBUFFULL 0x00008000
! 76: #define EMU_IPR_ADCBUFHALFFULL 0x00004000
! 77: #define EMU_IPR_EFXBUFFULL 0x00002000
! 78: #define EMU_IPR_EFXBUFHALFFULL 0x00001000
! 79: #define EMU_IPR_GPSPDIFSTCHANGE 0x00000800
! 80: #define EMU_IPR_CDROMSTCHANGE 0x00000400
! 81: #define EMU_IPR_INTERVALTIMER 0x00000200
! 82: #define EMU_IPR_MIDITRANSBUFE 0x00000100
! 83: #define EMU_IPR_MIDIRECVBUFE 0x00000080
! 84: #define EMU_IPR_A_MIDITRANSBUFE2 0x10000000
! 85: #define EMU_IPR_A_MIDIRECBUFE2 0x08000000
! 86: #define EMU_IPR_CHANNELLOOP 0x00000040
! 87: #define EMU_IPR_CHNOMASK 0x0000003f
! 88:
! 89: #define EMU_INTE 0x0c
! 90:
! 91: #define EMU_INTE_VSB_MASK 0xc0000000
! 92: #define EMU_INTE_VSB_220 0x00000000
! 93: #define EMU_INTE_VSB_240 0x40000000
! 94: #define EMU_INTE_VSB_260 0x80000000
! 95: #define EMU_INTE_VSB_280 0xc0000000
! 96:
! 97: #define EMU_INTE_VMPU_MASK 0x30000000
! 98: #define EMU_INTE_VMPU_300 0x00000000
! 99: #define EMU_INTE_VMPU_310 0x10000000
! 100: #define EMU_INTE_VMPU_320 0x20000000
! 101: #define EMU_INTE_VMPU_330 0x30000000
! 102: #define EMU_INTE_MDMAENABLE 0x08000000
! 103: #define EMU_INTE_SDMAENABLE 0x04000000
! 104: #define EMU_INTE_MPICENABLE 0x02000000
! 105: #define EMU_INTE_SPICENABLE 0x01000000
! 106: #define EMU_INTE_VSBENABLE 0x00800000
! 107: #define EMU_INTE_ADLIBENABLE 0x00400000
! 108: #define EMU_INTE_MPUENABLE 0x00200000
! 109: #define EMU_INTE_FORCEINT 0x00100000
! 110: #define EMU_INTE_MRHANDENABLE 0x00080000
! 111: #define EMU_INTE_SAMPLERATER 0x00002000
! 112: #define EMU_INTE_FXDSPENABLE 0x00001000
! 113: #define EMU_INTE_PCIERRENABLE 0x00000800
! 114: #define EMU_INTE_VOLINCRENABLE 0x00000400
! 115: #define EMU_INTE_VOLDECRENABLE 0x00000200
! 116: #define EMU_INTE_MUTEENABLE 0x00000100
! 117: #define EMU_INTE_MICBUFENABLE 0x00000080
! 118: #define EMU_INTE_ADCBUFENABLE 0x00000040
! 119: #define EMU_INTE_EFXBUFENABLE 0x00000020
! 120: #define EMU_INTE_GPSPDIFENABLE 0x00000010
! 121: #define EMU_INTE_CDSPDIFENABLE 0x00000008
! 122: #define EMU_INTE_INTERTIMERENB 0x00000004
! 123: #define EMU_INTE_MIDITXENABLE 0x00000002
! 124: #define EMU_INTE_MIDIRXENABLE 0x00000001
! 125: #define EMU_INTE_A_MIDITXENABLE2 0x00020000
! 126: #define EMU_INTE_A_MIDIRXENABLE2 0x00010000
! 127:
! 128: #define EMU_WC 0x10
! 129:
! 130: #define EMU_WC_SAMPLECOUNTER_MASK 0x03FFFFC0
! 131: #define EMU_WC_SAMPLECOUNTER EMU_MKSUBREG(20, 6, EMU_WC)
! 132: #define EMU_WC_CURRENTCHANNEL 0x0000003F
! 133:
! 134: #define EMU_HCFG 0x14
! 135: #define EMU_HCFG_LEGACYFUNC_MASK 0xe0000000
! 136: #define EMU_HCFG_LEGACYFUNC_MPU 0x00000000
! 137: #define EMU_HCFG_LEGACYFUNC_SB 0x40000000
! 138: #define EMU_HCFG_LEGACYFUNC_AD 0x60000000
! 139: #define EMU_HCFG_LEGACYFUNC_MPIC 0x80000000
! 140: #define EMU_HCFG_LEGACYFUNC_MDMA 0xa0000000
! 141: #define EMU_HCFG_LEGACYFUNC_SPCI 0xc0000000
! 142: #define EMU_HCFG_LEGACYFUNC_SDMA 0xe0000000
! 143: #define EMU_HCFG_IOCAPTUREADDR 0x1f000000
! 144: #define EMU_HCFG_LEGACYWRITE 0x00800000
! 145: #define EMU_HCFG_LEGACYWORD 0x00400000
! 146:
! 147: #define EMU_HCFG_LEGACYINT 0x00200000
! 148: #define EMU_HCFG_CODECFMT_MASK 0x00070000
! 149: #define EMU_HCFG_CODECFMT_AC97 0x00000000
! 150: #define EMU_HCFG_CODECFMT_I2S 0x00010000
! 151: #define EMU_HCFG_GPINPUT0 0x00004000
! 152: #define EMU_HCFG_GPINPUT1 0x00002000
! 153: #define EMU_HCFG_GPOUTPUT0 0x00001000
! 154: #define EMU_HCFG_GPOUTPUT1 0x00000800
! 155: #define EMU_HCFG_GPOUTPUT2 0x00000400
! 156: #define EMU_HCFG_GPOUTPUT_MASK 0x00001c00
! 157: #define EMU_HCFG_JOYENABLE 0x00000200
! 158: #define EMU_HCFG_PHASETRACKENABLE 0x00000100
! 159: #define EMU_HCFG_AC3ENABLE_MASK 0x000000e0
! 160: #define EMU_HCFG_AC3ENABLE_ZVIDEO 0x00000080
! 161: #define EMU_HCFG_AC3ENABLE_CDSPDIF 0x00000040
! 162: #define EMU_HCFG_AC3ENABLE_GPSPDIF 0x00000020
! 163: #define EMU_HCFG_AUTOMUTE 0x00000010
! 164: #define EMU_HCFG_LOCKSOUNDCACHE 0x00000008
! 165: #define EMU_HCFG_LOCKTANKCACHE_MASK 0x00000004
! 166: #define EMU_HCFG_LOCKTANKCACHE EMU_MKSUBREG(1, 2, EMU_HCFG)
! 167: #define EMU_HCFG_MUTEBUTTONENABLE 0x00000002
! 168: #define EMU_HCFG_AUDIOENABLE 0x00000001
! 169:
! 170: #define EMU_MUDATA 0x18
! 171: #define EMU_MUCMD 0x19
! 172: #define EMU_MUCMD_RESET 0xff
! 173: #define EMU_MUCMD_ENTERUARTMODE 0x3f
! 174:
! 175: #define EMU_MUSTAT EMU_MUCMD
! 176: #define EMU_MUSTAT_IRDYN 0x80
! 177: #define EMU_MUSTAT_ORDYN 0x40
! 178:
! 179: #define EMU_A_IOCFG 0x18
! 180: #define EMU_A_GPINPUT_MASK 0xff00
! 181: #define EMU_A_GPOUTPUT_MASK 0x00ff
! 182: #define EMU_A_IOCFG_GPOUT0 0x0040
! 183: #define EMU_A_IOCFG_GPOUT1 0x0004
! 184:
! 185: #define EMU_TIMER 0x1a
! 186: #define EMU_TIMER_RATE_MASK 0x000003ff
! 187: #define EMU_TIMER_RATE EMU_MKSUBREG(10, 0, EMU_TIMER)
! 188:
! 189: #define EMU_AC97DATA 0x1c
! 190: #define EMU_AC97ADDR 0x1e
! 191: #define EMU_AC97ADDR_RDY 0x80
! 192: #define EMU_AC97ADDR_ADDR 0x7f
! 193:
! 194: #define EMU_A2_PTR 0x20
! 195: #define EMU_A2_DATA 0x24
! 196:
! 197: #define EMU_A2_SRCSEL 0x600000
! 198: #define EMU_A2_SRCSEL_ENABLE_SPDIF 0x00000004
! 199: #define EMU_A2_SRCSEL_ENABLE_SRCMULTI 0x00000010
! 200: #define EMU_A2_SRCMULTI 0x6e0000
! 201: #define EMU_A2_SRCMULTI_ENABLE_INPUT 0xff00ff00
! 202:
! 203: #define EMU_CHAN_CPF 0x00
! 204:
! 205: #define EMU_CHAN_CPF_PITCH_MASK 0xffff0000
! 206: #define EMU_CHAN_CPF_PITCH EMU_MKSUBREG(16, 16, EMU_CHAN_CPF)
! 207:
! 208: #define EMU_CHAN_CPF_STEREO_MASK 0x00008000
! 209: #define EMU_CHAN_CPF_STEREO EMU_MKSUBREG(1, 15, EMU_CHAN_CPF)
! 210: #define EMU_CHAN_CPF_STOP_MASK 0x00004000
! 211:
! 212: #define EMU_CHAN_CPF_FRACADDRESS_MASK 0x00003fff
! 213:
! 214:
! 215: #define EMU_CHAN_PTRX 0x01
! 216:
! 217: #define EMU_CHAN_PTRX_PITCHTARGET_MASK 0xffff0000
! 218: #define EMU_CHAN_PTRX_PITCHTARGET EMU_MKSUBREG(16, 16, EMU_CHAN_PTRX)
! 219:
! 220: #define EMU_CHAN_PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00
! 221: #define EMU_CHAN_PTRX_FXSENDAMOUNT_A EMU_MKSUBREG(8, 8, EMU_CHAN_PTRX)
! 222:
! 223: #define EMU_CHAN_PTRX_FXSENDAMOUNT_B_MASK 0x000000ff
! 224: #define EMU_CHAN_PTRX_FXSENDAMOUNT_B EMU_MKSUBREG(8, 0, EMU_CHAN_PTRX)
! 225:
! 226: #define EMU_CHAN_CVCF 0x02
! 227: #define EMU_CHAN_CVCF_CURRVOL_MASK 0xffff0000
! 228:
! 229: #define EMU_CHAN_CVCF_CURRVOL EMU_MKSUBREG(16, 16, EMU_CHAN_CVCF)
! 230: #define EMU_CHAN_CVCF_CURRFILTER_MASK 0x0000ffff
! 231:
! 232: #define EMU_CHAN_CVCF_CURRFILTER EMU_MKSUBREG(16, 0, EMU_CHAN_CVCF)
! 233:
! 234: #define EMU_CHAN_VTFT 0x03
! 235: #define EMU_CHAN_VTFT_VOLUMETARGET_MASK 0xffff0000
! 236:
! 237: #define EMU_CHAN_VTFT_VOLUMETARGET EMU_MKSUBREG(16, 16, EMU_CHAN_VTFT)
! 238: #define EMU_CHAN_VTFT_FILTERTARGET_MASK 0x0000ffff
! 239:
! 240: #define EMU_CHAN_VTFT_FILTERTARGET EMU_MKSUBREG(16, 0, EMU_CHAN_VTFT)
! 241:
! 242: #define EMU_CHAN_Z1 0x05
! 243: #define EMU_CHAN_Z2 0x04
! 244:
! 245: #define EMU_CHAN_PSST 0x06
! 246: #define EMU_CHAN_PSST_FXSENDAMOUNT_C_MASK 0xff000000
! 247:
! 248: #define EMU_CHAN_PSST_FXSENDAMOUNT_C EMU_MKSUBREG(8, 24, EMU_CHAN_PSST)
! 249: #define EMU_CHAN_PSST_LOOPSTARTADDR_MASK 0x00ffffff
! 250:
! 251: #define EMU_CHAN_PSST_LOOPSTARTADDR EMU_MKSUBREG(24, 0, EMU_CHAN_PSST)
! 252:
! 253: #define EMU_CHAN_DSL 0x07
! 254: #define EMU_CHAN_DSL_FXSENDAMOUNT_D_MASK 0xff000000
! 255:
! 256: #define EMU_CHAN_DSL_FXSENDAMOUNT_D EMU_MKSUBREG(8, 24, EMU_CHAN_DSL)
! 257: #define EMU_CHAN_DSL_LOOPENDADDR_MASK 0x00ffffff
! 258:
! 259: #define EMU_CHAN_DSL_LOOPENDADDR EMU_MKSUBREG(24, 0, EMU_CHAN_DSL)
! 260:
! 261: #define EMU_CHAN_CCCA 0x08
! 262:
! 263: #define EMU_CHAN_CCCA_RESONANCE 0xf0000000
! 264: #define EMU_CHAN_CCCA_INTERPROMMASK 0x0e000000
! 265: #define EMU_CHAN_CCCA_INTERPROM_0 0x00000000
! 266: #define EMU_CHAN_CCCA_INTERPROM_1 0x02000000
! 267: #define EMU_CHAN_CCCA_INTERPROM_2 0x04000000
! 268: #define EMU_CHAN_CCCA_INTERPROM_3 0x06000000
! 269: #define EMU_CHAN_CCCA_INTERPROM_4 0x08000000
! 270: #define EMU_CHAN_CCCA_INTERPROM_5 0x0a000000
! 271: #define EMU_CHAN_CCCA_INTERPROM_6 0x0c000000
! 272: #define EMU_CHAN_CCCA_INTERPROM_7 0x0e000000
! 273:
! 274: #define EMU_CHAN_CCCA_8BITSELECT 0x01000000
! 275:
! 276: #define EMU_CHAN_CCCA_CURRADDR_MASK 0x00ffffff
! 277: #define EMU_CHAN_CCCA_CURRADDR EMU_MKSUBREG(24, 0, EMU_CHAN_CCCA)
! 278:
! 279: #define EMU_CHAN_CCR 0x09
! 280: #define EMU_CHAN_CCR_CACHEINVALIDSIZE_MASK 0xfe000000
! 281:
! 282: #define EMU_CHAN_CCR_CACHEINVALIDSIZE EMU_MKSUBREG(7, 25, EMU_CHAN_CCR)
! 283: #define EMU_CHAN_CCR_CACHELOOPFLAG 0x01000000
! 284:
! 285: #define EMU_CHAN_CCR_INTERLEAVEDSAMPLES 0x00800000
! 286:
! 287: #define EMU_CHAN_CCR_WORDSIZEDSAMPLES 0x00400000
! 288:
! 289: #define EMU_CHAN_CCR_READADDRESS_MASK 0x003f0000
! 290:
! 291: #define EMU_CHAN_CCR_READADDRESS EMU_MKSUBREG(6, 16, EMU_CHAN_CCR)
! 292: #define EMU_CHAN_CCR_LOOPINVALSIZE 0x0000fe00
! 293: #define EMU_CHAN_CCR_LOOPFLAG 0x00000100
! 294:
! 295: #define EMU_CHAN_CCR_CACHELOOPADDRHI 0x000000ff
! 296:
! 297: #define EMU_CHAN_CLP 0x0a
! 298: #define EMU_CHAN_CLP_CACHELOOPADDR 0x0000ffff
! 299:
! 300: #define EMU_CHAN_FXRT 0x0b
! 301: #define EMU_CHAN_FXRT_CHANNELA 0x000f0000
! 302: #define EMU_CHAN_FXRT_CHANNELB 0x00f00000
! 303: #define EMU_CHAN_FXRT_CHANNELC 0x0f000000
! 304: #define EMU_CHAN_FXRT_CHANNELD 0xf0000000
! 305:
! 306: #define EMU_CHAN_MAPA 0x0c
! 307: #define EMU_CHAN_MAPB 0x0d
! 308:
! 309: #define EMU_CHAN_MAP_PTE_MASK 0xffffe000
! 310: #define EMU_CHAN_MAP_PTI_MASK 0x00001fff
! 311:
! 312:
! 313: #define EMU_CHAN_ENVVOL 0x10
! 314: #define EMU_CHAN_ENVVOL_MASK 0x0000ffff
! 315:
! 316:
! 317: #define EMU_CHAN_ATKHLDV 0x11
! 318: #define EMU_CHAN_ATKHLDV_PHASE0 0x00008000
! 319: #define EMU_CHAN_ATKHLDV_HOLDTIME_MASK 0x00007f00
! 320: #define EMU_CHAN_ATKHLDV_ATTACKTIME_MASK 0x0000007f
! 321:
! 322:
! 323: #define EMU_CHAN_DCYSUSV 0x12
! 324:
! 325: #define EMU_CHAN_DCYSUSV_PHASE1_MASK 0x00008000
! 326:
! 327: #define EMU_CHAN_DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00
! 328: #define EMU_CHAN_DCYSUSV_CHANNELENABLE_MASK 0x00000080
! 329: #define EMU_CHAN_DCYSUSV_DECAYTIME_MASK 0x0000007f
! 330:
! 331:
! 332: #define EMU_CHAN_LFOVAL1 0x13
! 333: #define EMU_CHAN_LFOVAL_MASK 0x0000ffff
! 334:
! 335:
! 336: #define EMU_CHAN_ENVVAL 0x14
! 337: #define EMU_CHAN_ENVVAL_MASK 0x0000ffff
! 338:
! 339:
! 340: #define EMU_CHAN_ATKHLDM 0x15
! 341: #define EMU_CHAN_ATKHLDM_PHASE0 0x00008000
! 342: #define EMU_CHAN_ATKHLDM_HOLDTIME 0x00007f00
! 343: #define EMU_CHAN_ATKHLDM_ATTACKTIME 0x0000007f
! 344:
! 345:
! 346: #define EMU_CHAN_DCYSUSM 0x16
! 347: #define EMU_CHAN_DCYSUSM_PHASE1_MASK 0x00008000
! 348: #define EMU_CHAN_DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00
! 349: #define EMU_CHAN_DCYSUSM_DECAYTIME_MASK 0x0000007f
! 350:
! 351:
! 352: #define EMU_CHAN_LFOVAL2 0x17
! 353: #define EMU_CHAN_LFOVAL2_MASK 0x0000ffff
! 354:
! 355:
! 356: #define EMU_CHAN_IP 0x18
! 357: #define EMU_CHAN_IP_MASK 0x0000ffff
! 358: #define EMU_CHAN_IP_UNITY 0x0000e000
! 359:
! 360: #define EMU_CHAN_IFATN 0x19
! 361: #define EMU_CHAN_IFATN_FILTERCUTOFF_MASK 0x0000ff00
! 362: #define EMU_CHAN_IFATN_FILTERCUTOFF EMU_MKSUBREG(8, 8, EMU_CHAN_IFATN)
! 363:
! 364: #define EMU_CHAN_IFATN_ATTENUATION_MASK 0x000000ff
! 365: #define EMU_CHAN_IFATN_ATTENUATION EMU_MKSUBREG(8, 0, EMU_CHAN_IFATN)
! 366:
! 367:
! 368: #define EMU_CHAN_PEFE 0x1a
! 369: #define EMU_CHAN_PEFE_PITCHAMOUNT_MASK 0x0000ff00
! 370: #define EMU_CHAN_PEFE_PITCHAMOUNT EMU_MKSUBREG(8, 8, EMU_CHAN_PEFE)
! 371: #define EMU_CHAN_PEFE_FILTERAMOUNT_MASK 0x000000ff
! 372: #define EMU_CHAN_PEFE_FILTERAMOUNT EMU_MKSUBREG(8, 0, EMU_CHAN_PEFE)
! 373:
! 374:
! 375: #define EMU_CHAN_FMMOD 0x1b
! 376: #define EMU_CHAN_FMMOD_MODVIBRATO 0x0000ff00
! 377: #define EMU_CHAN_FMMOD_MOFILTER 0x000000ff
! 378:
! 379:
! 380: #define EMU_CHAN_TREMFRQ 0x1c
! 381: #define EMU_CHAN_TREMFRQ_DEPTH 0x0000ff00
! 382:
! 383:
! 384: #define EMU_CHAN_FM2FRQ2 0x1d
! 385: #define EMU_CHAN_FM2FRQ2_DEPTH 0x0000ff00
! 386: #define EMU_CHAN_FM2FRQ2_FREQUENCY 0x000000ff
! 387:
! 388:
! 389: #define EMU_CHAN_TEMPENV 0x1e
! 390: #define EMU_CHAN_TEMPENV_MASK 0x0000ffff
! 391:
! 392: #define EMU_CHAN_CD0 0x20
! 393: #define EMU_CHAN_CD1 0x21
! 394: #define EMU_CHAN_CD2 0x22
! 395: #define EMU_CHAN_CD3 0x23
! 396: #define EMU_CHAN_CD4 0x24
! 397: #define EMU_CHAN_CD5 0x25
! 398: #define EMU_CHAN_CD6 0x26
! 399: #define EMU_CHAN_CD7 0x27
! 400: #define EMU_CHAN_CD8 0x28
! 401: #define EMU_CHAN_CD9 0x29
! 402: #define EMU_CHAN_CDA 0x2a
! 403: #define EMU_CHAN_CDB 0x2b
! 404: #define EMU_CHAN_CDC 0x2c
! 405: #define EMU_CHAN_CDD 0x2d
! 406: #define EMU_CHAN_CDE 0x2e
! 407: #define EMU_CHAN_CDF 0x2f
! 408:
! 409: /* -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- */
! 410:
! 411: #define EMU_PTB 0x40
! 412: #define EMU_PTB_MASK 0xfffff000
! 413:
! 414: #define EMU_TCB 0x41
! 415: #define EMU_TCB_MASK 0xfffff000
! 416:
! 417: #define EMU_ADCCR 0x42
! 418: #define EMU_ADCCR_RCHANENABLE 0x00000010
! 419: #define EMU_A_ADCCR_RCHANENABLE 0x00000020
! 420: #define EMU_ADCCR_LCHANENABLE 0x00000008
! 421: #define EMU_A_ADCCR_LCHANENABLE 0x00000010
! 422:
! 423: #define EMU_ADCCR_SAMPLERATE_MASK 0x00000007
! 424: #define EMU_A_ADCCR_SAMPLERATE_MASK 0x0000000f
! 425: #define EMU_ADCCR_SAMPLERATE_48 0x00000000
! 426: #define EMU_ADCCR_SAMPLERATE_44 0x00000001
! 427: #define EMU_ADCCR_SAMPLERATE_32 0x00000002
! 428: #define EMU_ADCCR_SAMPLERATE_24 0x00000003
! 429: #define EMU_ADCCR_SAMPLERATE_22 0x00000004
! 430: #define EMU_ADCCR_SAMPLERATE_16 0x00000005
! 431: #define EMU_A_ADCCR_SAMPLERATE_12 0x00000006
! 432: #define EMU_ADCCR_SAMPLERATE_11 0x00000006
! 433: #define EMU_A_ADCCR_SAMPLERATE_11 0x00000007
! 434: #define EMU_ADCCR_SAMPLERATE_8 0x00000007
! 435: #define EMU_A_ADCCR_SAMPLERATE_8 0x00000008
! 436:
! 437: #define EMU_FXWC 0x43
! 438: #define EMU_TCBS 0x44
! 439: #define EMU_TCBS_MASK 0x00000007
! 440: #define EMU_TCBS_BUFFSIZE_16K 0x00000000
! 441: #define EMU_TCBS_BUFFSIZE_32K 0x00000001
! 442: #define EMU_TCBS_BUFFSIZE_64K 0x00000002
! 443: #define EMU_TCBS_BUFFSIZE_128K 0x00000003
! 444: #define EMU_TCBS_BUFFSIZE_256K 0x00000004
! 445: #define EMU_TCBS_BUFFSIZE_512K 0x00000005
! 446: #define EMU_TCBS_BUFFSIZE_1024K 0x00000006
! 447: #define EMU_TCBS_BUFFSIZE_2048K 0x00000007
! 448:
! 449:
! 450: #define EMU_MICBA 0x45
! 451: #define EMU_ADCBA 0x46
! 452: #define EMU_FXBA 0x47
! 453:
! 454: #define EMU_RECBA_MASK 0xfffff000
! 455:
! 456: #define EMU_MICBS 0x49
! 457: #define EMU_ADCBS 0x4a
! 458: #define EMU_FXBS 0x4b
! 459: #define EMU_RECBS_BUFSIZE_NONE 0x00000000
! 460: #define EMU_RECBS_BUFSIZE_384 0x00000001
! 461: #define EMU_RECBS_BUFSIZE_448 0x00000002
! 462: #define EMU_RECBS_BUFSIZE_512 0x00000003
! 463: #define EMU_RECBS_BUFSIZE_640 0x00000004
! 464: #define EMU_RECBS_BUFSIZE_768 0x00000005
! 465: #define EMU_RECBS_BUFSIZE_896 0x00000006
! 466: #define EMU_RECBS_BUFSIZE_1024 0x00000007
! 467: #define EMU_RECBS_BUFSIZE_1280 0x00000008
! 468: #define EMU_RECBS_BUFSIZE_1536 0x00000009
! 469: #define EMU_RECBS_BUFSIZE_1792 0x0000000a
! 470: #define EMU_RECBS_BUFSIZE_2048 0x0000000b
! 471: #define EMU_RECBS_BUFSIZE_2560 0x0000000c
! 472: #define EMU_RECBS_BUFSIZE_3072 0x0000000d
! 473: #define EMU_RECBS_BUFSIZE_3584 0x0000000e
! 474: #define EMU_RECBS_BUFSIZE_4096 0x0000000f
! 475: #define EMU_RECBS_BUFSIZE_5120 0x00000010
! 476: #define EMU_RECBS_BUFSIZE_6144 0x00000011
! 477: #define EMU_RECBS_BUFSIZE_7168 0x00000012
! 478: #define EMU_RECBS_BUFSIZE_8192 0x00000013
! 479: #define EMU_RECBS_BUFSIZE_10240 0x00000014
! 480: #define EMU_RECBS_BUFSIZE_12288 0x00000015
! 481: #define EMU_RECBS_BUFSIZE_14366 0x00000016
! 482: #define EMU_RECBS_BUFSIZE_16384 0x00000017
! 483: #define EMU_RECBS_BUFSIZE_20480 0x00000018
! 484: #define EMU_RECBS_BUFSIZE_24576 0x00000019
! 485: #define EMU_RECBS_BUFSIZE_28672 0x0000001a
! 486: #define EMU_RECBS_BUFSIZE_32768 0x0000001b
! 487: #define EMU_RECBS_BUFSIZE_40960 0x0000001c
! 488: #define EMU_RECBS_BUFSIZE_49152 0x0000001d
! 489: #define EMU_RECBS_BUFSIZE_57344 0x0000001e
! 490: #define EMU_RECBS_BUFSIZE_65536 0x0000001f
! 491:
! 492:
! 493: #define EMU_CDCS 0x50
! 494: #define EMU_GPSCS 0x51
! 495:
! 496:
! 497: #define EMU_DBG 0x52
! 498: #define EMU_DBG_ZC 0x80000000
! 499: #define EMU_DBG_SATURATION_OCCURED 0x02000000
! 500: #define EMU_DBG_SATURATION_ADDR 0x01ff0000
! 501: #define EMU_DBG_SINGLE_STEP 0x00008000
! 502: #define EMU_DBG_STEP 0x00004000
! 503: #define EMU_DBG_CONDITION_CODE 0x00003e00
! 504: #define EMU_DBG_SINGLE_STEP_ADDR 0x000001ff
! 505:
! 506: #define EMU_A_DBG 0x53
! 507: #define EMU_A_DBG_SINGLE_STEP 0x00020000
! 508: #define EMU_A_DBG_ZC 0x40000000
! 509: #define EMU_A_DBG_STEP_ADDR 0x000003ff
! 510: #define EMU_A_DBG_SATURATION_OCCRD 0x20000000
! 511: #define EMU_A_DBG_SATURATION_ADDR 0x0ffc0000
! 512:
! 513: #define EMU_SPCS0 0x54
! 514: #define EMU_SPCS1 0x55
! 515: #define EMU_SPCS2 0x56
! 516:
! 517: #define EMU_SPCS_CLKACCYMASK 0x30000000
! 518: #define EMU_SPCS_CLKACCY_1000PPM 0x00000000
! 519: #define EMU_SPCS_CLKACCY_50PPM 0x10000000
! 520: #define EMU_SPCS_CLKACCY_VARIABLE 0x20000000
! 521:
! 522: #define EMU_SPCS_SAMPLERATEMASK 0x0f000000
! 523: #define EMU_SPCS_SAMPLERATE_44 0x00000000
! 524: #define EMU_SPCS_SAMPLERATE_48 0x02000000
! 525: #define EMU_SPCS_SAMPLERATE_32 0x03000000
! 526:
! 527: #define EMU_SPCS_CHANNELNUMMASK 0x00f00000
! 528:
! 529: #define EMU_SPCS_CHANNELNUM_UNSPEC 0x00000000
! 530: #define EMU_SPCS_CHANNELNUM_LEFT 0x00100000
! 531: #define EMU_SPCS_CHANNELNUM_RIGHT 0x00200000
! 532: #define EMU_SPCS_SOURCENUMMASK 0x000f0000
! 533: #define EMU_SPCS_SOURCENUM_UNSPEC 0x00000000
! 534: #define EMU_SPCS_GENERATIONSTATUS 0x00008000
! 535:
! 536: #define EMU_SPCS_CATEGORYCODEMASK 0x00007f00
! 537:
! 538: #define EMU_SPCS_MODEMASK 0x000000c0
! 539: #define EMU_SPCS_EMPHASISMASK 0x00000038
! 540: #define EMU_SPCS_EMPHASIS_NONE 0x00000000
! 541: #define EMU_SPCS_EMPHASIS_50_15 0x00000008
! 542: #define EMU_SPCS_COPYRIGHT 0x00000004
! 543:
! 544: #define EMU_SPCS_NOTAUDIODATA 0x00000002
! 545:
! 546: #define EMU_SPCS_PROFESSIONAL 0x00000001
! 547:
! 548:
! 549: #define EMU_CLIEL 0x58
! 550: #define EMU_CLIEH 0x59
! 551: #define EMU_CLIPL 0x5a
! 552: #define EMU_CLIPH 0x5b
! 553: #define EMU_SOLEL 0x5c
! 554: #define EMU_SOLEH 0x5d
! 555:
! 556: #define EMU_SPBYPASS 0x5e
! 557: #define EMU_SPBYPASS_ENABLE 0x00000001
! 558: #define EMU_SPBYPASS_24_BITS 0x00000f00
! 559:
! 560: #define EMU_AC97SLOT 0x5f
! 561: #define EMU_AC97SLOT_CENTER 0x00000010
! 562: #define EMU_AC97SLOT_LFE 0x00000020
! 563:
! 564: #define EMU_CDSRCS 0x60
! 565: #define EMU_GPSRCS 0x61
! 566: #define EMU_ZVSRCS 0x62
! 567: #define EMU_SRCS_SPDIFLOCKED 0x02000000
! 568: #define EMU_SRCS_RATELOCKED 0x01000000
! 569: #define EMU_SRCS_ESTSAMPLERATE 0x0007ffff
! 570:
! 571:
! 572: #define EMU_MICIDX 0x63
! 573: #define EMU_A_MICIDX 0x64
! 574: #define EMU_ADCIDX 0x64
! 575: #define EMU_A_ADCIDX 0x63
! 576: #define EMU_FXIDX 0x65
! 577: #define EMU_RECIDX_MASK 0x0000ffff
! 578: #define EMU_RECIDX(idxreg) (0x10000000|(idxreg))
! 579: /*
! 580: #define EMU_MICIDX_IDX 0x10000063
! 581: #define EMU_ADCIDX_IDX 0x10000064
! 582: #define EMU_FXIDX_IDX 0x10000065
! 583: */
! 584:
! 585: #define EMU_A_MUDATA1 0x70
! 586: #define EMU_A_MUCMD1 0x71
! 587: #define EMU_A_MUSTAT1 EMU_A_MUCMD1
! 588: #define EMU_A_MUDATA2 0x72
! 589: #define EMU_A_MUCMD2 0x73
! 590: #define EMU_A_MUSTAT2 EMU_A_MUCMD2
! 591: #define EMU_A_FXWC1 0x74
! 592: #define EMU_A_FXWC2 0x75
! 593: #define EMU_A_SPDIF_SAMPLERATE 0x76
! 594: #define EMU_A_SPDIF_48000 0x00000080
! 595: #define EMU_A_SPDIF_44100 0x00000000
! 596: #define EMU_A_SPDIF_96000 0x00000040
! 597: #define EMU_A2_SPDIF_SAMPLERATE EMU_MKSUBREG(3, 9, EMU_A_SPDIF_SAMPLERATE)
! 598: #define EMU_A2_SPDIF_MASK 0x00000e00
! 599: #define EMU_A2_SPDIF_UNKNOWN 0x2
! 600:
! 601: #define EMU_A_CHAN_FXRT2 0x7c
! 602: #define EMU_A_CHAN_FXRT_CHANNELE 0x0000003f
! 603: #define EMU_A_CHAN_FXRT_CHANNELF 0x00003f00
! 604: #define EMU_A_CHAN_FXRT_CHANNELG 0x003f0000
! 605: #define EMU_A_CHAN_FXRT_CHANNELH 0x3f000000
! 606: #define EMU_A_CHAN_SENDAMOUNTS 0x7d
! 607: #define EMU_A_CHAN_FXSENDAMOUNTS_E_MASK 0xff000000
! 608: #define EMU_A_CHAN_FXSENDAMOUNTS_F_MASK 0x00ff0000
! 609: #define EMU_A_CHAN_FXSENDAMOUNTS_G_MASK 0x0000ff00
! 610: #define EMU_A_CHAN_FXSENDAMOUNTS_H_MASK 0x000000ff
! 611: #define EMU_A_CHAN_FXRT1 0x7e
! 612: #define EMU_A_CHAN_FXRT_CHANNELA 0x0000003f
! 613: #define EMU_A_CHAN_FXRT_CHANNELB 0x00003f00
! 614: #define EMU_A_CHAN_FXRT_CHANNELC 0x003f0000
! 615: #define EMU_A_CHAN_FXRT_CHANNELD 0x3f000000
! 616:
! 617: #define EMU_FXGPREGBASE 0x100
! 618: #define EMU_A_FXGPREGBASE 0x400
! 619: #define EMU_TANKMEMDATAREGBASE 0x200
! 620: #define EMU_TANKMEMDATAREG_MASK 0x000fffff
! 621:
! 622: #define EMU_TANKMEMADDRREGBASE 0x300
! 623: #define EMU_TANKMEMADDRREG_ADDR_MASK 0x000fffff
! 624: #define EMU_TANKMEMADDRREG_CLEAR 0x00800000
! 625: #define EMU_TANKMEMADDRREG_ALIGN 0x00400000
! 626: #define EMU_TANKMEMADDRREG_WRITE 0x00200000
! 627: #define EMU_TANKMEMADDRREG_READ 0x00100000
! 628:
! 629:
! 630: #define EMU_MICROCODEBASE 0x400
! 631: #define EMU_A_MICROCODEBASE 0x600
! 632:
! 633: #define EMU_DSP_LOWORD_OPX_MASK 0x000ffc00
! 634: #define EMU_DSP_LOWORD_OPY_MASK 0x000003ff
! 635: #define EMU_DSP_HIWORD_OPCODE_MASK 0x00f00000
! 636: #define EMU_DSP_HIWORD_RESULT_MASK 0x000ffc00
! 637: #define EMU_DSP_HIWORD_OPA_MASK 0x000003ff
! 638: #define EMU_A_DSP_LOWORD_OPX_MASK 0x007ff000
! 639: #define EMU_A_DSP_LOWORD_OPY_MASK 0x000007ff
! 640: #define EMU_A_DSP_HIWORD_OPCODE_MASK 0x0f000000
! 641: #define EMU_A_DSP_HIWORD_RESULT_MASK 0x007ff000
! 642: #define EMU_A_DSP_HIWORD_OPA_MASK 0x000007ff
! 643:
! 644:
! 645: #define EMU_DSP_OP_MACS 0x0
! 646: #define EMU_DSP_OP_MACS1 0x1
! 647: #define EMU_DSP_OP_MACW 0x2
! 648: #define EMU_DSP_OP_MACW1 0x3
! 649: #define EMU_DSP_OP_MACINTS 0x4
! 650: #define EMU_DSP_OP_MACINTW 0x5
! 651: #define EMU_DSP_OP_ACC3 0x6
! 652: #define EMU_DSP_OP_MACMV 0x7
! 653: #define EMU_DSP_OP_ANDXOR 0x8
! 654: #define EMU_DSP_OP_TSTNEG 0x9
! 655: #define EMU_DSP_OP_LIMIT 0xA
! 656: #define EMU_DSP_OP_LIMIT1 0xB
! 657: #define EMU_DSP_OP_LOG 0xC
! 658: #define EMU_DSP_OP_EXP 0xD
! 659: #define EMU_DSP_OP_INTERP 0xE
! 660: #define EMU_DSP_OP_SKIP 0xF
! 661:
! 662:
! 663: #define EMU_DSP_FX(num) (num)
! 664:
! 665:
! 666: #define EMU_DSP_IOL(base, num) (base + (num << 1))
! 667: #define EMU_DSP_IOR(base, num) (EMU_DSP_IOL(base, num) + 1)
! 668:
! 669: #define EMU_DSP_INL_BASE 0x010
! 670: #define EMU_DSP_INL(num) (EMU_DSP_IOL(EMU_DSP_INL_BASE, num))
! 671: #define EMU_DSP_INR(num) (EMU_DSP_IOR(EMU_DSP_INL_BASE, num))
! 672: #define EMU_A_DSP_INL_BASE 0x040
! 673: #define EMU_A_DSP_INL(num) (EMU_DSP_IOL(EMU_A_DSP_INL_BASE, num))
! 674: #define EMU_A_DSP_INR(num) (EMU_DSP_IOR(EMU_A_DSP_INL_BASE, num))
! 675: #define EMU_DSP_IN_AC97 0
! 676: #define EMU_DSP_IN_CDSPDIF 1
! 677: #define EMU_DSP_IN_ZOOM 2
! 678: #define EMU_DSP_IN_TOSOPT 3
! 679: #define EMU_DSP_IN_LVDLM1 4
! 680: #define EMU_DSP_IN_LVDCOS 5
! 681: #define EMU_DSP_IN_LVDLM2 6
! 682: #define EMU_DSP_IN_UNKNOWN 7
! 683:
! 684: #define EMU_DSP_OUTL_BASE 0x020
! 685: #define EMU_DSP_OUTL(num) (EMU_DSP_IOL(EMU_DSP_OUTL_BASE, num))
! 686: #define EMU_DSP_OUTR(num) (EMU_DSP_IOR(EMU_DSP_OUTL_BASE, num))
! 687: #define EMU_DSP_OUT_A_FRONT 0
! 688: #define EMU_DSP_OUT_D_FRONT 1
! 689: #define EMU_DSP_OUT_D_CENTER 2
! 690: #define EMU_DSP_OUT_DRIVE_HP 3
! 691: #define EMU_DSP_OUT_AD_REAR 4
! 692: #define EMU_DSP_OUT_ADC 5
! 693: #define EMU_DSP_OUTL_MIC 6
! 694:
! 695: #define EMU_A_DSP_OUTL_BASE 0x060
! 696: #define EMU_A_DSP_OUTL(num) (EMU_DSP_IOL(EMU_A_DSP_OUTL_BASE, num))
! 697: #define EMU_A_DSP_OUTR(num) (EMU_DSP_IOR(EMU_A_DSP_OUTL_BASE, num))
! 698: #define EMU_A_DSP_OUT_D_FRONT 0
! 699: #define EMU_A_DSP_OUT_D_CENTER 1
! 700: #define EMU_A_DSP_OUT_DRIVE_HP 2
! 701: #define EMU_A_DSP_OUT_DREAR 3
! 702: #define EMU_A_DSP_OUT_A_FRONT 4
! 703: #define EMU_A_DSP_OUT_A_CENTER 5
! 704: #define EMU_A_DSP_OUT_A_REAR 7
! 705: #define EMU_A_DSP_OUT_ADC 11
! 706:
! 707:
! 708: #define EMU_DSP_CST_BASE 0x40
! 709: #define EMU_A_DSP_CST_BASE 0xc0
! 710: #define EMU_DSP_CST(num) (EMU_DSP_CST_BASE + num)
! 711: #define EMU_A_DSP_CST(num) (EMU_A_DSP_CST_BASE + num)
! 712: /*
! 713: 00 = 0x00000000
! 714: 01 = 0x00000001
! 715: 02 = 0x00000002
! 716: 03 = 0x00000003
! 717: 04 = 0x00000004
! 718: 05 = 0x00000008
! 719: 06 = 0x00000010
! 720: 07 = 0x00000020
! 721: 08 = 0x00000100
! 722: 09 = 0x00010000
! 723: 0A = 0x00080000
! 724: 0B = 0x10000000
! 725: 0C = 0x20000000
! 726: 0D = 0x40000000
! 727: 0E = 0x80000000
! 728: 0F = 0x7FFFFFFF
! 729: 10 = 0xFFFFFFFF
! 730: 11 = 0xFFFFFFFE
! 731: 12 = 0xC0000000
! 732: 13 = 0x4F1BBCDC
! 733: 14 = 0x5A7EF9DB
! 734: 15 = 0x00100000
! 735: */
! 736:
! 737: #define EMU_DSP_HWR_ACC 0x056
! 738: #define EMU_DSP_HWR_CCR 0x057
! 739: #define EMU_DSP_HWR_CCR_S 0x04
! 740: #define EMU_DSP_HWR_CCR_Z 0x03
! 741: #define EMU_DSP_HWR_CCR_M 0x02
! 742: #define EMU_DSP_HWR_CCR_N 0x01
! 743: #define EMU_DSP_HWR_CCR_B 0x00
! 744: #define EMU_DSP_HWR_NOISE0 0x058
! 745: #define EMU_DSP_HWR_NOISE1 0x059
! 746: #define EMU_DSP_HWR_INTR 0x05A
! 747: #define EMU_DSP_HWR_DBAC 0x05B
! 748:
! 749: #define EMU_DSP_GPR(num) (EMU_FXGPREGBASE + num)
! 750: #define EMU_A_DSP_GPR(num) (EMU_A_FXGPREGBASE + num)
! 751:
! 752: #endif /* _DEV_PCI_EMUXKIREG_H_ */
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