Annotation of sys/dev/pci/cs4280reg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: cs4280reg.h,v 1.1 2000/06/30 03:28:08 art Exp $ */
! 2: /* $NetBSD: cs4280reg.h,v 1.3 2000/05/15 01:35:29 thorpej Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved.
! 6: *
! 7: * Redistribution and use in source and binary forms, with or without
! 8: * modification, are permitted provided that the following conditions
! 9: * are met:
! 10: * 1. Redistributions of source code must retain the above copyright
! 11: * notice, this list of conditions and the following disclaimer.
! 12: * 2. Redistributions in binary form must reproduce the above copyright
! 13: * notice, this list of conditions and the following disclaimer in the
! 14: * documentation and/or other materials provided with the distribution.
! 15: * 3. All advertising materials mentioning features or use of this software
! 16: * must display the following acknowledgement:
! 17: * This product includes software developed by Tatoku Ogaito
! 18: * for the NetBSD Project.
! 19: * 4. The name of the author may not be used to endorse or promote products
! 20: * derived from this software without specific prior written permission
! 21: *
! 22: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 23: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
! 24: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
! 25: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
! 26: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
! 27: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
! 28: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
! 29: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
! 30: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
! 31: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
! 32: */
! 33:
! 34:
! 35: #define CS4280_BA0_SIZE 0x2000
! 36: #define CS4280_BA1_SIZE 0x40000
! 37:
! 38: /* BA0 */
! 39:
! 40: /* Interrupt Reporting Registers */
! 41: #define CS4280_HISR 0x000 /* Host Interrupt Status Register */
! 42: #define HISR_INTENA 0x80000000
! 43: #define HISR_MIDI 0x00100000
! 44: #define HISR_CINT 0x00000002
! 45: #define HISR_PINT 0x00000001
! 46: #define CS4280_HICR 0x008 /* Host Interrupt Control Register */
! 47: #define HICR_CHGM 0x00000002
! 48: #define HICR_IEV 0x00000001
! 49:
! 50: /* Clock Control Registers */
! 51: #define CS4280_CLKCR1 0x400 /* Clock Control Register 1 */
! 52: #define CLKCR1_PLLSS_SPBC 0x00000000
! 53: #define CLKCR1_PLLSS_RSV 0x00000004
! 54: #define CLKCR1_PLLSS_PCI 0x00000008
! 55: #define CLKCR1_PLLSS_RSV2 0x0000000c
! 56: #define CLKCR1_PLLP 0x00000010
! 57: #define CLKCR1_SWCE 0x00000020
! 58:
! 59: #define CS4280_CLKCR2 0x404 /* Clock Control Register 2 */
! 60: #define CLKCR2_PDIVS_RSV 0x00000002
! 61: #define CLKCR2_PDIVS_8 0x00000008
! 62: #define CLKCR2_PDIVS_16 0x00000000
! 63:
! 64: #define CS4280_PLLM 0x408 /* PLL Multiplier Register */
! 65: #define PLLM_STATE 0x0000003a
! 66:
! 67: #define CS4280_PLLCC 0x40c /* PLL Capacitor Coefficient Register */
! 68: #define PLLCC_CDR_STATE 0x00000006
! 69: #define PLLCC_LPF_STATE 0x00000078
! 70:
! 71: /* General Configuration Registers */
! 72: #define CS4280_SERMC1 0x420 /* Serial Port Master Control Register 1 */
! 73: #define SERMC1_MSPE 0x00000001
! 74: #define SERMC1_PTC_MASK 0x0000000e
! 75: #define SERMC1_PTC_CS423X 0x00000000
! 76: #define SERMC1_PTC_AC97 0x00000002
! 77: #define SERMC1_PLB_EN 0x00000010
! 78: #define SERMC1_XLB_EN 0x00000020
! 79: #define CS4280_SERC1 0x428 /* Serial Port Configuration Register 1 */
! 80: #define SERC1_SO1EN 0x00000001
! 81: #define SERC1_SO1F_MASK 0x0000000e
! 82: #define SERC1_SO1F_CS423X 0x00000000
! 83: #define SERC1_SO1F_AC97 0x00000002
! 84: #define SERC1_SO1F_DAC 0x00000004
! 85: #define SERC1_SO1F_SPDIF 0x00000006
! 86: #define CS4280_SERC2 0x42c /* Serial Port Configuration Register 2 */
! 87: #define SERC2_SI1EN 0x00000001
! 88: #define SERC2_SI1F_MASK 0x0000000e
! 89: #define SERC2_SI1F_CS423X 0x00000000
! 90: #define SERC2_SI1F_AC97 0x00000002
! 91: #define SERC2_SI1F_ADC 0x00000004
! 92: #define SERC2_SI1F_SPDIF 0x00000006
! 93:
! 94: #define CS4280_SERBSP 0x43c
! 95: #define SERBSP_FSP_MASK 0x0000000f
! 96:
! 97: #define CS4280_SERBST 0x440
! 98: #define SERBST_RRDY 0x00000001
! 99: #define SERBST_WBSY 0x00000002
! 100: #define CS4280_SERBCM 0x444
! 101: #define SERBCM_RDC 0x000000001
! 102: #define SERBCM_WRC 0x000000002
! 103: #define CS4280_SERBAD 0x448
! 104: #define CS4280_SERBWP 0x450
! 105: /* AC97 Registers */
! 106: #define CS4280_ACCTL 0x460 /* AC97 Control Register */
! 107: #define ACCTL_RSTN 0x00000001
! 108: #define ACCTL_ESYN 0x00000002
! 109: #define ACCTL_VFRM 0x00000004
! 110: #define ACCTL_DCV 0x00000008
! 111: #define ACCTL_CRW 0x00000010
! 112: #define ACCTL_ASYN 0x00000020
! 113: #define ACCTL_TC 0x00000040
! 114: #define CS4280_ACSTS 0x464 /* AC97 Status Register */
! 115: #define ACSTS_CRDY 0x00000001
! 116: #define ACSTS_VSTS 0x00000002
! 117: #define ACSTS_WKUP 0x00000004
! 118: #define CS4280_ACOSV 0x468 /* AC97 Output Slot Valid Register */
! 119: #define ACOSV_SLV3 0x00000001
! 120: #define ACOSV_SLV4 0x00000002
! 121: #define ACOSV_SLV5 0x00000004
! 122: #define ACOSV_SLV6 0x00000008
! 123: #define ACOSV_SLV7 0x00000010
! 124: #define ACOSV_SLV8 0x00000020
! 125: #define ACOSV_SLV9 0x00000040
! 126: #define ACOSV_SLV10 0x00000080
! 127: #define ACOSV_SLV11 0x00000100
! 128: #define ACOSV_SLV12 0x00000200
! 129:
! 130: #define CS4280_ACCAD 0x46c /* AC97 Command Address Register */
! 131: #define CS4280_ACCDA 0x470 /* AC97 Command Data Register */
! 132: #define CS4280_ACISV 0x474 /* AC97 Input Slot Valid Register */
! 133: #define ACISV_ISV3 0x00000001
! 134: #define ACISV_ISV4 0x00000002
! 135: #define ACISV_ISV5 0x00000004
! 136: #define ACISV_ISV6 0x00000008
! 137: #define ACISV_ISV7 0x00000010
! 138: #define ACISV_ISV8 0x00000020
! 139: #define ACISV_ISV9 0x00000040
! 140: #define ACISV_ISV10 0x00000080
! 141: #define ACISV_ISV11 0x00000100
! 142: #define ACISV_ISV12 0x00000200
! 143: #define CS4280_ACSAD 0x478 /* AC97 Status Address Register */
! 144: #define CS4280_ACSDA 0x47c /* AC97 Status Data Register */
! 145:
! 146: /* Host Access Methods */
! 147: #define CS4280_GPIOR 0x4b8 /* General Purpose I/O Register */
! 148: #define CS4280_EGPIODR 0x4bc /* Extended GPIO Direction Register */
! 149: #define CS4280_EGPIOPTR 0x4c0 /* Extended GPIO Polarity/Type Register */
! 150: #define CS4280_EGPIOTR 0x4c4 /* Extended GPIO Sticky Register */
! 151: #define CS4280_EGPIOWR 0x4c8 /* Extended GPIO Wakeup Register */
! 152: #define CS4280_EGPIOSR 0x4cc /* Extended GPIO Status Register */
! 153:
! 154: /* Control Register */
! 155: #define CS4280_CFGI 0x4b0 /* Configuration Interface Register */
! 156:
! 157: #define CS4280_SERACC 0x4d8
! 158: #define SERACC_CTYPE_MASK 0x00000001
! 159: #define SERACC_CTYPE_1_03 0x00000000
! 160: #define SERACC_CTYPE_2_0 0x00000001
! 161: #define SERACC_TWO_CODECS 0x00000002
! 162: #define SERACC_MDM 0x00000004
! 163: #define SERACC_HSP 0x00000008
! 164:
! 165: /* Midi Port */
! 166: #define CS4280_MIDCR 0x490 /* MIDI Control Register */
! 167: #define MIDCR_TXE 0x00000001 /* MIDI Transmit Enable */
! 168: #define MIDCR_RXE 0x00000002 /* MIDI Receive Enable */
! 169: #define MIDCR_RIE 0x00000004 /* MIDI Receive Interrupt Enable */
! 170: #define MIDCR_TIE 0x00000008 /* MIDI Transmit Interrupt Enable */
! 171: #define MIDCR_MLB 0x00000010 /* MIDI Loop Back Enable */
! 172: #define MIDCR_MRST 0x00000020 /* MIDI Reset */
! 173: #define MIDCR_MASK 0x0000003f
! 174: #define CS4280_MIDSR 0x494 /* Host MIDI Status Register */
! 175: #define MIDSR_TBF 0x00000001 /* Transmit Buffer Full */
! 176: #define MIDSR_RBE 0x00000002 /* Receive Buffer Empty */
! 177: #define CS4280_MIDWP 0x498 /* MIDI Write Port */
! 178: #define MIDWP_MASK 0x000000ff
! 179: #define CS4280_MIDRP 0x49c /* MIDI Read Port */
! 180: #define MIDRP_MASK 0x000000ff
! 181:
! 182: /* Joy Stick Port */
! 183: #define CS4280_JSPT 0x480 /* Joystick Poll/Trigger Register */
! 184: #define CS4280_JSCTL 0x484 /* Joystick Control Register */
! 185: #define CS4280_JSC1 0x488 /* Joystick Coordinate Register 1 */
! 186: #define CS4280_JSC2 0x48c /* Joystick Coordinate Register 2 */
! 187:
! 188:
! 189: /* BA1 */
! 190:
! 191: /* Playback Parameters */
! 192: #define CS4280_PDTC 0x00c0 /* Playback DMA Transaction Count */
! 193: #define PDTC_MASK 0x000003ff
! 194: #define CS4280_MK_PDTC(x) ((x)/2 - 1)
! 195: #define CS4280_PFIE 0x00c4 /* Playback Format and Interrupt Enable */
! 196: #define PFIE_UNSIGNED 0x00008000 /* Playback Format is unsigned */
! 197: #define PFIE_SWAPPED 0x00004000 /* Playback Format is need swapped */
! 198: #define PFIE_MONO 0x00002000 /* Playback Format is monoral */
! 199: #define PFIE_8BIT 0x00001000 /* Playback Format is 8bit */
! 200: #define PFIE_PI_ENABLE 0x00000000 /* Playback Interrupt Enabled */
! 201: #define PFIE_PI_DISABLE 0x00000010 /* Playback Interrupt Disabled */
! 202: #define PFIE_PI_MASK 0x0000003f
! 203: #define PFIE_MASK 0x0000f03f
! 204: #define CS4280_PBA 0x00c8 /* Playback Buffer Address */
! 205: #define CS4280_PVOL 0x00f8 /* Playback Volume */
! 206: #define CS4280_PSRC 0x0288 /* Playback Sample Rate Correction */
! 207: #define PSRC_MASK 0xffff0000
! 208: #define CS4280_MK_PSRC(psrc, py) ((((psrc) << 16) & 0xffff0000) | ((py) & 0xffff))
! 209: #define CS4280_PCTL 0x02a4 /* Playback Control */
! 210: #define PCTL_MASK 0xffff0000
! 211: #define CS4280_PPI 0x02b4 /* Playback Phase Increment */
! 212:
! 213: /* Capture Parameters */
! 214: #define CS4280_CCTL 0x0064 /* Capture Control */
! 215: #define CCTL_MASK 0x0000ffff
! 216: #define CS4280_CDTC 0x0100 /* Capture DMA Transaction Count */
! 217: #define CS4280_CIE 0x0104 /* Capture Interrupt Enable */
! 218: #define CIE_CI_ENABLE 0x00000001 /* Capture Interrupt enabled */
! 219: #define CIE_CI_DISABLE 0x00000011 /* Capture Interrupt disabled */
! 220: #define CIE_CI_MASK 0x0000003f
! 221: #define CS4280_CBA 0x010c /* Capture Buffer Address */
! 222: #define CS4280_CSRC 0x02c8 /* Capture Sample Rate Correction */
! 223: #define CSRC_MASK 0xffff0000
! 224: #define CS4280_MK_CSRC(csrc, cy) ((((csrc) << 16) & 0xffff0000) | ((cy) & 0xffff))
! 225: #define CS4280_CCI 0x02d8 /* Capture Coefficient Increment */
! 226: #define CCI_MASK 0xffff0000
! 227: #define CS4280_CD 0x02e0 /* Capture Delay */
! 228: #define CD_MASK 0xfffc000
! 229: #define CS4280_CPI 0x02f4 /* Capture Phase Incremnt */
! 230: #define CS4280_CGL 0x0134 /* Capture Group Length */
! 231: #define CGL_MASK 0x0000ffff
! 232: #define CS4280_CNT 0x0340 /* Capture Number of Triplets */
! 233: #define CS4280_CGC 0x0138 /* Capture Group Count */
! 234: #define CGC_MASK 0x0000ffff
! 235: #define CS4280_CVOL 0x02f8 /* Capture Volume */
! 236:
! 237: /* Processor Registers */
! 238: #define CS4280_SPCR 0x30000 /* Processor Control Register */
! 239: #define SPCR_RUN 0x00000001
! 240: #define SPCR_STPFR 0x00000002
! 241: #define SPCR_RUNFR 0x00000004
! 242: #define SPCR_DRQEN 0x00000020
! 243: #define SPCR_RSTSP 0x00000040
! 244: #define CS4280_DREG 0x30004
! 245: #define CS4280_DSRWP 0x30008
! 246: #define CS4280_TWPR 0x3000c /* Trap Write Port Register */
! 247: #define CS4280_SPWR 0x30010
! 248: #define CS4280_SPCS 0x30028 /* Processor Clock Status Register */
! 249: #define SPCS_SPRUN 0x00000100
! 250: #define CS4280_FRMT 0x30030 /* Frame Timer Register */
! 251: #define FRMT_FTV 0x00000adf
! 252:
! 253:
! 254: #define CF_MONO 0x01
! 255: #define CF_8BIT 0x02
! 256:
! 257: #define CF_16BIT_STEREO 0x00
! 258: #define CF_16BIT_MONO 0x01
! 259: #define CF_8BIT_STEREO 0x02
! 260: #define CF_8BIT_MONO 0x03
! 261:
! 262: #define MIDI_BUSY_WAIT 100
! 263: #define MIDI_BUSY_DELAY 100 /* Delay when UART is busy */
! 264:
! 265: /* 3*1024 parameter, 3.5*1024 sample, 2*3.5*1024 code */
! 266: #define BA1_DWORD_SIZE (13 * 1024 + 512)
! 267: #define BA1_MEMORY_COUNT 3
! 268:
! 269: struct BA1struct {
! 270: struct {
! 271: u_int32_t offset;
! 272: u_int32_t size;
! 273: } memory[BA1_MEMORY_COUNT];
! 274: u_int32_t map[BA1_DWORD_SIZE];
! 275: };
! 276:
! 277: #define CS4280_ICHUNK 2048 /* Bytes between interrupts */
! 278: #define CS4280_DCHUNK 4096 /* Bytes of DMA memory */
! 279: #define CS4280_DALIGN 4096 /* Alignment of DMA memory */
! 280:
! 281: /* AC97 Registers */
! 282: #define CS4280_SAVE_REG_MAX 0x10
! 283:
! 284: /* for AC97_REG_POWER */
! 285: #define CS4280_POWER_DOWN_ALL 0x7f0f
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