Annotation of sys/dev/pci/bt8370reg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: bt8370reg.h,v 1.3 2005/12/19 15:53:15 claudio Exp $ */
2:
3: /*
4: * Copyright (c) 2004,2005 Internet Business Solutions AG, Zurich, Switzerland
5: * Written by: Andre Oppermann <oppermann@accoom.net>
6: *
7: * Permission to use, copy, modify, and distribute this software for any
8: * purpose with or without fee is hereby granted, provided that the above
9: * copyright notice and this permission notice appear in all copies.
10: *
11: * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12: * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13: * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14: * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15: * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16: * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17: * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18: */
19:
20: /* Bt8370 Register definitions */
21: /* Globals */
22: #define Bt8370_DID 0x000 /* Device Identification */
23: #define Bt8370_CR0 0x001 /* Primary control register */
24: #define CR0_RESET 0x80 /* Reset Framer */
25: #define CR0_E1_FAS 0x00 /* E1 FAS only */
26: #define CR0_E1_FAS_CRC 0x08 /* E1 FAS+CRC4 */
27: #define CR0_T1_SF 0x09 /* T1 SF */
28: #define CR0_T1_ESF 0x1B /* T1 ESF+ForceCRC */
29: #define Bt8370_JAT_CR 0x002 /* Jitter attenuator conf */
30: #define JAT_CR_JEN 0x80 /* Jitter anntenuator enable */
31: #define JAT_CR_JFREE 0x40 /* Free running JCLK and CLADO */
32: #define JAT_CR_JDIR_TX 0x00 /* JAT in TX direction */
33: #define JAT_CR_JDIR_RX 0x20 /* JAT in RC direction */
34: #define JAT_CR_JAUTO 0x10 /* JCLK Acceleration */
35: #define JAT_CR_CENTER 0x80 /* Force JAT to center */
36: #define JAT_CR_JSIZE8 0x00 /* Elastic store size 8 bits */
37: #define JAT_CR_JSIZE16 0x01 /* Elastic store size 16 bits */
38: #define JAT_CR_JSIZE32 0x02 /* Elastic store size 32 bits */
39: #define JAT_CR_JSIZE64 0x03 /* Elastic store size 64 bits */
40: #define JAT_CR_JSIZE128 0x04 /* Elastic store size 128 bits */
41: #define Bt8370_IRR 0x003 /* Interrupt request register */
42: /* Interrupt Status */
43: #define Bt8370_ISR7 0x004 /* Alarm 1 Interrupt Status */
44: #define Bt8370_ISR6 0x005 /* Alarm 2 Interrupt Status */
45: #define Bt8370_ISR5 0x006 /* Error Interrupt Status */
46: #define Bt8370_ISR4 0x007 /* Counter Overflow Interrupt Status */
47: #define Bt8370_ISR3 0x008 /* Timer Interrupt Status */
48: #define Bt8370_ISR2 0x009 /* Data Link 1 Interrupt Status */
49: #define Bt8370_ISR1 0x00A /* Data Link 2 Interrupt Status */
50: #define Bt8370_ISR0 0x00B /* Pattern Interrupt Status */
51: /* Interrupt Enable */
52: #define Bt8370_IER7 0x00C /* Alarm 1 Interrupt Enable register */
53: #define Bt8370_IER6 0x00D /* Alarm 2 Interrupt Enable register */
54: #define Bt8370_IER5 0x00E /* Error Interrupt Enable register */
55: #define Bt8370_IER4 0x00F /* Count Overflow Interrupt Enable register */
56: #define Bt8370_IER3 0x010 /* Timer Interrupt Enable register */
57: #define Bt8370_IER2 0x011 /* Data Link 1 Interrupt Enable register */
58: #define Bt8370_IER1 0x012 /* Date Link 2 Interrupt Enable register */
59: #define Bt8370_IER0 0x013 /* Pattern Interrupt Enable register */
60: /* Primary */
61: #define Bt8370_LOOP 0x014 /* Loopback Configuration register */
62: #define LOOP_PLOOP 0x08 /* Remote Payload Loopback */
63: #define LOOP_LLOOP 0x04 /* Remote Line Loopback */
64: #define LOOP_FLOOP 0x02 /* Local Framer Loopback */
65: #define LOOP_ALOOP 0x01 /* Local Analog Loopback */
66: #define Bt8370_DL3_TS 0x015 /* External Data Link Channel */
67: #define Bt8370_DL3_BIT 0x016 /* External Data Link Bit */
68: #define Bt8370_FSTAT 0x017 /* Offline Framer Status */
69: #define FSTAT_INVALID 0x10 /* No candidate */
70: #define FSTAT_FOUND 0x08 /* Frame Search Successful */
71: #define FSTAT_TIMEOUT 0x04 /* Framer Search Timeout */
72: #define FSTAT_ACTIVE 0x02 /* Framer Active */
73: #define FSTAT_RXTXN 0x01 /* RX/TX Reframe Operation */
74: #define Bt8370_PIO 0x018 /* Programmable Input/Output */
75: #define PIO_ONESEC_IO 0x80 /* */
76: #define PIO_RDL_IO 0x40 /* */
77: #define PIO_TDL_IO 0x20 /* */
78: #define PIO_INDY_IO 0x10 /* */
79: #define PIO_RFSYNC_IO 0x08 /* */
80: #define PIO_RMSYNC_IO 0x04 /* */
81: #define PIO_TFSYNC_IO 0x02 /* */
82: #define PIO_TMSYNC_IO 0x01 /* */
83: #define Bt8370_POE 0x019 /* Programmable Output Enable */
84: #define POE_TDL_OE 0x20 /* */
85: #define POE_RDL_OE 0x10 /* */
86: #define POE_INDY_OE 0x08 /* */
87: #define POE_TCKO_OE 0x04 /* */
88: #define POE_CLADO_OE 0x02 /* */
89: #define POE_RCKO_OE 0x01 /* */
90: #define Bt8370_CMUX 0x01A /* Clock Input Mux */
91: #define CMUX_RSBCKI_RSBCKI 0x00 /* */
92: #define CMUX_RSBCKI_TSBCKI 0x40 /* */
93: #define CMUX_RSBCKI_CLADI 0x80 /* */
94: #define CMUX_RSBCKI_CLADO 0xC0 /* */
95: #define CMUX_TSBCKI_TSBCKI 0x00 /* */
96: #define CMUX_TSBCKI_RSBCKI 0x10 /* */
97: #define CMUX_TSBCKI_CLADI 0x20 /* */
98: #define CMUX_TSBCKI_CLADO 0x30 /* */
99: #define CMUX_CLADI_CLADI 0x00 /* */
100: #define CMUX_CLADI_RCKO 0x04 /* */
101: #define CMUX_CLADI_TSBCKI 0x08 /* */
102: #define CMUX_CLADI_TCKI 0x0C /* */
103: #define CMUX_TCKI_TCKI 0x00 /* */
104: #define CMUX_TCKI_RCKO 0x01 /* */
105: #define CMUX_TCKI_RSBCKI 0x02 /* */
106: #define CMUX_TCKI_CLADO 0x03 /* */
107: #define Bt8370_TMUX 0x01B /* Test Mux Configuration */
108: #define Bt8370_TEST 0x01C /* Test Configuration */
109: /* Receive LIU (RLIU) */
110: #define Bt8370_LIU_CR 0x020 /* LIU Configuration */
111: #define LIU_CR_RST_LIU 0x80 /* Reset RLIU */
112: #define LIU_CR_SQUELCH 0x40 /* Enable Squelch */
113: #define LIU_CR_FORCE_VGA 0x20 /* Internal Variable Gain Amp */
114: #define LIU_CR_RDIGI 0x10 /* Enable Receive Digital Inputs */
115: #define LIU_CR_ATTN0 0x00 /* Bridge Attenuation 0db */
116: #define LIU_CR_ATTN10 0x04 /* Bridge Attenuation -10db */
117: #define LIU_CR_ATTN20 0x08 /* Bridge Attenuation -20db */
118: #define LIU_CR_ATTN30 0x0C /* Bridge Attenuation -30db */
119: #define LIU_CR_MAGIC 0x01 /* This one must be enabled */
120: #define Bt8370_RSTAT 0x021 /* Receive LIU Status */
121: #define RSTAT_CPDERR 0x80 /* CLAD Phase detector lost lock */
122: #define RSTAT_JMPTY 0x40 /* JAT Empty/Full */
123: #define RSTAT_ZCSUB 0x20 /* ZCS detected */
124: #define RSTAT_EXZ 0x10 /* Excessive Zeros */
125: #define RSTAT_BPV 0x08 /* Bipolar Violations */
126: #define RSTAT_EYEOPEN 0x02 /* Equalization State */
127: #define RSTAT_PRE_EQ 0x01 /* Pre-Equalizer Status */
128: #define Bt8370_RLIU_CR 0x022 /* Receive LIU Configuration */
129: #define RLIU_CR_FRZ_SHORT 0x80 /* Freeze Equalizer for short lines */
130: #define RLIU_CR_HI_CLICE 0x40 /* High Clock Slicer Threshold */
131: #define RLIU_CR_AGC32 0x00 /* AGC Observation Window 32bit */
132: #define RLIU_CR_AGC128 0x10 /* AGC Observation Window 128bit */
133: #define RLIU_CR_AGC512 0x20 /* AGC Observation Window 512bit */
134: #define RLIU_CR_AGC2048 0x30 /* AGC Observation Window 2048bit */
135: #define RLIU_CR_EQ_FRZ 0x08 /* Freeze EQ Coefficients */
136: #define RLIU_CR_OOR_BLOCK 0x04 /* Disable automatic RLBO */
137: #define RLIU_CR_RLBO 0x02 /* Receiver Line Build Out */
138: #define RLIU_CR_LONG_EYE 0x01 /* Eye Open Timeout 8192bit */
139: #define Bt8370_LPF 0x023 /* RPLL Low Pass Filter */
140: #define Bt8370_VGA_MAX 0x024 /* Variable Gain Amplifier Maximum */
141: #define Bt8370_EQ_DAT 0x025 /* Equalizer Coefficient Data register */
142: #define Bt8370_EQ_PTR 0x026 /* Equalizer Coefficient Table Pointer */
143: #define Bt8370_DSLICE 0x027 /* Data Slicer Threshold */
144: #define Bt8370_EQ_OUT 0x028 /* Equalizer Output Levels */
145: #define Bt8370_VGA 0x029 /* Variable Gain Amplifier Status */
146: #define Bt8370_PRE_EQ 0x02A /* Pre-Equalizer */
147: #define Bt8370_COEFF 0x030 /* -037 *//* LMS Adjusted Equalizer Coefficient Status */
148: #define Bt8370_GAIN 0x038 /* -03C *//* Equalizer Gain Thresholds */
149: /* Digital Reveiver (RCVR) */
150: #define Bt8370_RCR0 0x040 /* Receiver Configuration */
151: #define RCR0_HDB3 0x00 /* */
152: #define RCR0_B8ZS 0x00 /* */
153: #define RCR0_AMI 0x80 /* */
154: #define RCR0_RABORT 0x40 /* */
155: #define RCR0_RFORCE 0x20 /* */
156: #define RCR0_LFA_FAS 0x18 /* 3 consecutive FAS Errors */
157: #define RCR0_LFA_FASCRC 0x08 /* 3 consecutive FAS or 915 CRC Errors */
158: #define RCR0_LFA_26F 0x08 /* 2 out of 6 F bit Errors */
159: #define RCR0_RZCS_BPV 0x00 /* */
160: #define RCR0_RZCS_NBPV 0x01 /* */
161: #define Bt8370_RPATT 0x041 /* Receive Test Pattern Configuration */
162: #define Bt8370_RLB 0x042 /* Receive Loopback Code Detector Configuration */
163: #define Bt8370_LBA 0x043 /* Loopback Activate Code Pattern */
164: #define Bt8370_LBD 0x044 /* Loopback Deactivate Code Pattern */
165: #define Bt8370_RALM 0x045 /* Receive Alarm Signal Configuration */
166: #define RALM_FSNFAS 0x20 /* Include FS/NFAS in FERR and FRED */
167: #define Bt8370_LATCH 0x046 /* Alarm/Error/Counter Latch Configuration */
168: #define LATCH_STOPCNT 0x08 /* Stop Error Counter during RLOF,RLOS,RAIS */
169: #define Bt8370_ALM1 0x047 /* Alarm 1 Status */
170: #define ALM1_RMYEL 0x80 /* Receive Multifram Yellow Alarm */
171: #define ALM1_RYEL 0x40 /* Receive Yellow Alarm */
172: #define ALM1_RAIS 0x10 /* Reveive Alarm Indication Signal */
173: #define ALM1_RALOS 0x09 /* Receive Analog Loss of Signal */
174: #define ALM1_RLOS 0x04 /* Receive Loss of Signal */
175: #define ALM1_RLOF 0x02 /* Receive Loss of Frame Alignment */
176: #define ALM1_SIGFRZ 0x01 /* Signalling Freeze */
177: #define Bt8370_ALM2 0x048 /* Alarm 2 Status */
178: #define ALM2_LOOPDN 0x80 /* */
179: #define ALM2_LOOPUP 0x40 /* */
180: #define ALM2_TSHORT 0x10 /* Transmit Short Circuit */
181: #define ALM2_TLOC 0x08 /* Transmit Loss of clock */
182: #define ALM2_TLOF 0x02 /* Transmit Loss of Frame alignment */
183: #define Bt8370_ALM3 0x049 /* Alarm 3 Status */
184: #define ALM3_RMAIS 0x40 /* Receive TS16 Alarm Indication */
185: #define ALM3_SEF 0x20 /* Severely Errored Frame */
186: #define ALM3_SRED 0x10 /* Loss of CAS Alignment */
187: #define ALM3_MRED 0x08 /* Loss of MFAS Alignment */
188: #define ALM3_FRED 0x04 /* Loss of T1/FAS Alignment */
189: #define ALM3_LOF1 0x02 /* Reason for Loss of Frame Alignment */
190: #define ALM3_LOF0 0x01 /* Reason for Loss of Frame Alignment */
191: /* Error/Alarm Counters */
192: #define Bt8370_FERR_LSB 0x050 /* Framing Bit Error Counter LSB */
193: #define Bt8370_FERR_MSB 0x051 /* ditto MSB */
194: #define Bt8370_CERR_LSB 0x052 /* CRC Error Counter LSB */
195: #define Bt8370_CERR_MSB 0x053 /* ditto MSB */
196: #define Bt8370_LCV_LSB 0x054 /* Line Code Violation Counter LSB*/
197: #define Bt8370_LCV_MSB 0x055 /* ditto MSB */
198: #define Bt8370_FEBE_LSB 0x056 /* Far End Block Error Counter LSB*/
199: #define Bt8370_FEBE_MSB 0x057 /* ditto MSB */
200: #define Bt8370_BERR_LSB 0x058 /* PRBS Bit Error Counter LSB */
201: #define Bt8370_BERR_MSB 0x059 /* ditto MSB */
202: /* Receive Sa-Byte */
203: #define Bt8370_RSA4 0x05B /* Receive Sa4 Byte Buffer */
204: #define Bt8370_RSA5 0x05C /* ditto Sa5 */
205: #define Bt8370_RSA6 0x05D /* ditto Sa6 */
206: #define Bt8370_RSA7 0x05E /* ditto Sa7 */
207: #define Bt8370_RSA8 0x05F /* ditto Sa8 */
208: /* Transmit LIU (TLIU) */
209: #define Bt8370_SHAPE 0x060 /* -067 *//* Transmit Pulse Shape Configuration */
210: #define Bt8370_TLIU_CR 0x068 /* Transmit LIU Configuration */
211: #define TLIU_CR_120 0x4C /* 120 Ohms, external term */
212: #define TLIU_CR_100 0x40 /* 100 Ohms, external term */
213: /* Digital Transmitter (XMTR) */
214: #define Bt8370_TCR0 0x070 /* Transmit Framer Configuration */
215: #define TCR0_FAS 0x00 /* FAS Only */
216: #define TCR0_MFAS 0x04 /* FAS + MFAS*/
217: #define TCR0_SF 0x04 /* SF Only */
218: #define TCR0_ESF 0x01 /* ESF Only */
219: #define TCR0_ESFCRC 0x0D /* ESF + Force CRC */
220: #define Bt8370_TCR1 0x071 /* Transmitter Configuration */
221: #define TCR1_TABORT 0x40 /* Disable TX Offline Framer */
222: #define TCR1_TFORCE 0x20 /* Force TX Reframe */
223: #define TCR1_HDB3 0x01 /* Line code HDB3 */
224: #define TCR1_B8ZS 0x01 /* Line code B8ZS */
225: #define TCR1_AMI 0x00 /* Line code AMI */
226: #define TCR1_3FAS 0x10 /* 3 consecutive FAS Errors */
227: #define TCR1_26F 0x10 /* 2 out of 6 Frame Bit Errors */
228: #define Bt8370_TFRM 0x072 /* Transmit Frame Format */
229: #define TFRM_MYEL 0x20 /* Insert MultiFrame Yellow Alarm */
230: #define TFRM_YEL 0x10 /* Insert Yellow Alarm */
231: #define TFRM_MF 0x08 /* Insert MultiFrame Alignment */
232: #define TFRM_FE 0x04 /* Insert FEBE */
233: #define TFRM_CRC 0x02 /* Insert CRC4 */
234: #define TFRM_FBIT 0x01 /* Insert F bit or FAS/NAS alignment */
235: #define Bt8370_TERROR 0x073 /* Transmit Error Insert */
236: #define Bt8370_TMAN 0x074 /* Transmit Manual Sa-Byte/FEBE Configuration */
237: #define TMAN_MALL 0xF8 /* All Sa Bytes Manual */
238: #define Bt8370_TALM 0x075 /* Transmit Alarm Signal Configuration */
239: #define TALM_AMYEL 0x20 /* Automatic MultiFrame Yellow Alarm transmit */
240: #define TALM_AYEL 0x10 /* Automatic Yellow Alarm transmit */
241: #define TALM_AAIS 0x08 /* Automatic AIS Alarm transmit */
242: #define Bt8370_TPATT 0x076 /* Transmit Test Pattern Configuration */
243: #define Bt8370_TLB 0x077 /* Transmit Inband Loopback Code Configuration */
244: #define Bt8370_LBP 0x078 /* Transmit Inband Loopback Code Pattern */
245: /* Transmit Sa-Byte */
246: #define Bt8370_TSA4 0x07B /* Transmit Sa4 Byte Buffer */
247: #define Bt8370_TSA5 0x07C /* ditto Sa5 */
248: #define Bt8370_TSA6 0x07D /* ditto Sa6 */
249: #define Bt8370_TSA7 0x07E /* ditto Sa7 */
250: #define Bt8370_TSA8 0x07F /* ditto Sa8 */
251: /* Clock Rate Adapter (CLAD) */
252: #define Bt8370_CLAD_CR 0x090 /* Clock Rate Adapter Configuration */
253: #define CLAD_CR_CEN 0x80 /* Enable CLAD phase detector */
254: #define CLAD_CR_XSEL_1X 0x00 /* Line rate multiplier 1X */
255: #define CLAD_CR_XSEL_2X 0x10 /* Line rate multiplier 2X */
256: #define CLAD_CR_XSEL_4X 0x20 /* Line rate multiplier 4X */
257: #define CLAD_CR_XSEL_8X 0x30 /* Line rate multiplier 8X */
258: #define CLAD_CR_LFGAIN 0x05 /* Loop filter gain */
259: #define Bt8370_CSEL 0x091 /* CLAD Frequency Select */
260: #define CSEL_VSEL_1536 0x60 /* 1536kHz */
261: #define CSEL_VSEL_1544 0x50 /* 1544kHz */
262: #define CSEL_VSEL_2048 0x10 /* 2048kHz */
263: #define CSEL_VSEL_4096 0x20 /* 4096kHz */
264: #define CSEL_VSEL_8192 0x30 /* 8192kHz */
265: #define CSEL_OSEL_1536 0x06 /* 1536kHz */
266: #define CSEL_OSEL_1544 0x05 /* 1544kHz */
267: #define CSEL_OSEL_2048 0x01 /* 2048kHz */
268: #define CSEL_OSEL_4096 0x02 /* 4096kHz */
269: #define CSEL_OSEL_8192 0x03 /* 8192kHz */
270: #define Bt8370_CPHASE 0x092 /* CLAD Phase Detector Scale Factor */
271: #define Bt8370_CTEST 0x093 /* CLAD Test */
272: /* Bit Oriented Protocol Transceiver (BOP) */
273: #define Bt8370_BOP 0x0A0 /* Bit Oriented Protocol Transceiver */
274: #define Bt8370_TBOP 0x0A1 /* Transmit BOP Code Word */
275: #define Bt8370_RBOP 0x0A2 /* Receive BOP Code Word */
276: #define Bt8370_BOP_STAT 0x0A3 /* BOP Status */
277: /* Data Link #1 */
278: #define Bt8370_DL1_TS 0x0A4 /* DL1 Time Slot Enable */
279: #define Bt8370_DL1_BIT 0x0A5 /* DL1 Bit Enable */
280: #define Bt8370_DL1_CTL 0x0A6 /* DL1 Control */
281: #define Bt8370_RDL1_FFC 0x0A7 /* RDL #1 FIFO Fill Control */
282: #define Bt8370_RDL1 0x0A8 /* Receive Data Link FIFO #1 */
283: #define Bt8370_RDL1_STAT 0x0A9 /* RDL #1 Status */
284: #define Bt8370_PRM1 0x0AA /* Performance Report Message */
285: #define Bt8370_TDL1_FEC 0x0AB /* TDL #1 FIFO Empty Control */
286: #define Bt8370_TDL1_EOM 0x0AC /* TDL #1 End of Message Control */
287: #define Bt8370_TDL1 0x0AD /* Transmit Data Link FIFO #1*/
288: #define Bt8370_TDL1_STAT 0x0AE /* TDL #1 Status */
289: /* Data Link #2 */
290: #define Bt8370_DL2_TS 0x0AF /* DL2 Time Slot Enable */
291: #define Bt8370_DL2_BIT 0x0B0 /* DL2 Bit Enable */
292: #define Bt8370_DL2_CTL 0x0B1 /* DL2 Control */
293: #define Bt8370_RDL2_FFC 0x0B2 /* RDL #2 FIFO Fill Control */
294: #define Bt8370_RDL2 0x0B3 /* Receive Data Link FIFO #2 */
295: #define Bt8370_RDL2_STAT 0x0B4 /* RDL #2 Status */
296: #define Bt8370_TDL2_FEC 0x0B6 /* TDL #2 FIFO Empty Control */
297: #define Bt8370_TDL2_EOM 0x0B7 /* TDL #2 End of Message Control */
298: #define Bt8370_TDL2 0x0B8 /* Transmit Data Link FIFO #2*/
299: #define Bt8370_TDL2_STAT 0x0B9 /* TDL #2 Status */
300: /* Test */
301: #define Bt8370_TEST1 0x0BA /* DLINK Test Configuration */
302: #define Bt8370_TEST2 0x0BB /* DLINK Test Status */
303: #define Bt8370_TEST3 0x0BC /* DLINK Test Status */
304: #define Bt8370_TEST4 0x0BD /* DLINK Test Control #1 or Configuration #2 */
305: #define Bt8370_TEST5 0x0BE /* DLINK Test Control #2 or Configuration #2 */
306: /* System Bus Interface (SBI) */
307: #define Bt8370_SBI_CR 0x0D0 /* System Bus Interface Configuration */
308: #define SBI_CR_X2CLK 0x80 /* Times 2 clock */
309: #define SBI_CR_SBI_OE 0x40 /* Enable SBI */
310: #define SBI_CR_1536 0x08 /* 1536, 24TS*/
311: #define SBI_CR_1544 0x07 /* 1544, 24TS + F bit */
312: #define SBI_CR_2048 0x06 /* 2048, 32TS */
313: #define SBI_CR_4096_A 0x04 /* 4096 Group A */
314: #define SBI_CR_4096_B 0x05 /* 4096 Group B */
315: #define SBI_CR_8192_A 0x00 /* 8192 Group A */
316: #define SBI_CR_8192_B 0x01 /* 8192 Group B */
317: #define SBI_CR_8192_C 0x02 /* 8192 Group C */
318: #define SBI_CR_8192_D 0x03 /* 8192 Group D */
319: #define Bt8370_RSB_CR 0x0D1 /* Receive System Bus Configuration */
320: #define RSB_CR_BUS_RSB 0x80 /* Multiple devices on bus */
321: #define RSB_CR_SIG_OFF 0x40 /* Inhibit RPCMO Signal reinsertion */
322: #define RSB_CR_RPCM_NEG 0x20 /* RSB falling edge */
323: #define RSB_CR_RSYN_NEG 0x10 /* RFSYNC falling edge */
324: #define RSB_CR_BUS_FRZ 0x08 /* Multiple devices on bus */
325: #define RSB_CR_RSB_CTR 0x04 /* Force RSLIP Center */
326: #define RSB_CR_RSBI_NORMAL 0x00 /* Normal Slip Buffer Mode */
327: #define RSB_CR_RSBI_ELASTIC 0x02 /* Receive Slip Buffer Elastic Mode */
328: #define RSB_CR_RSBI_BYPASS 0x03 /* Bypass Slip Buffer */
329: #define Bt8370_RSYNC_BIT 0x0D2 /* Receive System Bus Sync Bit Offset */
330: #define Bt8370_RSYNC_TS 0x0D3 /* Receive System Bus Sync Time Slot Offset */
331: #define Bt8370_TSB_CR 0x0D4 /* Transmit System Bus Configuration */
332: #define TSB_CR_BUS_TSB 0x80 /* Bused TSB output */
333: #define TSB_CR_TPCM_NEG 0x20 /* TINDO falling edge */
334: #define TSB_CR_TSYN_NEG 0x10 /* TFSYNC falling edge */
335: #define TSB_CR_TSB_CTR 0x04 /* Force TSLIP Center */
336: #define TSB_CR_TSB_NORMAL 0x00 /* Normal Slip Buffer Mode */
337: #define TSB_CR_TSB_ELASTIC 0x02 /* Send Slip Buffer Elastic Mode */
338: #define TSB_CR_TSB_BYPASS 0x03 /* Bypass Slip Buffer */
339: #define Bt8370_TSYNC_BIT 0x0D5 /* Transmit System Bus Sync Bit Offset */
340: #define Bt8370_TSYNC_TS 0x0D6 /* Transmit System Bus Sync Time Slot Offset */
341: #define Bt8370_RSIG_CR 0x0D7 /* Receive Signaling Configuration */
342: #define RSIG_CR_FRZ_OFF 0x04 /* Manual Signaling Update FRZ */
343: #define RSIG_CR_THRU 0x01 /* Transparent Robbed Bit Signaling */
344: #define Bt8370_RSYNC_FRM 0x0D8 /* Signaling Reinsertion Frame Offset */
345: #define Bt8370_SSTAT 0x0D9 /* Slip Buffer Status */
346: #define SSTAT_TSDIR 0x80 /* Transmit Slip Direction */
347: #define SSTAT_TFSLIP 0x40 /* Controlled Slip Event */
348: #define SSTAT_TUSLIP 0x20 /* Uncontrolled Slip Event */
349: #define SSTAT_RSDIR 0x08 /* Receive Slip Direction */
350: #define SSTAT_RFSLIP 0x04 /* Controlled Slip Event */
351: #define SSTAT_RUSLIP 0x02 /* Uncontrolled Slip Event */
352: #define Bt8370_STACK 0x0DA /* Receive Signaling Stack */
353: #define Bt8370_RPHASE 0x0DB /* RSLIP Phase Status */
354: #define Bt8370_TPHASE 0x0DC /* TSLIP Phase Status */
355: #define Bt8370_PERR 0x0DD /* RAM Parity Status */
356: #define Bt8370_SBCn 0x0E0 /* -0FF *//* System Bus Per-Channel Control */
357: #define SBCn_INSERT 0x40 /* Insert RX Signaling on RPCMO */
358: #define SBCn_SIG_LP 0x20 /* Local Signaling Loopback */
359: #define SBCn_RLOOP 0x10 /* Local Loopback */
360: #define SBCn_RINDO 0x08 /* Activate RINDO time slot indicator */
361: #define SBCn_TINDO 0x04 /* Activate TINDO time slot indicator */
362: #define SBCn_TSIG_AB 0x02 /* AB Signaling */
363: #define SBCn_ASSIGN 0x01 /* Enable System Bus Time Slot */
364: /* Buffer Memory */
365: #define Bt8370_TPCn 0x100 /* Transmit Per-Channel Control */
366: #define TPCn_CLEAR 0x00 /* Clear Channel Mode */
367: #define TPCn_EMFBIT 0x80 /* TB7ZS/EMFBIT */
368: #define TPCn_TLOOP 0x40 /* Remote DS0 Channel Loopback */
369: #define TPCn_TIDLE 0x20 /* Transmit Idle */
370: #define TPCn_TLOCAL 0x10 /* Transmit Local Signaling */
371: #define TPCn_TSIGA 0x08 /* ABCD signaling value */
372: #define TPCn_TSIGB 0x04 /* ABCD signaling value */
373: #define TPCn_TSIGC 0x02 /* ABCD signaling value */
374: #define TPCn_TSIGD 0x01 /* ABCD signaling value */
375: #define TPCn_TSIGO TPCn_TSIGA /* Transmit Signaling Output */
376: #define TPCn_RSIGO TPCn_TSIGB /* Receive Signaling Output */
377: #define Bt8370_TSIGn 0x120 /* Transmit Signaling Buffer */
378: #define Bt8370_TSLIP_LOn 0x140 /* Transmit PCM Slip Buffer */
379: #define Bt8370_TSLIP_HIn 0x160 /* Transmit PCM Slip Buffer */
380: #define Bt8370_RPCn 0x180 /* Receive Per-Channel Control */
381: #define RPCn_CLEAR 0x00 /* Clear Channel Mode */
382: #define RPCn_RSIG_AB 0x80 /* AB Signaling */
383: #define RPCn_RIDLE 0x40 /* Time Slot Idle */
384: #define RPCn_SIG_STK 0x20 /* Receive Signal Stack */
385: #define RPCn_RLOCAL 0x10 /* Enable Local Signaling Output */
386: #define RPCn_RSIGA 0x08 /* Local Receive Signaling */
387: #define RPCn_RSIGB 0x04 /* Local Receive Signaling */
388: #define RPCn_RSIGC 0x02 /* Local Receive Signaling */
389: #define RPCn_RSIGD 0x01 /* Local Receive Signaling */
390: #define Bt8370_RSIGn 0x1A0 /* Receive Signaling Buffer */
391: #define Bt8370_RSLIP_LOn 0x1C0 /* Receive PCM Slip Buffer */
392: #define Bt8370_RSLIP_HIn 0x1E0 /* Receive PCM Slip Buffer */
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