Annotation of sys/dev/pci/bt8370.c, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: bt8370.c,v 1.7 2006/01/31 16:51:13 claudio Exp $ */
! 2:
! 3: /*
! 4: * Copyright (c) 2004,2005 Internet Business Solutions AG, Zurich, Switzerland
! 5: * Written by: Andre Oppermann <oppermann@accoom.net>
! 6: *
! 7: * Permission to use, copy, modify, and distribute this software for any
! 8: * purpose with or without fee is hereby granted, provided that the above
! 9: * copyright notice and this permission notice appear in all copies.
! 10: *
! 11: * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
! 12: * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
! 13: * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
! 14: * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
! 15: * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
! 16: * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
! 17: * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
! 18: */
! 19: #include <sys/param.h>
! 20: #include <sys/types.h>
! 21:
! 22: #include <sys/device.h>
! 23: #include <sys/systm.h>
! 24: #include <sys/socket.h>
! 25: #include <sys/sockio.h>
! 26: #include <sys/syslog.h>
! 27:
! 28: #include <net/if.h>
! 29: #include <net/if_media.h>
! 30: #include <net/if_types.h>
! 31: #include <net/if_sppp.h>
! 32:
! 33: #include <netinet/in.h>
! 34: #include <netinet/if_ether.h>
! 35:
! 36: #include <machine/cpu.h>
! 37: #include <machine/bus.h>
! 38:
! 39: #include "musyccreg.h"
! 40: #include "musyccvar.h"
! 41: #include "if_art.h"
! 42: #include "bt8370reg.h"
! 43:
! 44: #define FRAMER_LIU_E1_120 1
! 45: #define FRAMER_LIU_T1_133 2
! 46:
! 47: void bt8370_set_sbi_clock_mode(struct art_softc *, enum art_sbi_type,
! 48: u_int, int);
! 49: void bt8370_set_bus_mode(struct art_softc *, enum art_sbi_mode, int);
! 50: void bt8370_set_line_buildout(struct art_softc *, int);
! 51: void bt8370_set_loopback_mode(struct art_softc *, enum art_loopback);
! 52: void bt8370_set_bop_mode(struct art_softc *ac, int);
! 53: void bt8370_set_dl_1_mode(struct art_softc *, int);
! 54: void bt8370_set_dl_2_mode(struct art_softc *, int);
! 55: void bt8370_intr_enable(struct art_softc *ac, int);
! 56:
! 57: #ifndef ACCOOM_DEBUG
! 58: #define bt8370_print_status(x)
! 59: #define bt8370_print_counters(x)
! 60: #define bt8370_dump_registers(x)
! 61: #else
! 62: void bt8370_print_status(struct art_softc *);
! 63: void bt8370_print_counters(struct art_softc *);
! 64: void bt8370_dump_registers(struct art_softc *);
! 65: #endif
! 66:
! 67: int
! 68: bt8370_reset(struct art_softc *ac)
! 69: {
! 70: u_int8_t cr0;
! 71:
! 72: ebus_write(&ac->art_ebus, Bt8370_CR0, 0x00);
! 73: DELAY(10); /* 10 microseconds */
! 74: ebus_write(&ac->art_ebus, Bt8370_CR0, CR0_RESET);
! 75: DELAY(20); /* 20 microseconds */
! 76: ebus_write(&ac->art_ebus, Bt8370_CR0, 0x00);
! 77: cr0 = ebus_read(&ac->art_ebus, Bt8370_CR0);
! 78: if (cr0 != 0x0) {
! 79: log(LOG_ERR, "%s: reset not successful\n",
! 80: ac->art_dev.dv_xname);
! 81: return (-1);
! 82: }
! 83: return (0);
! 84: }
! 85:
! 86: int
! 87: bt8370_set_frame_mode(struct art_softc *ac, enum art_sbi_type type, u_int mode,
! 88: u_int clockmode)
! 89: {
! 90: int channels;
! 91:
! 92: /* Get into a clean state */
! 93: bt8370_reset(ac);
! 94:
! 95: /* Disable all interrupts to be sure */
! 96: bt8370_intr_enable(ac, 0);
! 97:
! 98: switch (mode) {
! 99: case IFM_TDM_E1: /* 32 payload channels, bit transparent */
! 100: channels = 32;
! 101:
! 102: /* Global Config */
! 103: ebus_write(&ac->art_ebus, Bt8370_CR0, CR0_E1_FAS);
! 104:
! 105: /* Primary Config */
! 106: bt8370_set_loopback_mode(ac, ART_NOLOOP);
! 107: ebus_write(&ac->art_ebus, Bt8370_DL3_TS, 0x00);
! 108:
! 109: /* Timing and Clock Config */
! 110: bt8370_set_sbi_clock_mode(ac, type, clockmode, channels);
! 111:
! 112: /* Receiver RLIU, RCVR */
! 113: bt8370_set_line_buildout(ac, FRAMER_LIU_E1_120);
! 114: /* This one is critical */
! 115: ebus_write(&ac->art_ebus, Bt8370_RCR0, RCR0_HDB3 |
! 116: RCR0_RABORT | RCR0_LFA_FAS | RCR0_RZCS_NBPV);
! 117: ebus_write(&ac->art_ebus, Bt8370_RALM, 0x00);
! 118: ebus_write(&ac->art_ebus, Bt8370_LATCH, LATCH_STOPCNT);
! 119:
! 120: /* Transmitter TLIU, XMTR */
! 121: ebus_write(&ac->art_ebus, Bt8370_TCR0, TCR0_FAS);
! 122: ebus_write(&ac->art_ebus, Bt8370_TCR1, TCR1_TABORT |
! 123: TCR1_HDB3);
! 124: ebus_write(&ac->art_ebus, Bt8370_TFRM, 0x00);
! 125: ebus_write(&ac->art_ebus, Bt8370_TMAN, 0x00);
! 126: ebus_write(&ac->art_ebus, Bt8370_TALM, 0x00);
! 127: ebus_write(&ac->art_ebus, Bt8370_TPATT, 0x00);
! 128: ebus_write(&ac->art_ebus, Bt8370_TLB, 0x00);
! 129: ebus_write(&ac->art_ebus, Bt8370_TSA4, 0xFF);
! 130: ebus_write(&ac->art_ebus, Bt8370_TSA5, 0xFF);
! 131: ebus_write(&ac->art_ebus, Bt8370_TSA6, 0xFF);
! 132: ebus_write(&ac->art_ebus, Bt8370_TSA7, 0xFF);
! 133: ebus_write(&ac->art_ebus, Bt8370_TSA8, 0xFF);
! 134:
! 135: /* Bit Oriented Protocol Transceiver BOP disabled */
! 136: bt8370_set_bop_mode(ac, 0);
! 137:
! 138: /* Data Link #1 disabled */
! 139: bt8370_set_dl_1_mode(ac, 0);
! 140:
! 141: /* Data Link #2 disabled */
! 142: bt8370_set_dl_2_mode(ac, 0);
! 143:
! 144: ACCOOM_PRINTF(1, ("%s: set to E1 G.703 unframed, HDB3\n",
! 145: ac->art_dev.dv_xname));
! 146: break;
! 147: case IFM_TDM_E1_G704: /* 31 payload channels, byte aligned */
! 148: channels = 32;
! 149:
! 150: /* Global Config */
! 151: ebus_write(&ac->art_ebus, Bt8370_CR0, CR0_E1_FAS);
! 152:
! 153: /* Primary Config */
! 154: bt8370_set_loopback_mode(ac, ART_NOLOOP);
! 155: ebus_write(&ac->art_ebus, Bt8370_DL3_TS, 0x00);
! 156:
! 157: /* Timing and Clock Config */
! 158: bt8370_set_sbi_clock_mode(ac, type, clockmode, channels);
! 159:
! 160: /* Receiver RLIU, RCVR */
! 161: bt8370_set_line_buildout(ac, FRAMER_LIU_E1_120);
! 162: /* This one is critical */
! 163: ebus_write(&ac->art_ebus, Bt8370_RCR0, RCR0_RFORCE |
! 164: RCR0_HDB3 | RCR0_LFA_FAS | RCR0_RZCS_NBPV);
! 165: ebus_write(&ac->art_ebus, Bt8370_RALM, RALM_FSNFAS);
! 166: ebus_write(&ac->art_ebus, Bt8370_LATCH, LATCH_STOPCNT);
! 167:
! 168: /* Transmitter TLIU, XMTR */
! 169: ebus_write(&ac->art_ebus, Bt8370_TCR0, TCR0_FAS);
! 170: /* This one is critical */
! 171: ebus_write(&ac->art_ebus, Bt8370_TCR1, TCR1_TABORT |
! 172: TCR1_3FAS | TCR1_HDB3);
! 173: ebus_write(&ac->art_ebus, Bt8370_TFRM, TFRM_YEL |
! 174: TFRM_FBIT);
! 175: ebus_write(&ac->art_ebus, Bt8370_TMAN, TMAN_MALL);
! 176: ebus_write(&ac->art_ebus, Bt8370_TALM, TALM_AYEL);
! 177: ebus_write(&ac->art_ebus, Bt8370_TPATT, 0x00);
! 178: ebus_write(&ac->art_ebus, Bt8370_TLB, 0x00);
! 179: ebus_write(&ac->art_ebus, Bt8370_TSA4, 0xFF);
! 180: ebus_write(&ac->art_ebus, Bt8370_TSA5, 0xFF);
! 181: ebus_write(&ac->art_ebus, Bt8370_TSA6, 0xFF);
! 182: ebus_write(&ac->art_ebus, Bt8370_TSA7, 0xFF);
! 183: ebus_write(&ac->art_ebus, Bt8370_TSA8, 0xFF);
! 184:
! 185: /* Bit Oriented Protocol Transceiver BOP disabled */
! 186: bt8370_set_bop_mode(ac, 0);
! 187:
! 188: /* Data Link #1 disabled */
! 189: bt8370_set_dl_1_mode(ac, 0);
! 190:
! 191: /* Data Link #2 disabled */
! 192: bt8370_set_dl_2_mode(ac, 0);
! 193:
! 194: ACCOOM_PRINTF(1, ("%s: set to E1 G.704, HDB3\n",
! 195: ac->art_dev.dv_xname));
! 196: break;
! 197: case IFM_TDM_E1_G704_CRC4: /* 31 payload channels, byte aligned */
! 198: channels = 32;
! 199:
! 200: /*
! 201: * Over normal G.704 the following registers need changes:
! 202: * CR0 = +CRC
! 203: * TFRM = +INS_CRC
! 204: */
! 205:
! 206: /* Global Config */
! 207: ebus_write(&ac->art_ebus, Bt8370_CR0, CR0_E1_FAS_CRC);
! 208:
! 209: /* Primary Config */
! 210: bt8370_set_loopback_mode(ac, ART_NOLOOP);
! 211: ebus_write(&ac->art_ebus, Bt8370_DL3_TS, 0x00);
! 212:
! 213: /* Timing and Clock Config */
! 214: bt8370_set_sbi_clock_mode(ac, type, clockmode, channels);
! 215:
! 216: /* Receiver RLIU, RCVR */
! 217: bt8370_set_line_buildout(ac, FRAMER_LIU_E1_120);
! 218: /* This one is critical */
! 219: ebus_write(&ac->art_ebus, Bt8370_RCR0, RCR0_RFORCE |
! 220: RCR0_HDB3 | RCR0_LFA_FASCRC | RCR0_RZCS_NBPV);
! 221: ebus_write(&ac->art_ebus, Bt8370_RALM, RALM_FSNFAS);
! 222: ebus_write(&ac->art_ebus, Bt8370_LATCH, LATCH_STOPCNT);
! 223:
! 224: /* Transmitter TLIU, XMTR */
! 225: ebus_write(&ac->art_ebus, Bt8370_TCR0, TCR0_MFAS);
! 226: /* This one is critical */
! 227: ebus_write(&ac->art_ebus, Bt8370_TCR1, TCR1_TABORT |
! 228: TCR1_3FAS | TCR1_HDB3);
! 229: ebus_write(&ac->art_ebus, Bt8370_TFRM, TFRM_YEL |
! 230: TFRM_MF | TFRM_FE | TFRM_CRC | TFRM_FBIT);
! 231: ebus_write(&ac->art_ebus, Bt8370_TMAN, TMAN_MALL);
! 232: ebus_write(&ac->art_ebus, Bt8370_TALM, TALM_AYEL | TALM_AAIS);
! 233: ebus_write(&ac->art_ebus, Bt8370_TPATT, 0x00);
! 234: ebus_write(&ac->art_ebus, Bt8370_TLB, 0x00);
! 235: ebus_write(&ac->art_ebus, Bt8370_TSA4, 0xFF);
! 236: ebus_write(&ac->art_ebus, Bt8370_TSA5, 0xFF);
! 237: ebus_write(&ac->art_ebus, Bt8370_TSA6, 0xFF);
! 238: ebus_write(&ac->art_ebus, Bt8370_TSA7, 0xFF);
! 239: ebus_write(&ac->art_ebus, Bt8370_TSA8, 0xFF);
! 240:
! 241: /* Bit Oriented Protocol Transceiver BOP disabled */
! 242: bt8370_set_bop_mode(ac, 0);
! 243:
! 244: /* Data Link #1 disabled */
! 245: bt8370_set_dl_1_mode(ac, 0);
! 246:
! 247: /* Data Link #2 disabled */
! 248: bt8370_set_dl_2_mode(ac, 0);
! 249:
! 250: ACCOOM_PRINTF(1, ("%s: set to E1 G.704 CRC4, HDB3\n",
! 251: ac->art_dev.dv_xname));
! 252: break;
! 253: case IFM_TDM_T1_AMI: /* 24 payload channels, byte aligned */
! 254: channels = 25; /* zero is ignored for T1 */
! 255:
! 256: /* Global Config */
! 257: ebus_write(&ac->art_ebus, Bt8370_CR0, CR0_T1_SF);
! 258:
! 259: /* Primary Config */
! 260: bt8370_set_loopback_mode(ac, ART_NOLOOP);
! 261: ebus_write(&ac->art_ebus, Bt8370_DL3_TS, 0x00);
! 262:
! 263: /* Timing and Clock Config */
! 264: bt8370_set_sbi_clock_mode(ac, type, clockmode, channels);
! 265:
! 266: /* Receiver RLIU, RCVR */
! 267: bt8370_set_line_buildout(ac, FRAMER_LIU_T1_133);
! 268: /* This one is critical */
! 269: ebus_write(&ac->art_ebus, Bt8370_RCR0, RCR0_RFORCE |
! 270: RCR0_AMI | RCR0_LFA_26F | RCR0_RZCS_NBPV);
! 271: ebus_write(&ac->art_ebus, Bt8370_RALM, RALM_FSNFAS);
! 272: ebus_write(&ac->art_ebus, Bt8370_LATCH, LATCH_STOPCNT);
! 273:
! 274: /* Transmitter TLIU, XMTR */
! 275: ebus_write(&ac->art_ebus, Bt8370_TCR0, TCR0_SF);
! 276: /* This one is critical */
! 277: ebus_write(&ac->art_ebus, Bt8370_TCR1, TCR1_TABORT |
! 278: TCR1_26F | TCR1_AMI);
! 279: ebus_write(&ac->art_ebus, Bt8370_TFRM, TFRM_YEL |
! 280: TFRM_MF | TFRM_FBIT);
! 281: ebus_write(&ac->art_ebus, Bt8370_TMAN, 0x00);
! 282: ebus_write(&ac->art_ebus, Bt8370_TALM, TALM_AYEL);
! 283: ebus_write(&ac->art_ebus, Bt8370_TPATT, 0x00);
! 284: ebus_write(&ac->art_ebus, Bt8370_TLB, 0x00);
! 285: ebus_write(&ac->art_ebus, Bt8370_TSA4, 0xFF);
! 286: ebus_write(&ac->art_ebus, Bt8370_TSA5, 0xFF);
! 287: ebus_write(&ac->art_ebus, Bt8370_TSA6, 0xFF);
! 288: ebus_write(&ac->art_ebus, Bt8370_TSA7, 0xFF);
! 289: ebus_write(&ac->art_ebus, Bt8370_TSA8, 0xFF);
! 290:
! 291: /* Bit Oriented Protocol Transceiver BOP disabled */
! 292: bt8370_set_bop_mode(ac, 0);
! 293:
! 294: /* Data Link #1 disabled */
! 295: bt8370_set_dl_1_mode(ac, 0);
! 296:
! 297: /* Data Link #2 disabled */
! 298: bt8370_set_dl_2_mode(ac, 0);
! 299:
! 300: ACCOOM_PRINTF(1, ("%s: set to T1 SF, AMI\n",
! 301: ac->art_dev.dv_xname));
! 302: break;
! 303: case IFM_TDM_T1: /* 24 payload channels, byte aligned */
! 304: channels = 25; /* zero is ignored for T1 */
! 305:
! 306: /* Global Config */
! 307: ebus_write(&ac->art_ebus, Bt8370_CR0, CR0_T1_ESF);
! 308:
! 309: /* Primary Config */
! 310: bt8370_set_loopback_mode(ac, ART_NOLOOP);
! 311: ebus_write(&ac->art_ebus, Bt8370_DL3_TS, 0x00);
! 312:
! 313: /* Timing and Clock Config */
! 314: bt8370_set_sbi_clock_mode(ac, type, clockmode, channels);
! 315:
! 316: /* Receiver RLIU, RCVR */
! 317: bt8370_set_line_buildout(ac, FRAMER_LIU_T1_133);
! 318: /* This one is critical */
! 319: ebus_write(&ac->art_ebus, Bt8370_RCR0, RCR0_RFORCE |
! 320: RCR0_B8ZS | RCR0_LFA_26F | RCR0_RZCS_NBPV);
! 321: ebus_write(&ac->art_ebus, Bt8370_RLB, 0x09);
! 322: ebus_write(&ac->art_ebus, Bt8370_LBA, 0x08);
! 323: ebus_write(&ac->art_ebus, Bt8370_LBD, 0x24);
! 324: ebus_write(&ac->art_ebus, Bt8370_RALM, 0x00);
! 325: ebus_write(&ac->art_ebus, Bt8370_LATCH, LATCH_STOPCNT);
! 326:
! 327: /* Transmitter TLIU, XMTR */
! 328: ebus_write(&ac->art_ebus, Bt8370_TCR0, TCR0_ESFCRC);
! 329: /* This one is critical */
! 330: ebus_write(&ac->art_ebus, Bt8370_TCR1, TCR1_TABORT |
! 331: TCR1_26F | TCR1_B8ZS);
! 332: ebus_write(&ac->art_ebus, Bt8370_TFRM, TFRM_CRC |
! 333: TFRM_FBIT);
! 334: ebus_write(&ac->art_ebus, Bt8370_TMAN, 0x00);
! 335: ebus_write(&ac->art_ebus, Bt8370_TALM, TALM_AYEL);
! 336: ebus_write(&ac->art_ebus, Bt8370_TPATT, 0x00);
! 337: ebus_write(&ac->art_ebus, Bt8370_TLB, 0x00);
! 338: ebus_write(&ac->art_ebus, Bt8370_TSA4, 0xFF);
! 339: ebus_write(&ac->art_ebus, Bt8370_TSA5, 0xFF);
! 340: ebus_write(&ac->art_ebus, Bt8370_TSA6, 0xFF);
! 341: ebus_write(&ac->art_ebus, Bt8370_TSA7, 0xFF);
! 342: ebus_write(&ac->art_ebus, Bt8370_TSA8, 0xFF);
! 343:
! 344: /* Bit Oriented Protocol Transceiver BOP setup */
! 345: bt8370_set_bop_mode(ac, ART_BOP_ESF);
! 346:
! 347: /* Data Link #1 set to BOP mode for FDL */
! 348: bt8370_set_dl_1_mode(ac, ART_DL1_BOP);
! 349:
! 350: /* Data Link #2 disabled */
! 351: bt8370_set_dl_2_mode(ac, 0);
! 352:
! 353: ACCOOM_PRINTF(1, ("%s: set to T1 ESF CRC6, B8ZS\n",
! 354: ac->art_dev.dv_xname));
! 355: break;
! 356: /*
! 357: * case FAS_BSLIP:
! 358: * case FAS_CRC_BSLIP:
! 359: * case FAS_CAS:
! 360: * case FAS_CAS_BSLIP:
! 361: * case FAS_CRC_CAS:
! 362: * case FAS_CRC_CAS_BSLIP:
! 363: * case FT:
! 364: * case ESF_NOCRC:
! 365: * case SF_JYEL:
! 366: * case SF_T1DM:
! 367: * case SLC_FSLOF:
! 368: * case SLC:
! 369: * case ESF_xx (MimicCRC, ForceCRC?)
! 370: *
! 371: * are not yet implemented.
! 372: * If you need one of them please contact us.
! 373: */
! 374: default:
! 375: return (-1);
! 376: }
! 377: return (0);
! 378: }
! 379:
! 380: void
! 381: bt8370_set_sbi_clock_mode(struct art_softc *ac, enum art_sbi_type mode,
! 382: u_int linemode, int channels)
! 383: {
! 384: u_int8_t cmux, jatcr;
! 385:
! 386: /*
! 387: * mode is either master or slave.
! 388: * linemode is either T1 (1544) or E1 (2048) external or internal.
! 389: */
! 390: switch (mode) {
! 391: case ART_SBI_MASTER:
! 392: ACCOOM_PRINTF(1, ("%s: set to MASTER\n",
! 393: ac->art_dev.dv_xname));
! 394: /*
! 395: * ONESEC pulse output,
! 396: * RDL/TDL/INDY ignored,
! 397: * RFSYNC Receive Frame Sync output,
! 398: * RMSYNC Reveice MultiFrame Sync output,
! 399: * TFYNC Transmit Frame Sync output,
! 400: * TMSYNC Transmit MultiFrame Sync output.
! 401: */
! 402: ebus_write(&ac->art_ebus, Bt8370_PIO, PIO_ONESEC_IO |
! 403: PIO_TDL_IO | PIO_RFSYNC_IO | PIO_RMSYNC_IO |
! 404: PIO_TFSYNC_IO | PIO_TMSYNC_IO);
! 405: /*
! 406: * TDL/RDL/INDY/TCKO three-stated.
! 407: * CLADO enabled, drives SBI bus RCLK, TCLK and
! 408: * is connected to own TSBCKI and TSBCKI on slave.
! 409: * RCKO enabled, is connected to TCKI on slave.
! 410: */
! 411: ebus_write(&ac->art_ebus, Bt8370_POE, POE_TDL_OE |
! 412: POE_RDL_OE | POE_INDY_OE | POE_TCKO_OE);
! 413: /*
! 414: * We are the SBI bus master and take clock from our own
! 415: * CLADO. The TCKI source depends on line or internal
! 416: * clocking.
! 417: */
! 418: cmux = CMUX_RSBCKI_CLADO | CMUX_TSBCKI_CLADO |
! 419: CMUX_CLADI_CLADI;
! 420: break;
! 421: case ART_SBI_SLAVE:
! 422: ACCOOM_PRINTF(1, ("%s: set to SLAVE\n",
! 423: ac->art_dev.dv_xname));
! 424: /*
! 425: * ONESEC pulse input,
! 426: * RDL/TDL/INDY ignored,
! 427: * RFSYNC Receive Frame Sync input,
! 428: * RMSYNC Reveice MultiFrame Sync input,
! 429: * TFYNC Transmit Frame Sync input,
! 430: * TMSYNC Transmit MultiFrame Sync input.
! 431: */
! 432: ebus_write(&ac->art_ebus, Bt8370_PIO, PIO_TDL_IO);
! 433: /*
! 434: * TDL/RDL/INDY/TCKO three-stated.
! 435: * CLADO enabled, is connected to own ACKI and
! 436: * RSBCKI, ACKI on master.
! 437: * RCKO enabled, is connected to TCKI on master.
! 438: */
! 439: ebus_write(&ac->art_ebus, Bt8370_POE, POE_TDL_OE |
! 440: POE_RDL_OE | POE_INDY_OE | POE_TCKO_OE);
! 441: /*
! 442: * We are the SBI bus slave and take clock from TSBCKI.
! 443: * The TCKI source depends on line or internal clocking.
! 444: */
! 445: cmux = CMUX_RSBCKI_TSBCKI | CMUX_TSBCKI_TSBCKI |
! 446: CMUX_CLADI_CLADI;
! 447: break;
! 448: case ART_SBI_SINGLE:
! 449: ACCOOM_PRINTF(1, ("%s: set to SINGLE\n",
! 450: ac->art_dev.dv_xname));
! 451: /*
! 452: * ONESEC pulse output,
! 453: * RDL/TDL/INDY ignored,
! 454: * RFSYNC Receive Frame Sync output,
! 455: * RMSYNC Reveice MultiFrame Sync output,
! 456: * TFSYNC Transmit Frame Sync output,
! 457: * TMSYNC Transmit MultiFrame Sync output.
! 458: */
! 459: ebus_write(&ac->art_ebus, Bt8370_PIO, PIO_ONESEC_IO |
! 460: PIO_TDL_IO | PIO_RFSYNC_IO | PIO_RMSYNC_IO |
! 461: PIO_TFSYNC_IO | PIO_TMSYNC_IO);
! 462: /*
! 463: * TDL/RDL/INDY/TCKO three-stated, CLADO/RCKO enabled.
! 464: */
! 465: ebus_write(&ac->art_ebus, Bt8370_POE, POE_TDL_OE |
! 466: POE_RDL_OE | POE_INDY_OE | POE_RCKO_OE);
! 467: /*
! 468: * We are the SBI bus master and take clock from our own
! 469: * CLADO. The TCKI source is always CLADO (jitter attenuated
! 470: * if receive clock).
! 471: */
! 472: cmux = CMUX_RSBCKI_CLADO | CMUX_TSBCKI_CLADO |
! 473: CMUX_CLADI_RCKO;
! 474: break;
! 475: }
! 476:
! 477: /* Transmit clock from where? */
! 478: switch (linemode) {
! 479: case IFM_TDM_MASTER:
! 480: ACCOOM_PRINTF(1, ("%s: clock MASTER\n",
! 481: ac->art_dev.dv_xname));
! 482: if (mode == ART_SBI_MASTER)
! 483: cmux |= CMUX_TCKI_RSBCKI;
! 484: else
! 485: cmux |= CMUX_TCKI_CLADO;
! 486: jatcr = JAT_CR_JFREE;
! 487: break;
! 488: /* case ART_CLOCK_EXTREF: */
! 489: default:
! 490: ACCOOM_PRINTF(1, ("%s: clock LINE\n",
! 491: ac->art_dev.dv_xname));
! 492: cmux |= CMUX_TCKI_RCKO;
! 493: jatcr = JAT_CR_JEN | JAT_CR_JDIR_RX | JAT_CR_JSIZE32;
! 494: break;
! 495: }
! 496:
! 497: ebus_write(&ac->art_ebus, Bt8370_CMUX, cmux);
! 498: ebus_write(&ac->art_ebus, Bt8370_JAT_CR, jatcr);
! 499:
! 500: /* Set up the SBI (System Bus Interface) and clock source. */
! 501: switch (mode) {
! 502: case ART_SBI_MASTER:
! 503: ebus_write(&ac->art_ebus, Bt8370_CSEL, CSEL_VSEL_4096 |
! 504: CSEL_OSEL_4096);
! 505: bt8370_set_bus_mode(ac, SBI_MODE_4096_A, channels);
! 506: /* no need to set musycc port mode */
! 507: break;
! 508: case ART_SBI_SLAVE:
! 509: /*
! 510: * On the slave the CLADO depends on the line type
! 511: * of the master.
! 512: */
! 513: bt8370_set_bus_mode(ac, SBI_MODE_4096_B, channels);
! 514: /* no need to set musycc port mode */
! 515: break;
! 516: case ART_SBI_SINGLE:
! 517: if (channels == 25) {
! 518: ACCOOM_PRINTF(1, ("%s: SINGLE T1\n",
! 519: ac->art_dev.dv_xname));
! 520: ebus_write(&ac->art_ebus, Bt8370_CSEL, CSEL_VSEL_1544 |
! 521: CSEL_OSEL_1544);
! 522: bt8370_set_bus_mode(ac, SBI_MODE_1544, channels);
! 523: musycc_set_port(ac->art_channel->cc_group,
! 524: MUSYCC_PORT_MODE_T1);
! 525: } else {
! 526: ACCOOM_PRINTF(1, ("%s: SINGLE E1\n",
! 527: ac->art_dev.dv_xname));
! 528: ebus_write(&ac->art_ebus, Bt8370_CSEL, CSEL_VSEL_2048 |
! 529: CSEL_OSEL_2048);
! 530: bt8370_set_bus_mode(ac, SBI_MODE_2048, channels);
! 531: musycc_set_port(ac->art_channel->cc_group,
! 532: MUSYCC_PORT_MODE_E1);
! 533: }
! 534: break;
! 535: }
! 536: ebus_write(&ac->art_ebus, Bt8370_CLAD_CR, CLAD_CR_LFGAIN);
! 537: }
! 538:
! 539: void
! 540: bt8370_set_bus_mode(struct art_softc *ac, enum art_sbi_mode mode, int nchannels)
! 541: {
! 542: bus_size_t channel;
! 543:
! 544: /*
! 545: * Be aware that on the CN847x 'TSYNC_EDGE' has to be set to
! 546: * 'raising edge' in the port config for this to work correctly.
! 547: * All others (including RSYNC) are on 'falling edge'.
! 548: */
! 549: ebus_write(&ac->art_ebus, Bt8370_RSB_CR, RSB_CR_BUS_RSB |
! 550: RSB_CR_SIG_OFF | RSB_CR_RPCM_NEG | RSB_CR_RSYN_NEG |
! 551: RSB_CR_RSB_CTR | TSB_CR_TSB_NORMAL);
! 552: ebus_write(&ac->art_ebus, Bt8370_RSYNC_BIT, 0x00);
! 553: ebus_write(&ac->art_ebus, Bt8370_RSYNC_TS, 0x00);
! 554: ebus_write(&ac->art_ebus, Bt8370_TSB_CR, TSB_CR_BUS_TSB |
! 555: TSB_CR_TPCM_NEG | TSB_CR_TSYN_NEG | TSB_CR_TSB_CTR |
! 556: TSB_CR_TSB_NORMAL);
! 557: ebus_write(&ac->art_ebus, Bt8370_TSYNC_BIT, 0x00);
! 558: ebus_write(&ac->art_ebus, Bt8370_TSYNC_TS, 0x00);
! 559: ebus_write(&ac->art_ebus, Bt8370_RSIG_CR, 0x00);
! 560: ebus_write(&ac->art_ebus, Bt8370_RSYNC_FRM, 0x00);
! 561:
! 562: /* Mode dependent */
! 563: switch (mode) {
! 564: case SBI_MODE_1536:
! 565: ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE |
! 566: SBI_CR_1536);
! 567: break;
! 568: case SBI_MODE_1544:
! 569: ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE |
! 570: SBI_CR_1544);
! 571: break;
! 572: case SBI_MODE_2048:
! 573: ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE |
! 574: SBI_CR_2048);
! 575: break;
! 576: case SBI_MODE_4096_A:
! 577: ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE |
! 578: SBI_CR_4096_A);
! 579: break;
! 580: case SBI_MODE_4096_B:
! 581: ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE |
! 582: SBI_CR_4096_B);
! 583: break;
! 584: case SBI_MODE_8192_A:
! 585: ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE |
! 586: SBI_CR_8192_A);
! 587: break;
! 588: case SBI_MODE_8192_B:
! 589: ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE |
! 590: SBI_CR_8192_B);
! 591: break;
! 592: case SBI_MODE_8192_C:
! 593: ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE |
! 594: SBI_CR_8192_C);
! 595: break;
! 596: case SBI_MODE_8192_D:
! 597: ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE |
! 598: SBI_CR_8192_D);
! 599: break;
! 600: }
! 601:
! 602: /* Initialize and reset all channels */
! 603: for (channel = 0; channel < 32; channel++) {
! 604: ebus_write(&ac->art_ebus, Bt8370_SBCn + channel, 0x00);
! 605: ebus_write(&ac->art_ebus, Bt8370_TPCn + channel, 0x00);
! 606: ebus_write(&ac->art_ebus, Bt8370_TSIGn + channel, 0x00);
! 607: ebus_write(&ac->art_ebus, Bt8370_TSLIP_LOn + channel, 0x7e);
! 608: ebus_write(&ac->art_ebus, Bt8370_RSLIP_LOn + channel, 0x7e);
! 609: ebus_write(&ac->art_ebus, Bt8370_RPCn + channel, 0x00);
! 610: }
! 611:
! 612: /* Configure used channels */
! 613: for (channel = Bt8370_SBCn; channel < Bt8370_SBCn +
! 614: nchannels; channel++) {
! 615: ebus_write(&ac->art_ebus, channel, SBCn_RINDO |
! 616: SBCn_TINDO | SBCn_ASSIGN);
! 617: /* In T1 mode timeslot 0 must not be used. */
! 618: if (nchannels == 25 && channel == Bt8370_SBCn)
! 619: ebus_write(&ac->art_ebus, channel, 0x00);
! 620: }
! 621: for (channel = Bt8370_TPCn; channel < Bt8370_TPCn +
! 622: nchannels; channel++) {
! 623: ebus_write(&ac->art_ebus, channel, TPCn_CLEAR);
! 624: }
! 625: for (channel = Bt8370_RPCn; channel < Bt8370_RPCn +
! 626: nchannels; channel++) {
! 627: ebus_write(&ac->art_ebus, channel, RPCn_CLEAR);
! 628: }
! 629: }
! 630:
! 631: void
! 632: bt8370_set_line_buildout(struct art_softc *ac, int mode)
! 633: {
! 634: /*
! 635: * LIU Stuff: Send and Reveive side
! 636: * T1: 0-133, 133-266, 266-399, 399-533, 533-655,
! 637: * Long-Haul FCC Part 68.
! 638: * E1: ITU-T G.703 120 Ohm Twisted Pair.
! 639: */
! 640:
! 641: ebus_write(&ac->art_ebus, Bt8370_RLIU_CR, RLIU_CR_FRZ_SHORT |
! 642: RLIU_CR_AGC2048 | RLIU_CR_LONG_EYE);
! 643:
! 644: switch (mode) {
! 645: case FRAMER_LIU_T1_133:
! 646: /* Short haul */
! 647: ebus_write(&ac->art_ebus, Bt8370_VGA_MAX, 0x1F);
! 648: /* Force EQ off */
! 649: ebus_write(&ac->art_ebus, Bt8370_PRE_EQ, 0xA6);
! 650:
! 651: ebus_write(&ac->art_ebus, Bt8370_TLIU_CR, TLIU_CR_100);
! 652: break;
! 653: #if 0
! 654: case FRAMER_LIU_T1_266:
! 655: case FRAMER_LIU_T1_399:
! 656: case FRAMER_LIU_T1_533:
! 657: case FRAMER_LIU_T1_655:
! 658: case FRAMER_LIU_T1_LH68:
! 659: #endif
! 660: case FRAMER_LIU_E1_120:
! 661: /* Short haul */
! 662: ebus_write(&ac->art_ebus, Bt8370_VGA_MAX, 0x1F);
! 663: /* Force EQ off */
! 664: ebus_write(&ac->art_ebus, Bt8370_PRE_EQ, 0xA6);
! 665:
! 666: ebus_write(&ac->art_ebus, Bt8370_TLIU_CR, TLIU_CR_120);
! 667: break;
! 668: }
! 669:
! 670: /*
! 671: * Run this last. The RLIU reset causes the values written above
! 672: * to be activated.
! 673: */
! 674: ebus_write(&ac->art_ebus, Bt8370_LIU_CR, LIU_CR_MAGIC |
! 675: LIU_CR_SQUELCH | LIU_CR_RST_LIU);
! 676: }
! 677:
! 678: void
! 679: bt8370_set_loopback_mode(struct art_softc *ac, enum art_loopback mode)
! 680: {
! 681: switch (mode) {
! 682: case ART_RLOOP_PAYLOAD: /* Remote digital payload loopback */
! 683: ebus_write(&ac->art_ebus, Bt8370_LOOP, LOOP_PLOOP);
! 684: break;
! 685: case ART_RLOOP_LINE: /* Remote analog line signal loopback */
! 686: ebus_write(&ac->art_ebus, Bt8370_LOOP, LOOP_LLOOP);
! 687: break;
! 688: case ART_LLOOP_PAYLOAD: /* Local digital payload loopback */
! 689: ebus_write(&ac->art_ebus, Bt8370_LOOP, LOOP_FLOOP);
! 690: break;
! 691: case ART_LLOOP_LINE: /* Local analog line signal loopback */
! 692: ebus_write(&ac->art_ebus, Bt8370_LOOP, LOOP_ALOOP);
! 693: break;
! 694: case ART_NOLOOP: /* Disable all loopbacks */
! 695: ebus_write(&ac->art_ebus, Bt8370_LOOP, 0x00);
! 696: break;
! 697: }
! 698: }
! 699:
! 700: void
! 701: bt8370_set_bop_mode(struct art_softc *ac, int mode)
! 702: {
! 703: /* disabled or ESF mode */
! 704: switch (mode) {
! 705: case ART_BOP_ESF:
! 706: ebus_write(&ac->art_ebus, Bt8370_BOP, 0x9A);
! 707: break;
! 708: default:
! 709: ebus_write(&ac->art_ebus, Bt8370_BOP, 0x00);
! 710: break;
! 711: }
! 712: }
! 713:
! 714: void
! 715: bt8370_set_dl_1_mode(struct art_softc *ac, int mode)
! 716: {
! 717: /*
! 718: * We don't support the builtin HDLC controllers,
! 719: * however some DL1 registers are used for the BOP
! 720: * in ESF mode.
! 721: */
! 722: switch (mode) {
! 723: case ART_DL1_BOP:
! 724: ebus_write(&ac->art_ebus, Bt8370_DL1_TS, 0x40);
! 725: ebus_write(&ac->art_ebus, Bt8370_DL1_CTL, 0x03);
! 726: ebus_write(&ac->art_ebus, Bt8370_RDL1_FFC, 0x0A);
! 727: ebus_write(&ac->art_ebus, Bt8370_PRM1, 0x80);
! 728: ebus_write(&ac->art_ebus, Bt8370_TDL1_FEC, 0x0A);
! 729: break;
! 730: default:
! 731: ebus_write(&ac->art_ebus, Bt8370_RDL1_FFC, 0x0A);
! 732: ebus_write(&ac->art_ebus, Bt8370_TDL1, 0x00);
! 733: break;
! 734: }
! 735: }
! 736:
! 737: void
! 738: bt8370_set_dl_2_mode(struct art_softc *ac, int mode)
! 739: {
! 740: /* We don't support the builtin HDLC controllers. */
! 741: ebus_write(&ac->art_ebus, Bt8370_RDL2_FFC, 0x0A);
! 742: ebus_write(&ac->art_ebus, Bt8370_TDL2, 0x00);
! 743: }
! 744:
! 745: void
! 746: bt8370_intr_enable(struct art_softc *ac, int intr)
! 747: {
! 748: switch (intr) {
! 749: default:
! 750: /* Disable all interrupts */
! 751: ebus_write(&ac->art_ebus, Bt8370_IER7, 0x00);
! 752: ebus_write(&ac->art_ebus, Bt8370_IER6, 0x00);
! 753: ebus_write(&ac->art_ebus, Bt8370_IER5, 0x00);
! 754: ebus_write(&ac->art_ebus, Bt8370_IER4, 0x00);
! 755: ebus_write(&ac->art_ebus, Bt8370_IER3, 0x00);
! 756: ebus_write(&ac->art_ebus, Bt8370_IER2, 0x00);
! 757: ebus_write(&ac->art_ebus, Bt8370_IER1, 0x00);
! 758: ebus_write(&ac->art_ebus, Bt8370_IER0, 0x00);
! 759: break;
! 760: }
! 761: return;
! 762: }
! 763:
! 764: void
! 765: bt8370_intr(struct art_softc *ac)
! 766: {
! 767: u_int8_t irr, alrm;
! 768:
! 769: /* IRR tells us which interrupt class fired. */
! 770: irr = ebus_read(&ac->art_ebus, Bt8370_IRR);
! 771: /* If it wasn't us don't waste time. */
! 772: if (irr == 0x00)
! 773: return;
! 774:
! 775: /* Reding the interrupt service registers clears them. */
! 776: alrm = ebus_read(&ac->art_ebus, Bt8370_ISR7);
! 777: alrm = ebus_read(&ac->art_ebus, Bt8370_ISR6);
! 778: alrm = ebus_read(&ac->art_ebus, Bt8370_ISR5);
! 779: alrm = ebus_read(&ac->art_ebus, Bt8370_ISR4);
! 780: alrm = ebus_read(&ac->art_ebus, Bt8370_ISR3);
! 781: alrm = ebus_read(&ac->art_ebus, Bt8370_ISR2);
! 782: alrm = ebus_read(&ac->art_ebus, Bt8370_ISR1);
! 783: alrm = ebus_read(&ac->art_ebus, Bt8370_ISR0);
! 784:
! 785: /* IRR should be zero now or something went wrong. */
! 786: irr = ebus_read(&ac->art_ebus, Bt8370_IRR);
! 787: if (irr != 0x00)
! 788: ACCOOM_PRINTF(0, ("%s: Interrupts did not clear properly\n",
! 789: ac->art_dev.dv_xname));
! 790: return;
! 791: }
! 792:
! 793: int
! 794: bt8370_link_status(struct art_softc *ac)
! 795: {
! 796: u_int8_t rstat, alm1, alm2, alm3, alm1mask;
! 797: int status = 1;
! 798:
! 799: /*
! 800: * 1 everything fine
! 801: * 0 framing problems but link detected
! 802: * -1 no link detected
! 803: */
! 804:
! 805: alm1mask = ALM1_RYEL | ALM1_RAIS | ALM1_RALOS | ALM1_RLOF;
! 806: /*
! 807: * XXX don't check RYEL in T1 mode it toggles more or less
! 808: * regular.
! 809: */
! 810: if (IFM_SUBTYPE(ac->art_media) == IFM_TDM_T1)
! 811: alm1mask &= ~ALM1_RYEL;
! 812:
! 813: rstat = ebus_read(&ac->art_ebus, Bt8370_RSTAT);
! 814: alm1 = ebus_read(&ac->art_ebus, Bt8370_ALM1);
! 815: alm2 = ebus_read(&ac->art_ebus, Bt8370_ALM2);
! 816: alm3 = ebus_read(&ac->art_ebus, Bt8370_ALM3);
! 817:
! 818: if ((rstat & (RSTAT_EXZ | RSTAT_BPV)) ||
! 819: (alm1 & alm1mask) || (alm3 & (ALM3_SEF)))
! 820: status = 0;
! 821:
! 822: if ((alm1 & (ALM1_RLOS)) ||
! 823: (alm2 & (ALM2_TSHORT)))
! 824: status = -1;
! 825:
! 826: return (status);
! 827: }
! 828:
! 829: #ifdef ACCOOM_DEBUG
! 830: void
! 831: bt8370_print_status(struct art_softc *ac)
! 832: {
! 833: u_int8_t fstat, rstat, vga, alm1, alm2, alm3, sstat, loop;
! 834:
! 835: /* FSTAT Register. */
! 836: fstat = ebus_read(&ac->art_ebus, Bt8370_FSTAT);
! 837: printf("%s: Current FSTAT:\n", ac->art_dev.dv_xname);
! 838: if (fstat & FSTAT_ACTIVE) {
! 839: printf("\tOffline Framer active ");
! 840: if (fstat & FSTAT_RXTXN)
! 841: printf("in Receive direction\n");
! 842: else
! 843: printf("in Transmit direction\n");
! 844: if (fstat & FSTAT_INVALID)
! 845: printf("\tNo Candidate found\n");
! 846: if (fstat & FSTAT_FOUND)
! 847: printf("\tFrame Alignment found\n");
! 848: if (fstat & FSTAT_TIMEOUT)
! 849: printf("\tFramer Search timeout\n");
! 850: } else
! 851: printf("\tOffline inactive\n");
! 852:
! 853: /* RSTAT and VGA Register. */
! 854: rstat = ebus_read(&ac->art_ebus, Bt8370_RSTAT);
! 855: printf("%s: Current RSTAT:\n", ac->art_dev.dv_xname);
! 856: if (rstat & RSTAT_CPDERR)
! 857: printf("\tCLAD phase detector lost lock to CLADI reference\n");
! 858: if (rstat & RSTAT_ZCSUB)
! 859: printf("\tHDB3/B8ZS pattern detected\n");
! 860: if (rstat & RSTAT_EXZ)
! 861: printf("\tExcessive zeros detected\n");
! 862: if (rstat & RSTAT_BPV)
! 863: printf("\tBipolar violations\n");
! 864: if (rstat & RSTAT_EYEOPEN)
! 865: printf("\tReceived signal valid and RPLL locked\n");
! 866: else
! 867: printf("\tReceived signal invalid\n");
! 868: if (rstat & RSTAT_PRE_EQ)
! 869: printf("\tPre-Equalizer is ON\n");
! 870: else
! 871: printf("\tPre-Equalizer is OFF\n");
! 872: /* Need to write something to cause internal update. */
! 873: ebus_write(&ac->art_ebus, Bt8370_VGA, 0x00);
! 874: vga = ebus_read(&ac->art_ebus, Bt8370_VGA);
! 875: printf("\t%i dB Gain\n", vga);
! 876:
! 877: /* Alarm 1 Status. */
! 878: alm1 = ebus_read(&ac->art_ebus, Bt8370_ALM1);
! 879: printf("%s: Current ALM1:\n", ac->art_dev.dv_xname);
! 880: if (alm1 & ALM1_RMYEL)
! 881: printf("\tMultiframe Yellow Alarm [MYEL]\n");
! 882: if (alm1 & ALM1_RYEL)
! 883: printf("\tYellow Alarm [YEL]\n");
! 884: if (alm1 & ALM1_RAIS)
! 885: printf("\tRemote Alarm Indication [RAIS]\n");
! 886: if (alm1 & ALM1_RALOS)
! 887: printf("\tAnalog Loss of Signal or RCKI Loss of Clock [RALOS]\n");
! 888: if (alm1 & ALM1_RLOS)
! 889: printf("\tLoss of Signal [RLOS]\n");
! 890: if (alm1 & ALM1_RLOF)
! 891: printf("\tLoss of Frame Alignment [RLOF]\n");
! 892: if (alm1 & ALM1_SIGFRZ)
! 893: printf("\tSignalling Freeze\n");
! 894:
! 895: /* Alarm 2 Status. */
! 896: alm2 = ebus_read(&ac->art_ebus, Bt8370_ALM2);
! 897: printf("%s: Current ALM2:\n", ac->art_dev.dv_xname);
! 898: if (alm2 & ALM2_LOOPDN)
! 899: printf("\tLOOPDN code detected\n");
! 900: if (alm2 & ALM2_LOOPUP)
! 901: printf("\tLOOPUP code detected\n");
! 902: if (alm2 & ALM2_TSHORT)
! 903: printf("\tTransmitter short circuit\n");
! 904: if (alm2 & ALM2_TLOC)
! 905: printf("\tTransmit loss of clock (relative to ACKI)\n");
! 906: if (alm2 & ALM2_TLOF)
! 907: printf("\tTransmit loss of frame alignment (ignored)\n");
! 908:
! 909: /* Alarm 3 Status. */
! 910: alm3 = ebus_read(&ac->art_ebus, Bt8370_ALM3);
! 911: printf("%s: Current ALM3:\n", ac->art_dev.dv_xname);
! 912: if (alm3 & ALM3_RMAIS)
! 913: printf("\tRMAIS TS16 Alarm Indication Signal\n");
! 914: if (alm3 & ALM3_SEF)
! 915: printf("\tSeverely Errored Frame encountered\n");
! 916: if (alm3 & ALM3_SRED)
! 917: printf("\tLoss of CAS Alignment\n");
! 918: if (alm3 & ALM3_MRED)
! 919: printf("\tLoss of MFAS Alignment\n");
! 920: if (alm3 & ALM3_FRED)
! 921: printf("\tLoss of T1/FAS Alignment\n");
! 922: /* LOF omitted */
! 923:
! 924: /* Slip Buffer Status. */
! 925: sstat = ebus_read(&ac->art_ebus, Bt8370_SSTAT);
! 926: printf("%s: Current SSTAT:\n", ac->art_dev.dv_xname);
! 927: if (sstat & SSTAT_TFSLIP) {
! 928: if (sstat & SSTAT_TUSLIP)
! 929: printf("\tControlled Transmit Slip, ");
! 930: else
! 931: printf("\tUncontrolled Transmit Slip, ");
! 932: if (sstat & SSTAT_TSDIR)
! 933: printf("repeated one frame\n");
! 934: else
! 935: printf("deleted one frame\n");
! 936: } else if (sstat & SSTAT_RFSLIP) {
! 937: if (sstat & SSTAT_RUSLIP)
! 938: printf("\tControlled Receive Slip, ");
! 939: else
! 940: printf("\tUncontrolled Receive Slip, ");
! 941: if (sstat & SSTAT_RSDIR)
! 942: printf("repeated one frame\n");
! 943: else
! 944: printf("deleted one frame\n");
! 945: }
! 946:
! 947: /* Loopback Status. */
! 948: loop = ebus_read(&ac->art_ebus, Bt8370_LOOP);
! 949: printf("%s: Current LOOP:\n", ac->art_dev.dv_xname);
! 950: if (loop & LOOP_PLOOP)
! 951: printf("\tRemote Payload Loopback\n");
! 952: if (loop & LOOP_LLOOP)
! 953: printf("\tRemote Line Loopback\n");
! 954: if (loop & LOOP_FLOOP)
! 955: printf("\tLocal Payload Loopback\n");
! 956: if (loop & LOOP_ALOOP)
! 957: printf("\tLocal Line Loopback\n");
! 958: if (loop & 0x00)
! 959: printf("\tNo active Loopbacks\n");
! 960: }
! 961:
! 962: void
! 963: bt8370_print_counters(struct art_softc *ac)
! 964: {
! 965: u_int16_t counters[5];
! 966: u_int16_t hi, lo;
! 967: int i;
! 968:
! 969: for (i = 0; i < 5; i++) {
! 970: lo = ebus_read(&ac->art_ebus, Bt8370_FERR_LSB + i);
! 971: hi = ebus_read(&ac->art_ebus, Bt8370_FERR_LSB + i + 1);
! 972:
! 973: counters[i] = lo | (hi << 8);
! 974: }
! 975:
! 976: printf("%s: %hu framing bit errors, %hu CRC errors, ",
! 977: ac->art_dev.dv_xname, counters[0], counters[1]);
! 978: printf("%hu line code violations\n", counters[2]);
! 979: printf("%s: %hu Far End Errors %hu PRBS bit errors\n",
! 980: ac->art_dev.dv_xname, counters[3], counters[4]);
! 981: }
! 982: void
! 983: bt8370_dump_registers(struct art_softc *ac)
! 984: {
! 985: int i;
! 986:
! 987: printf("%s: dummping registers", ac->art_dev.dv_xname);
! 988: for (i = 0; i < 0x200; i++) {
! 989: if (i % 16 == 0)
! 990: printf("\n%03x:", i);
! 991: printf("%s%02x%s", i % 2 ? "" : " ",
! 992: ebus_read(&ac->art_ebus, i),
! 993: i % 8 == 7 ? " " : "");
! 994: }
! 995: printf("\n");
! 996: }
! 997:
! 998: #endif
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