Annotation of sys/dev/pci/autrireg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: autrireg.h,v 1.2 2002/11/29 04:59:59 fgsch Exp $ */
2:
3: /*
4: * Copyright (c) 2001 SOMEYA Yoshihiko and KUROSAWA Takahiro.
5: * All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: *
16: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26: */
27:
28: /*
29: * Trident 4DWAVE registers
30: */
31:
32: #ifndef _DEV_PCI_AUTRIREG_H_
33: #define _DEV_PCI_AUTRIREG_H_
34:
35:
36: #define AUTRI_DEVICE_ID_4DWAVE_DX \
37: ((PCI_PRODUCT_TRIDENT_4DWAVE_DX << 16) | PCI_VENDOR_TRIDENT)
38: #define AUTRI_DEVICE_ID_4DWAVE_NX \
39: ((PCI_PRODUCT_TRIDENT_4DWAVE_NX << 16) | PCI_VENDOR_TRIDENT)
40: #define AUTRI_DEVICE_ID_SIS_7018 \
41: ((PCI_PRODUCT_SIS_7018 << 16) | PCI_VENDOR_SIS)
42: #define AUTRI_DEVICE_ID_ALI_M5451 \
43: ((PCI_PRODUCT_ALI_M5451 << 16) | PCI_VENDOR_ALI)
44:
45: /*
46: * PCI Config Registers
47: */
48: #define AUTRI_PCI_MEMORY_BASE 0x14
49: #define AUTRI_PCI_DDMA_CFG 0x40
50: #define AUTRI_PCI_LEGACY_IOBASE 0x44
51:
52: /*
53: * AC'97 Registers
54: */
55: #define AUTRI_DX_ACR0 0x40
56: # define AUTRI_DX_ACR0_CMD_WRITE 0x00008000
57: # define AUTRI_DX_ACR0_BUSY_WRITE 0x00008000
58: #define AUTRI_DX_ACR1 0x44
59: # define AUTRI_DX_ACR1_CMD_READ 0x00008000
60: # define AUTRI_DX_ACR1_BUSY_READ 0x00008000
61: #define AUTRI_DX_ACR2 0x48
62: # define AUTRI_DX_ACR2_CODEC_READY 0x00000010
63:
64: #define AUTRI_NX_ACR0 0x40
65: # define AUTRI_NX_ACR0_PSB_CAPTURE 0x00000200
66: # define AUTRI_NX_ACR0_CODEC_READY 0x00000008
67: #define AUTRI_NX_ACR1 0x44
68: # define AUTRI_NX_ACR1_CMD_WRITE 0x00000800
69: # define AUTRI_NX_ACR1_BUSY_WRITE 0x00000800
70: #define AUTRI_NX_ACR2 0x48
71: # define AUTRI_NX_ACR2_CMD_READ 0x00000800
72: # define AUTRI_NX_ACR2_BUSY_READ 0x00000800
73: # define AUTRI_NX_ACR2_RECV_WAIT 0x00000400
74: #define AUTRI_NX_ACR3 0x4c
75:
76: #define AUTRI_SIS_ACWR 0x40
77: # define AUTRI_SIS_ACWR_CMD_WRITE 0x00008000
78: # define AUTRI_SIS_ACWR_BUSY_WRITE 0x00008000
79: # define AUTRI_SIS_ACWR_AUDIO_BUSY 0x00004000
80: #define AUTRI_SIS_ACRD 0x44
81: # define AUTRI_SIS_ACRD_CMD_READ 0x00008000
82: # define AUTRI_SIS_ACRD_BUSY_READ 0x00008000
83: # define AUTRI_SIS_ACRD_AUDIO_BUSY 0x00004000
84: #define AUTRI_SIS_SCTRL 0x48
85: # define AUTRI_SIS_SCTRL_CODEC_READY 0x01000000
86: #define AUTRI_SIS_ACGPIO 0x4c
87:
88: #define AUTRI_ALI_ACWR 0x40
89: # define AUTRI_ALI_ACWR_CMD_WRITE 0x00008000
90: # define AUTRI_ALI_ACWR_BUSY_WRITE 0x00008000
91: #define AUTRI_ALI_ACRD 0x44
92: # define AUTRI_ALI_ACRD_CMD_READ 0x00008000
93: # define AUTRI_ALI_ACRD_BUSY_READ 0x00008000
94: #define AUTRI_ALI_SCTRL 0x48
95: # define AUTRI_ALI_SCTRL_CODEC_READY 0x01000000
96: #define AUTRI_ALI_ACGPIO 0x4c
97: /*
98: # define AUTRI_ALI_AC97_BUSY_READ 0x00008000
99: # define AUTRI_ALI_AC97_BUSY_WRITE 0x00008000
100: # define AUTRI_ALI_AC97_CMD_WRITE 0x00008000
101: */
102:
103: /*
104: * MPU-401 UART
105: */
106: #define AUTRI_MPUR0 0x20
107: #define AUTRI_MPUR1 0x21
108: # define AUTRI_MIDIOUT_READY 0x40
109: #define AUTRI_MPUR2 0x22
110: # define AUTRI_MIDIOUT_CONNECT 0x10
111: # define AUTRI_MIDIIN_ENABLE_INTR 0x08
112:
113: #define MIDI_BUSY_WAIT 100
114: #define MIDI_BUSY_DELAY 100
115:
116: /*
117: * Channel Registers
118: */
119: #define AUTRI_START_A 0x80
120: #define AUTRI_STOP_A 0x84
121: #define AUTRI_DLY_A 0x88
122: #define AUTRI_SIGN_CSO_A 0x8c
123: #define AUTRI_CSPF_A 0x90
124: #define AUTRI_CEBC_A 0x94
125: #define AUTRI_AIN_A 0x98
126: #define AUTRI_EINT_A 0x9c
127: #define AUTRI_LFO_GC_CIR 0xa0
128: # define ENDLP_IE 0x00001000
129: # define MIDLP_IE 0x00002000
130: # define BANK_B_EN 0x00010000
131: #define AUTRI_AINTEN_A 0xa4
132: #define AUTRI_MUSICVOL_WAVEVOL 0xa8
133: #define AUTRI_MISCINT 0xb0
134: # define ST_TARGET_REACHED 0x00008000
135: # define MIXER_OVERFLOW 0x00000800
136: # define MIXER_UNDERFLOW 0x00000800
137: # define ADDRESS_IRQ 0x00000020
138: # define MPU401_IRQ 0x00000008
139: #define AUTRI_START_B 0xb4
140: #define AUTRI_STOP_B 0xb8
141: #define AUTRI_CSPF_B 0xbc
142: #define AUTRI_AIN_B 0xd8
143: #define AUTRI_AINTEN_B 0xdc
144:
145: /*
146: * Indexed Channel Registers
147: */
148: #define AUTRI_ARAM_CR 0xe0
149: # define AUTRI_ATTR_PCMREC_SIS 0x88000000
150: # define AUTRI_ATTR_ENASRC_SIS 0x00800000
151: # define AUTRI_CTRL_WAVEVOL 0x80000000
152: # define AUTRI_CTRL_MUTE 0x3fff0000
153: # define AUTRI_CTRL_MUTE_SIS 0x3f000fff
154: # define AUTRI_CTRL_16BIT 0x00008000
155: # define AUTRI_CTRL_STEREO 0x00004000
156: # define AUTRI_CTRL_SIGNED 0x00002000
157: # define AUTRI_CTRL_LOOPMODE 0x00001000
158: #define AUTRI_EBUF1 0xf4
159: #define AUTRI_EBUF2 0xf8
160: # define AUTRI_EMOD_STILL 0x30000000
161:
162: /*
163: * Others
164: */
165: #define AUTRI_NX_RCI3 0x73
166: # define AUTRI_NX_RCI3_ENABLE 0x80
167:
168: #define AUTRI_ALI_GCONTROL 0xd4
169: # define AUTRI_ALI_GCONTROL_PCM_IN 0x80000000
170:
171:
172: #endif /* _DEV_PCI_AUTRIREG_H_ */
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