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Annotation of sys/dev/mii/mtdphyreg.h, Revision 1.1

1.1     ! nbrk        1: /*     $OpenBSD: mtdphyreg.h,v 1.3 2003/06/02 19:08:58 jason Exp $     */
        !             2:
        !             3: /*
        !             4:  * Copyright (c) 1998 Jason L. Wright (jason@thought.net)
        !             5:  * All rights reserved.
        !             6:  *
        !             7:  * Redistribution and use in source and binary forms, with or without
        !             8:  * modification, are permitted provided that the following conditions
        !             9:  * are met:
        !            10:  * 1. Redistributions of source code must retain the above copyright
        !            11:  *    notice, this list of conditions and the following disclaimer.
        !            12:  * 2. Redistributions in binary form must reproduce the above copyright
        !            13:  *    notice, this list of conditions and the following disclaimer in the
        !            14:  *    documentation and/or other materials provided with the distribution.
        !            15:  *
        !            16:  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
        !            17:  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
        !            18:  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
        !            19:  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
        !            20:  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
        !            21:  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
        !            22:  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
        !            23:  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
        !            24:  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
        !            25:  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
        !            26:  * POSSIBILITY OF SUCH DAMAGE.
        !            27:  */
        !            28:
        !            29: #ifndef _DEV_MII_MTDPHYREG_H_
        !            30: #define        _DEV_MII_MTDPHYREG_H_
        !            31:
        !            32: /*
        !            33:  * Myson MTD972 registers.
        !            34:  */
        !            35:
        !            36: #define        MII_MTDPHY_ANNPTR       0x07    /* Auto-Neg Next Page Tx Register */
        !            37: #define        ANNPTR_NEXT             0x8000  /* Next Page */
        !            38: #define        ANNPTR_ACK              0x4000  /* Acknowledge */
        !            39: #define        ANNPTR_MPG              0x2000  /* Message Page */
        !            40: #define        ANNPTR_ACK2             0x1000  /* Acknowledge 2 */
        !            41: #define        ANNPTR_TOGGLE           0x0800  /* Toggle */
        !            42: #define        ANNPTR_DAT              0x0400  /* Data */
        !            43:
        !            44: #define        MII_MTDPHY_DCR          0x12    /* Disconnect Register */
        !            45:        /* count of the number of partitions */
        !            46:
        !            47: #define        MII_MTDPHY_FCSCR        0x13    /* False Carrier Sense Counter Reg */
        !            48:        /* count of the number of false carrier senses */
        !            49:
        !            50: #define        MII_MTDPHY_RECR         0x15    /* Receive Error Condition Register */
        !            51:        /* count of the number of receive errors */
        !            52:
        !            53: #define        MII_MTDPHY_RR           0x16    /* Revision Register */
        !            54:        /* revision of the MTD972 */
        !            55:
        !            56: #define        MII_MTDPHY_PCR          0x17    /* PHY Configuration Register */
        !            57: #define        PCR_NRZIEN              0x8000  /* NRZI Encode/Decode Enable */
        !            58: #define        PCR_TOCEL               0x4000  /* Descrambler Time Out Select */
        !            59: #define        PCR_TODIS               0x2000  /* Descrambler Time Out Disable */
        !            60: #define        PCR_RPTR                0x1000  /* Enable Repeater mode */
        !            61: #define        PCR_ENCSEL              0x0800  /* PMD ENCSEL pin control */
        !            62: #define        PCR_20MENB              0x0100  /* 20MHz output enable */
        !            63: #define        PCR_25MDIS              0x0080  /* 25MHz output disable */
        !            64: #define        PCR_FGLNKTX             0x0040  /* Force link status good */
        !            65: #define        PCR_FCONNT              0x0020  /* Bypass disconnect function */
        !            66: #define        PCR_TXOFF               0x0010  /* Turn off TX */
        !            67: #define        PCR_LEDTSL              0x0002  /* LED T display select */
        !            68: #define        PCR_LEDPSL              0x0001  /* LED P display select */
        !            69:
        !            70: #define        MII_MTDPHY_LBCR         0x18    /* Loopback and Bypass Control Reg */
        !            71: #define        LBCR_BP4B5B             0x4000  /* Bypass */
        !            72: #define        LBCR_BPSCRM             0x2000  /* Bypass */
        !            73: #define        LBCR_BPALGN             0x1000  /* Bypass symbol alignment */
        !            74: #define        LBCR_LBK10              0x0800  /* Loopback control for 10BT */
        !            75: #define        LBCR_LBK1               0x0200  /* Loopback control 1 for PMD */
        !            76: #define        LBCR_LBK0               0x0100  /* Loopback control 0 for PMD */
        !            77: #define        LBCR_FDCRS              0x0040  /* Full duplex CRS function */
        !            78: #define        LBCR_CERR               0x0010  /* Code Error */
        !            79: #define        LBCR_PERR               0x0008  /* Premature Error */
        !            80: #define        LBCR_LERR               0x0004  /* Link Error */
        !            81: #define        LBCR_FERR               0x0002  /* Frame Error */
        !            82:
        !            83: #define        MII_MTDPHY_PAR          0x19    /* PHY Address Register */
        !            84: #define        PAR_ANS                 0x0400  /* State of autonegotiation */
        !            85: #define        PAR_FEFE                0x0100  /* Far End Fault Enable */
        !            86: #define        PAR_DPLX                0x0080  /* Duplex status */
        !            87: #define        PAR_SPD                 0x0040  /* Speed status */
        !            88: #define        PAR_CONN                0x0020  /* Connection status */
        !            89: #define        PAR_PHYADDR_MASK        0x001f  /* PHY address mask */
        !            90:
        !            91: #define        MII_MTDPHY_10SR         0x1b    /* 10baseT Status Register */
        !            92: #define        TENSR_10BTSER           0x0200  /* Serial mode for 10BaseT interface */
        !            93: #define        TENSR_POLST             0x0001  /* Polarity state */
        !            94:
        !            95: #define        MII_MTDPHY_10CR         0x1c    /* 10baseT Control Register */
        !            96: #define        TENCR_LOE               0x0020  /* Link Pulse Ouput Enable */
        !            97: #define        TENCR_HBE               0x0010  /* HeartBeat Enable */
        !            98: #define        TENCR_UTPV              0x0008  /* TPOV=1, TPOI=0 */
        !            99: #define        TENCR_LSS               0x0004  /* Low Squelch Select */
        !           100: #define        TENCR_PENB              0x0002  /* Parity Enable */
        !           101: #define        TENCR_JEN               0x0001  /* Jabber Enable */
        !           102:
        !           103: #endif /* _DEV_MII_MTDPHYREG_H_ */