Annotation of sys/dev/mii/miidevs.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: miidevs.h,v 1.88 2006/11/28 18:20:03 brad Exp $ */
2:
3: /*
4: * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
5: *
6: * generated from:
7: * OpenBSD: miidevs,v 1.85 2006/11/28 18:19:49 brad Exp
8: */
9: /* $NetBSD: miidevs,v 1.3 1998/11/05 03:43:43 thorpej Exp $ */
10:
11: /*-
12: * Copyright (c) 1998 The NetBSD Foundation, Inc.
13: * All rights reserved.
14: *
15: * This code is derived from software contributed to The NetBSD Foundation
16: * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
17: * NASA Ames Research Center.
18: *
19: * Redistribution and use in source and binary forms, with or without
20: * modification, are permitted provided that the following conditions
21: * are met:
22: * 1. Redistributions of source code must retain the above copyright
23: * notice, this list of conditions and the following disclaimer.
24: * 2. Redistributions in binary form must reproduce the above copyright
25: * notice, this list of conditions and the following disclaimer in the
26: * documentation and/or other materials provided with the distribution.
27: * 3. All advertising materials mentioning features or use of this software
28: * must display the following acknowledgement:
29: * This product includes software developed by the NetBSD
30: * Foundation, Inc. and its contributors.
31: * 4. Neither the name of The NetBSD Foundation nor the names of its
32: * contributors may be used to endorse or promote products derived
33: * from this software without specific prior written permission.
34: *
35: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
36: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
37: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
38: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
39: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
40: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
41: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
42: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
43: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
44: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
45: * POSSIBILITY OF SUCH DAMAGE.
46: */
47:
48: /*
49: * List of known MII OUIs
50: */
51:
52: #define MII_OUI_VITESSE 0x0001c1 /* Vitesse */
53: #define MII_OUI_3COM 0x00105a /* 3com */
54: #define MII_OUI_LUCENT 0x00601d /* Lucent Technologies */
55: #define MII_OUI_ALTIMA 0x0010a9 /* Altima Communications */
56: #define MII_OUI_AMD 0x00001a /* Advanced Micro Devices */
57: #define MII_OUI_ASIX 0x000ec6 /* ASIX Electronics */
58: #define MII_OUI_BROADCOM 0x001018 /* Broadcom Corporation */
59: #define MII_OUI_CENIX 0x000749 /* CENiX Inc. */
60: #define MII_OUI_CICADA 0x0003f1 /* Cicada Semiconductor */
61: #define MII_OUI_ENABLESEMI 0x0010dd /* Enable Semiconductor */
62: #define MII_OUI_DAVICOM 0x00606e /* Davicom Semiconductor */
63: #define MII_OUI_MARVELL 0x005043 /* Marvell Semiconductor */
64: #define MII_OUI_ICPLUS 0x0090c3 /* IC Plus Corp. */
65: #define MII_OUI_ICS 0x00a0be /* Integrated Circuit Systems */
66: #define MII_OUI_INTEL 0x00aa00 /* Intel */
67: #define MII_OUI_JATO 0x00e083 /* Jato Technologies */
68: #define MII_OUI_LEVEL1 0x00207b /* Level 1 */
69: #define MII_OUI_MYSON 0x00c0b4 /* Myson Technology */
70: #define MII_OUI_NATSEMI 0x080017 /* National Semiconductor */
71: #define MII_OUI_PLESSEY 0x046b40 /* Plessey Semiconductor */
72: #define MII_OUI_PMCSIERRA 0x00e004 /* PMC-Sierra */
73: #define MII_OUI_QUALSEMI 0x006051 /* Quality Semiconductor */
74: #define MII_OUI_REALTEK 0x000020 /* Realtek Semiconductor */
75: #define MII_OUI_REALTEK2 0x00e04c /* Realtek Semiconductor */
76: #define MII_OUI_SEEQ 0x00a07d /* Seeq */
77: #define MII_OUI_SIS 0x00e006 /* Silicon Integrated Systems */
78: #define MII_OUI_SMSC 0x00800f /* Standard Microsystems */
79: #define MII_OUI_TI 0x080028 /* Texas Instruments */
80: #define MII_OUI_TOPIC 0x0090c3 /* Topic Semiconductor */
81: #define MII_OUI_TSC 0x00c039 /* TDK Semiconductor */
82: #define MII_OUI_VIA 0x004063 /* VIA Networking Technologies */
83: #define MII_OUI_XAQTI 0x00e0ae /* XaQti Corp. */
84:
85: /* in the 79c873, AMD uses another OUI (which matches Davicom!) */
86: #define MII_OUI_xxALTIMA 0x000895 /* Altima Communications */
87: #define MII_OUI_xxAMD 0x00606e /* Advanced Micro Devices */
88: #define MII_OUI_xxINTEL 0x00f800 /* Intel (alt) */
89: #define MII_OUI_xxCICADA 0x00c08f /* Cicada Semiconductor (alt) */
90:
91: /* some vendors have the bits swapped within bytes
92: (ie, ordered as on the wire) */
93: #define MII_OUI_xxBROADCOM 0x000818 /* Broadcom Corporation */
94: #define MII_OUI_xxICS 0x00057d /* Integrated Circuit Systems */
95: #define MII_OUI_xxSEEQ 0x0005be /* Seeq */
96: #define MII_OUI_xxSIS 0x000760 /* Silicon Integrated Systems */
97: #define MII_OUI_xxTI 0x100014 /* Texas Instruments */
98: #define MII_OUI_xxXAQTI 0x350700 /* XaQti Corp. */
99:
100: /* Level 1 is completely different - from right to left.
101: (Two bits get lost in the third OUI byte.) */
102: #define MII_OUI_xxLEVEL1 0x1e0400 /* Level 1 */
103: #define MII_OUI_xxLEVEL1a 0x0004de /* Level 1 */
104:
105: /* Don't know what's going on here. */
106: #define MII_OUI_xxDAVICOM 0x006040 /* Davicom Semiconductor */
107: #define MII_OUI_xxBROADCOM2 0x0050ef /* Broadcom Corporation */
108:
109: /* This is the OUI of the gigE PHY in the RealTek 8169S/8110S chips */
110: #define MII_OUI_xxREALTEK 0x000732 /* Realtek Semiconductor */
111:
112: /* Contrived vendor for dcphy */
113: #define MII_OUI_xxDEC 0x040440 /* Digital Clone */
114:
115: #define MII_OUI_xxMARVELL 0x000ac2 /* Marvell Semiconductor */
116:
117: /*
118: * List of known models. Grouped by oui.
119: */
120:
121: /* Advanced Micro Devices PHYs */
122: #define MII_MODEL_xxAMD_79C873 0x0000
123: #define MII_STR_xxAMD_79C873 "Am79C873 10/100 PHY"
124: #define MII_MODEL_AMD_79C873phy 0x0036
125: #define MII_STR_AMD_79C873phy "Am79C873 internal PHY"
126: #define MII_MODEL_AMD_79C875phy 0x0014
127: #define MII_STR_AMD_79C875phy "Am79C875 quad PHY"
128:
129: /* Altima Communications PHYs */
130: #define MII_MODEL_xxALTIMA_AC_UNKNOWN 0x0001
131: #define MII_STR_xxALTIMA_AC_UNKNOWN "AC_UNKNOWN 10/100 PHY"
132: #define MII_MODEL_xxALTIMA_AC101 0x0021
133: #define MII_STR_xxALTIMA_AC101 "AC101 10/100 PHY"
134: #define MII_MODEL_xxALTIMA_AC101L 0x0012
135: #define MII_STR_xxALTIMA_AC101L "AC101L 10/100 PHY"
136:
137: /* Broadcom Corp. PHYs */
138: #define MII_MODEL_xxBROADCOM_BCM5400 0x0004
139: #define MII_STR_xxBROADCOM_BCM5400 "BCM5400 1000baseT PHY"
140: #define MII_MODEL_xxBROADCOM_BCM5401 0x0005
141: #define MII_STR_xxBROADCOM_BCM5401 "BCM5401 10/100/1000baseT PHY"
142: #define MII_MODEL_xxBROADCOM_BCM5411 0x0007
143: #define MII_STR_xxBROADCOM_BCM5411 "BCM5411 10/100/1000baseT PHY"
144: #define MII_MODEL_xxBROADCOM_BCM5462 0x000d
145: #define MII_STR_xxBROADCOM_BCM5462 "BCM5462 10/100/1000baseT PHY"
146: #define MII_MODEL_xxBROADCOM_BCM5421 0x000e
147: #define MII_STR_xxBROADCOM_BCM5421 "BCM5421 10/100/1000baseT PHY"
148: #define MII_MODEL_xxBROADCOM_BCM5752 0x0010
149: #define MII_STR_xxBROADCOM_BCM5752 "BCM5752 10/100/1000baseT PHY"
150: #define MII_MODEL_xxBROADCOM_BCM5701 0x0011
151: #define MII_STR_xxBROADCOM_BCM5701 "BCM5701 10/100/1000baseT PHY"
152: #define MII_MODEL_xxBROADCOM_BCM5706C 0x0015
153: #define MII_STR_xxBROADCOM_BCM5706C "BCM5706C 10/100/1000baseT PHY"
154: #define MII_MODEL_xxBROADCOM_BCM5703 0x0016
155: #define MII_STR_xxBROADCOM_BCM5703 "BCM5703 10/100/1000baseT PHY"
156: #define MII_MODEL_xxBROADCOM_BCM5704 0x0019
157: #define MII_STR_xxBROADCOM_BCM5704 "BCM5704 10/100/1000baseT PHY"
158: #define MII_MODEL_xxBROADCOM_BCM5705 0x001a
159: #define MII_STR_xxBROADCOM_BCM5705 "BCM5705 10/100/1000baseT PHY"
160: #define MII_MODEL_xxBROADCOM_BCM5750 0x0018
161: #define MII_STR_xxBROADCOM_BCM5750 "BCM5750 10/100/1000baseT PHY"
162: #define MII_MODEL_xxBROADCOM_BCM54K2 0x002e
163: #define MII_STR_xxBROADCOM_BCM54K2 "BCM54K2 10/100/1000baseT PHY"
164: #define MII_MODEL_xxBROADCOM_BCM5714 0x0034
165: #define MII_STR_xxBROADCOM_BCM5714 "BCM5714 10/100/1000baseT PHY"
166: #define MII_MODEL_xxBROADCOM_BCM5780 0x0035
167: #define MII_STR_xxBROADCOM_BCM5780 "BCM5780 10/100/1000baseT PHY"
168: #define MII_MODEL_xxBROADCOM_BCM5708C 0x0036
169: #define MII_STR_xxBROADCOM_BCM5708C "BCM5708C 10/100/1000baseT PHY"
170: #define MII_MODEL_xxBROADCOM2_BCM5755 0x000c
171: #define MII_STR_xxBROADCOM2_BCM5755 "BCM5755 10/100/1000baseT PHY"
172: #define MII_MODEL_xxBROADCOM2_BCM5787 0x000e
173: #define MII_STR_xxBROADCOM2_BCM5787 "BCM5787 10/100/1000baseT PHY"
174: #define MII_MODEL_BROADCOM_BCM5400 0x0004
175: #define MII_STR_BROADCOM_BCM5400 "BCM5400 1000baseT PHY"
176: #define MII_MODEL_BROADCOM_BCM5401 0x0005
177: #define MII_STR_BROADCOM_BCM5401 "BCM5401 1000baseT PHY"
178: #define MII_MODEL_BROADCOM_BCM5411 0x0007
179: #define MII_STR_BROADCOM_BCM5411 "BCM5411 1000baseT PHY"
180: #define MII_MODEL_BROADCOM_3C905B 0x0012
181: #define MII_STR_BROADCOM_3C905B "Broadcom 3C905B internal PHY"
182: #define MII_MODEL_BROADCOM_3C905C 0x0017
183: #define MII_STR_BROADCOM_3C905C "Broadcom 3C905C internal PHY"
184: #define MII_MODEL_BROADCOM_BCM5221 0x001e
185: #define MII_STR_BROADCOM_BCM5221 "BCM5221 100baseTX PHY"
186: #define MII_MODEL_BROADCOM_BCM5201 0x0021
187: #define MII_STR_BROADCOM_BCM5201 "BCM5201 10/100 PHY"
188: #define MII_MODEL_BROADCOM_BCM5214 0x0028
189: #define MII_STR_BROADCOM_BCM5214 "BCM5214 Quad 10/100 PHY"
190: #define MII_MODEL_BROADCOM_BCM5222 0x0032
191: #define MII_STR_BROADCOM_BCM5222 "BCM5222 Dual 10/100 PHY"
192: #define MII_MODEL_BROADCOM_BCM5220 0x0033
193: #define MII_STR_BROADCOM_BCM5220 "BCM5220 10/100 PHY"
194: #define MII_MODEL_BROADCOM_BCM4401 0x0036
195: #define MII_STR_BROADCOM_BCM4401 "BCM4401 10/100baseTX PHY"
196:
197: /* Cicada Semiconductor PHYs (now owned by Vitesse) */
198: #define MII_MODEL_CICADA_CS8201 0x0001
199: #define MII_STR_CICADA_CS8201 "Cicada CS8201 10/100/1000TX PHY"
200: #define MII_MODEL_CICADA_VSC8211 0x000b
201: #define MII_STR_CICADA_VSC8211 "VSC8211 10/100/1000 PHY"
202: #define MII_MODEL_CICADA_CS8201A 0x0020
203: #define MII_STR_CICADA_CS8201A "Cicada CS8201 10/100/1000TX PHY"
204: #define MII_MODEL_CICADA_CS8201B 0x0021
205: #define MII_STR_CICADA_CS8201B "Cicada CS8201 10/100/1000TX PHY"
206: #define MII_MODEL_xxCICADA_CS8201B 0x0021
207: #define MII_STR_xxCICADA_CS8201B "Cicada CS8201 10/100/1000TX PHY"
208: #define MII_MODEL_VITESSE_VSC8601 0x0002
209: #define MII_STR_VITESSE_VSC8601 "VSC8601 10/100/1000 PHY"
210:
211: /* Davicom Semiconductor PHYs */
212: #define MII_MODEL_xxDAVICOM_DM9101 0x0000
213: #define MII_STR_xxDAVICOM_DM9101 "DM9101 10/100 PHY"
214: #define MII_MODEL_DAVICOM_DM9102 0x0004
215: #define MII_STR_DAVICOM_DM9102 "DM9102 10/100 PHY"
216: #define MII_MODEL_DAVICOM_DM9601 0x000c
217: #define MII_STR_DAVICOM_DM9601 "DM9601 10/100 PHY"
218:
219: /* Enable Semiconductor PHYs (Agere) */
220: #define MII_MODEL_ENABLESEMI_LU3X31FT 0x0001
221: #define MII_STR_ENABLESEMI_LU3X31FT "Enable LU3X31FT"
222: #define MII_MODEL_ENABLESEMI_88E1000S 0x0004
223: #define MII_STR_ENABLESEMI_88E1000S "Enable 88E1000S"
224: #define MII_MODEL_ENABLESEMI_88E1000 0x0005
225: #define MII_STR_ENABLESEMI_88E1000 "Enable 88E1000"
226:
227: /* Marvell Semiconductor PHYs */
228: #define MII_MODEL_MARVELL_E1000_1 0x0000
229: #define MII_STR_MARVELL_E1000_1 "Marvell 88E1000 1 Gigabit PHY"
230: #define MII_MODEL_MARVELL_E1011 0x0002
231: #define MII_STR_MARVELL_E1011 "Marvell 88E1011 Gigabit PHY"
232: #define MII_MODEL_MARVELL_E1000_2 0x0003
233: #define MII_STR_MARVELL_E1000_2 "Marvell 88E1000 2 Gigabit PHY"
234: #define MII_MODEL_MARVELL_E1000S 0x0004
235: #define MII_STR_MARVELL_E1000S "Marvell 88E1000S Gigabit PHY"
236: #define MII_MODEL_MARVELL_E1000_3 0x0005
237: #define MII_STR_MARVELL_E1000_3 "Marvell 88E1000 3 Gigabit PHY"
238: #define MII_MODEL_MARVELL_E1000_4 0x0006
239: #define MII_STR_MARVELL_E1000_4 "Marvell 88E1000 4 Gigabit PHY"
240: #define MII_MODEL_MARVELL_E3082 0x0008
241: #define MII_STR_MARVELL_E3082 "Marvell 88E3082 10/100 PHY"
242: #define MII_MODEL_MARVELL_E1112 0x0009
243: #define MII_STR_MARVELL_E1112 "Marvell 88E1112 Gigabit PHY"
244: #define MII_MODEL_MARVELL_E1149 0x000b
245: #define MII_STR_MARVELL_E1149 "Marvell 88E1149 Gigabit PHY"
246: #define MII_MODEL_MARVELL_E1111 0x000c
247: #define MII_STR_MARVELL_E1111 "Marvell 88E1111 Gigabit PHY"
248: #define MII_MODEL_MARVELL_E1116 0x0021
249: #define MII_STR_MARVELL_E1116 "Marvell 88E1116 Gigabit PHY"
250: #define MII_MODEL_MARVELL_E1118 0x0022
251: #define MII_STR_MARVELL_E1118 "Marvell 88E1118 Gigabit PHY"
252: #define MII_MODEL_xxMARVELL_E1000_5 0x0002
253: #define MII_STR_xxMARVELL_E1000_5 "Marvell 88E1000 5 Gigabit PHY"
254: #define MII_MODEL_xxMARVELL_E1000_6 0x0003
255: #define MII_STR_xxMARVELL_E1000_6 "Marvell 88E1000 6 Gigabit PHY"
256: #define MII_MODEL_xxMARVELL_E1000_7 0x0005
257: #define MII_STR_xxMARVELL_E1000_7 "Marvell 88E1000 7 Gigabit PHY"
258: #define MII_MODEL_xxMARVELL_E1111 0x000c
259: #define MII_STR_xxMARVELL_E1111 "Marvell 88E1111 Gigabit PHY"
260:
261: /* Contrived vendor/model for dcphy */
262: #define MII_MODEL_xxDEC_xxDC 0x0001
263: #define MII_STR_xxDEC_xxDC "DC"
264:
265: /* IC Plus Corp. PHYs */
266: #define MII_MODEL_ICPLUS_IP100 0x0004
267: #define MII_STR_ICPLUS_IP100 "IP100 10/100 PHY"
268: #define MII_MODEL_ICPLUS_IP101 0x0005
269: #define MII_STR_ICPLUS_IP101 "IP101 10/100 PHY"
270: #define MII_MODEL_ICPLUS_IP1000A 0x0008
271: #define MII_STR_ICPLUS_IP1000A "IP1000A 10/100/1000 PHY"
272: #define MII_MODEL_ICPLUS_IP1001 0x0025
273: #define MII_STR_ICPLUS_IP1001 "IP1001 10/100/1000 PHY"
274:
275: /* Integrated Circuit Systems PHYs */
276: #define MII_MODEL_xxICS_1890 0x0002
277: #define MII_STR_xxICS_1890 "ICS1890 10/100 PHY"
278: #define MII_MODEL_xxICS_1892 0x0003
279: #define MII_STR_xxICS_1892 "ICS1892 10/100 PHY"
280: #define MII_MODEL_xxICS_1893 0x0004
281: #define MII_STR_xxICS_1893 "ICS1893 10/100 PHY"
282:
283: /* Intel PHYs */
284: #define MII_MODEL_xxINTEL_I82553 0x0000
285: #define MII_STR_xxINTEL_I82553 "i82553 10/100 PHY"
286: #define MII_MODEL_INTEL_I82555 0x0015
287: #define MII_STR_INTEL_I82555 "i82555 10/100 PHY"
288: #define MII_MODEL_INTEL_I82562EM 0x0032
289: #define MII_STR_INTEL_I82562EM "i82562EM 10/100 PHY"
290: #define MII_MODEL_INTEL_I82562ET 0x0033
291: #define MII_STR_INTEL_I82562ET "i82562ET 10/100 PHY"
292: #define MII_MODEL_INTEL_I82553 0x0035
293: #define MII_STR_INTEL_I82553 "i82553 10/100 PHY"
294:
295: /* Jato Technologies PHYs */
296: #define MII_MODEL_JATO_BASEX 0x0000
297: #define MII_STR_JATO_BASEX "Jato 1000baseX PHY"
298:
299: /* Level 1 PHYs */
300: #define MII_MODEL_xxLEVEL1_LXT970 0x0000
301: #define MII_STR_xxLEVEL1_LXT970 "LXT970 10/100 PHY"
302: #define MII_MODEL_LEVEL1_LXT1000_OLD 0x0003
303: #define MII_STR_LEVEL1_LXT1000_OLD "LXT1000 10/100/1000 PHY"
304: #define MII_MODEL_LEVEL1_LXT1000 0x000c
305: #define MII_STR_LEVEL1_LXT1000 "LXT1000 10/100/1000 PHY"
306: #define MII_MODEL_xxLEVEL1a_LXT971 0x000e
307: #define MII_STR_xxLEVEL1a_LXT971 "LXT971 10/100 PHY"
308:
309: /* Lucent Technologies PHYs */
310: #define MII_MODEL_LUCENT_LU6612 0x000c
311: #define MII_STR_LUCENT_LU6612 "LU6612 10/100 PHY"
312: #define MII_MODEL_LUCENT_LU3X51FT 0x0033
313: #define MII_STR_LUCENT_LU3X51FT "LU3X51FT 10/100 PHY"
314: #define MII_MODEL_LUCENT_LU3X54FT 0x0036
315: #define MII_STR_LUCENT_LU3X54FT "LU3X54FT 10/100 PHY"
316:
317: /* Myson Technology PHYs */
318: #define MII_MODEL_MYSON_MTD972 0x0000
319: #define MII_STR_MYSON_MTD972 "MTD972 10/100 PHY"
320:
321: /* National Semiconductor PHYs */
322: #define MII_MODEL_NATSEMI_DP83840 0x0000
323: #define MII_STR_NATSEMI_DP83840 "DP83840 10/100 PHY"
324: #define MII_MODEL_NATSEMI_DP83843 0x0001
325: #define MII_STR_NATSEMI_DP83843 "DP83843 10/100 PHY"
326: #define MII_MODEL_NATSEMI_DP83815 0x0002
327: #define MII_STR_NATSEMI_DP83815 "DP83815 10/100 PHY"
328: #define MII_MODEL_NATSEMI_DP83847 0x0003
329: #define MII_STR_NATSEMI_DP83847 "DP83847 10/100 PHY"
330: #define MII_MODEL_NATSEMI_DP83891 0x0005
331: #define MII_STR_NATSEMI_DP83891 "DP83891 10/100/1000 PHY"
332: #define MII_MODEL_NATSEMI_DP83861 0x0006
333: #define MII_STR_NATSEMI_DP83861 "DP83861 10/100/1000 PHY"
334:
335: /* Plessey Semiconductor PHYs */
336: #define MII_MODEL_PLESSEY_NWK914 0x0000
337: #define MII_STR_PLESSEY_NWK914 "NWK914 10/100 PHY"
338:
339: /* Quality Semiconductor PHYs */
340: #define MII_MODEL_QUALSEMI_QS6612 0x0000
341: #define MII_STR_QUALSEMI_QS6612 "QS6612 10/100 PHY"
342:
343: /* Realtek Semiconductor PHYs */
344: #define MII_MODEL_REALTEK_RTL8201L 0x0020
345: #define MII_STR_REALTEK_RTL8201L "RTL8201L 10/100 PHY"
346: #define MII_MODEL_xxREALTEK_RTL8169S 0x0011
347: #define MII_STR_xxREALTEK_RTL8169S "RTL8169S/8110S PHY"
348:
349: /* Seeq PHYs */
350: #define MII_MODEL_xxSEEQ_80220 0x0003
351: #define MII_STR_xxSEEQ_80220 "Seeq 80220 10/100 PHY"
352: #define MII_MODEL_xxSEEQ_84220 0x0004
353: #define MII_STR_xxSEEQ_84220 "Seeq 84220 10/100 PHY"
354: #define MII_MODEL_xxSEEQ_80225 0x0008
355: #define MII_STR_xxSEEQ_80225 "Seeq 80225 10/100 PHY"
356:
357: /* Silicon Integrated Systems PHYs */
358: #define MII_MODEL_xxSIS_900 0x0000
359: #define MII_STR_xxSIS_900 "SiS 900 10/100 PHY"
360:
361: /* Standard Microsystems PHYs */
362: #define MII_MODEL_SMSC_LAN83C185 0x000a
363: #define MII_STR_SMSC_LAN83C185 "LAN83C185 10/100 PHY"
364:
365: /* Texas Instruments PHYs */
366: #define MII_MODEL_xxTI_TLAN10T 0x0001
367: #define MII_STR_xxTI_TLAN10T "ThunderLAN 10baseT PHY"
368: #define MII_MODEL_xxTI_100VGPMI 0x0002
369: #define MII_STR_xxTI_100VGPMI "ThunderLAN 100VG-AnyLan PHY"
370: #define MII_MODEL_xxTI_TNETE2101 0x0003
371: #define MII_STR_xxTI_TNETE2101 "TNETE2101 PHY"
372:
373: /* TDK Semiconductor PHYs */
374: #define MII_MODEL_TSC_78Q2120 0x0014
375: #define MII_STR_TSC_78Q2120 "78Q2120 10/100 PHY"
376: #define MII_MODEL_TSC_78Q2121 0x0015
377: #define MII_STR_TSC_78Q2121 "78Q2121 100baseTX PHY"
378:
379: /* VIA Networking Technologies PHYs */
380: #define MII_MODEL_VIA_VT6103 0x0032
381: #define MII_STR_VIA_VT6103 "VT6103 10/100 PHY"
382: #define MII_MODEL_VIA_VT6103_2 0x0034
383: #define MII_STR_VIA_VT6103_2 "VT6103 10/100 PHY"
384:
385: /* XaQti Corp. PHYs */
386: #define MII_MODEL_XAQTI_XMACII 0x0000
387: #define MII_STR_XAQTI_XMACII "XaQti Corp. XMAC II Gigabit PHY"
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