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Annotation of sys/dev/mii/lxtphyreg.h, Revision 1.1.1.1

1.1       nbrk        1: /*     $OpenBSD: lxtphyreg.h,v 1.1 1998/11/11 19:34:47 jason Exp $     */
                      2: /*     $NetBSD: lxtphyreg.h,v 1.1 1998/10/24 00:33:17 thorpej Exp $    */
                      3:
                      4: /*-
                      5:  * Copyright (c) 1998 The NetBSD Foundation, Inc.
                      6:  * All rights reserved.
                      7:  *
                      8:  * This code is derived from software contributed to The NetBSD Foundation
                      9:  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
                     10:  * NASA Ames Research Center.
                     11:  *
                     12:  * Redistribution and use in source and binary forms, with or without
                     13:  * modification, are permitted provided that the following conditions
                     14:  * are met:
                     15:  * 1. Redistributions of source code must retain the above copyright
                     16:  *    notice, this list of conditions and the following disclaimer.
                     17:  * 2. Redistributions in binary form must reproduce the above copyright
                     18:  *    notice, this list of conditions and the following disclaimer in the
                     19:  *    documentation and/or other materials provided with the distribution.
                     20:  * 3. All advertising materials mentioning features or use of this software
                     21:  *    must display the following acknowledgement:
                     22:  *     This product includes software developed by the NetBSD
                     23:  *     Foundation, Inc. and its contributors.
                     24:  * 4. Neither the name of The NetBSD Foundation nor the names of its
                     25:  *    contributors may be used to endorse or promote products derived
                     26:  *    from this software without specific prior written permission.
                     27:  *
                     28:  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
                     29:  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
                     30:  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
                     31:  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
                     32:  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
                     33:  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
                     34:  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
                     35:  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
                     36:  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
                     37:  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
                     38:  * POSSIBILITY OF SUCH DAMAGE.
                     39:  */
                     40:
                     41: #ifndef _DEV_MII_LXTPHYREG_H_
                     42: #define        _DEV_MII_LXTPHYREG_H_
                     43:
                     44: /*
                     45:  * LXT970 registers.
                     46:  */
                     47:
                     48: #define        MII_LXTPHY_MIRROR       0x10    /* Mirror register */
                     49:        /* All bits user-defined */
                     50:
                     51: #define        MII_LXTPHY_IER          0x11    /* Interrupt Enable Register */
                     52: #define        IER_MIIDRVLVL           0x0008  /* Rediced MII driver levels */
                     53: #define        IER_LNK_CRITERIA        0x0004  /* Enhanced Link Loss Criteria */
                     54: #define        IER_INTEN               0x0002  /* Interrupt Enable */
                     55: #define        IER_TINT                0x0001  /* Force Interrupt */
                     56:
                     57: #define        MII_LXTPHY_ISR          0x12    /* Interrupt Status Register */
                     58: #define        ISR_MINT                0x8000  /* MII Interrupt Pending */
                     59: #define        ISR_XTALOK              0x4000  /* Clocks OK */
                     60:
                     61: #define        MII_LXTPHY_CONFIG       0x13    /* Configuration Register */
                     62: #define        CONFIG_TXMIT_TEST       0x4000  /* 100base-T Transmit Test */
                     63: #define        CONFIG_REPEATER         0x2000  /* Repeater Mode */
                     64: #define        CONFIG_MDIO_INT         0x1000  /* Enable intr signalling on MDIO */
                     65: #define        CONFIG_TPLOOP           0x0800  /* Disable 10base-T Loopback */
                     66: #define        CONFIG_SQE              0x0400  /* Enable SQE */
                     67: #define        CONFIG_DISJABBER        0x0200  /* Disable Jabber */
                     68: #define        CONFIG_DISLINKTEST      0x0100  /* Disable Link Test */
                     69: #define        CONFIG_LEDC1            0x0080  /* LEDC configuration */
                     70: #define        CONFIG_LEDC0            0x0040  /* ... */
                     71:                                        /* 0 0 LEDC indicates collision */
                     72:                                        /* 0 1 LEDC is off */
                     73:                                        /* 1 0 LEDC indicates activity */
                     74:                                        /* 1 1 LEDC is on */
                     75: #define        CONFIG_ADVTXCLK         0x0020  /* Advance TX clock */
                     76: #define        CONFIG_5BSYMBOL         0x0010  /* 5-bit Symbol mode */
                     77: #define        CONFIG_SCRAMBLER        0x0008  /* Bypass scrambler */
                     78: #define        CONFIG_100BASEFX        0x0004  /* 100base-FX */
                     79: #define        CONFIG_TXDISCON         0x0001  /* Disconnect TP transmitter */
                     80:
                     81: #define        MII_LXTPHY_CSR          0x14    /* Chip Status Register */
                     82: #define        CSR_LINK                0x2000  /* Link is up */
                     83: #define        CSR_DUPLEX              0x1000  /* Full-duplex */
                     84: #define        CSR_SPEED               0x0800  /* 100Mbps */
                     85: #define        CSR_ACOMP               0x0400  /* Autonegotiation complete */
                     86: #define        CSR_PAGERCVD            0x0200  /* Link page received */
                     87: #define        CSR_LOWVCC              0x0004  /* Low Voltage Fault */
                     88:
                     89: #endif /* _DEV_MII_LXTPHYREG_H_ */