Annotation of sys/dev/mii/bmtphyreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: bmtphyreg.h,v 1.3 2005/02/04 23:23:56 brad Exp $ */
2: /* $NetBSD: bmtphyreg.h,v 1.1 2001/06/02 21:42:10 thorpej Exp $ */
3:
4: /*-
5: * Copyright (c) 2001 Theo de Raadt
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: *
16: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
17: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26: * SUCH DAMAGE.
27: */
28:
29: #ifndef _DEV_MII_BMTPHYREG_H_
30: #define _DEV_MII_BMTPHYREG_H_
31:
32: /*
33: * BCM5201/BCM5202 registers.
34: */
35:
36: #define MII_BMTPHY_AUX_CTL 0x10 /* auxiliary control */
37: #define AUX_CTL_TXDIS 0x2000 /* transmitter disable */
38: #define AUX_CTL_4B5B_BYPASS 0x0400 /* bypass 4b5b encoder */
39: #define AUX_CTL_SCR_BYPASS 0x0200 /* bypass scrambler */
40: #define AUX_CTL_NRZI_BYPASS 0x0100 /* bypass NRZI encoder */
41: #define AUX_CTL_RXALIGN_BYPASS 0x0080 /* bypass rx symbol alignment */
42: #define AUX_CTL_BASEWANDER_DIS 0x0040 /* disable baseline wander correction */
43: #define AUX_CTL_FEF_EN 0x0020 /* far-end fault enable */
44:
45: #define MII_BMTPHY_AUX_STS 0x11 /* auxiliary status */
46: #define AUX_STS_FX_MODE 0x0400 /* 100base-FX mode (strap pin) */
47: #define AUX_STS_LOCKED 0x0200 /* descrambler locked */
48: #define AUX_STS_100BASE_LINK 0x0100 /* 1 = 100base link */
49: #define AUX_STS_REMFAULT 0x0080 /* remote fault */
50: #define AUX_STS_DISCON_STATE 0x0040 /* disconnect state */
51: #define AUX_STS_FCARDET 0x0020 /* false carrier detected */
52: #define AUX_STS_BAD_ESD 0x0010 /* bad ESD detected */
53: #define AUX_STS_RXERROR 0x0008 /* Rx error detected */
54: #define AUX_STS_TXERROR 0x0004 /* Tx error detected */
55: #define AUX_STS_LOCKERROR 0x0002 /* lock error detected */
56: #define AUX_STS_MLT3ERROR 0x0001 /* MLT3 code error detected */
57:
58: #define MII_BMTPHY_RXERROR_CTR 0x12 /* 100base-X Rx error counter */
59: #define RXERROR_CTR_MASK 0x00ff
60:
61: #define MII_BMTPHY_FCS_CTR 0x13 /* 100base-X false carrier counter */
62: #define FCS_CTR_MASK 0x00ff
63:
64: #define MII_BMTPHY_DIS_CTR 0x14 /* 100base-X disconnect counter */
65: #define DIS_CTR_MASK 0x00ff
66:
67: #define MII_BMTPHY_PTEST 0x17 /* PTEST */
68:
69: #define MII_BMTPHY_AUX_CSR 0x18 /* auxiliary control/status */
70: #define AUX_CSR_JABBER_DIS 0x8000 /* jabber disable */
71: #define AUX_CSR_FLINK 0x4000 /* force 10baseT link pass */
72: #define AUX_CSR_HSQ 0x0080 /* SQ high */
73: #define AUX_CSR_LSQ 0x0040 /* SQ low */
74: #define AUX_CSR_ER1 0x0020 /* edge rate 1 */
75: #define AUX_CSR_ER0 0x0010 /* edge rate 0 */
76: #define AUX_CSR_ANEG 0x0008 /* auto-negotiation activated */
77: #define AUX_CSR_F100 0x0004 /* force 100base */
78: #define AUX_CSR_SPEED 0x0002 /* 1 = 100, 0 = 10 */
79: #define AUX_CSR_FDX 0x0001 /* full-duplex */
80:
81: #define MII_BMTPHY_AUX_SS 0x19 /* auxiliary status summary */
82: #define AUX_SS_ACOMP 0x8000 /* auto-negotiation complete */
83: #define AUX_SS_ACOMP_ACK 0x4000 /* auto-negotiation compl. ack */
84: #define AUX_SS_AACK_DET 0x2000 /* auto-neg. ack detected */
85: #define AUX_SS_ANLPAD 0x1000 /* auto-neg. link part. ability det */
86: #define AUX_SS_ANEG_PAUSE 0x0800 /* pause operation bit */
87: #define AUX_SS_HCD 0x0700 /* highest common denominator */
88: #define AUX_SS_HCD_NONE 0x0000 /* none */
89: #define AUX_SS_HCD_10T 0x0100 /* 10baseT */
90: #define AUX_SS_HCD_10T_FDX 0x0200 /* 10baseT-FDX */
91: #define AUX_SS_HCD_100TX 0x0300 /* 100baseTX-FDX */
92: #define AUX_SS_HCD_100T4 0x0400 /* 100baseT4 */
93: #define AUX_SS_HCD_100TX_FDX 0x0500 /* 100baseTX-FDX */
94: #define AUX_SS_PDF 0x0080 /* parallel detection fault */
95: #define AUX_SS_LPRF 0x0040 /* link partner remote fault */
96: #define AUX_SS_LPPR 0x0020 /* link partner page received */
97: #define AUX_SS_LPANA 0x0010 /* link partner auto-neg able */
98: #define AUX_SS_SPEED 0x0008 /* 1 = 100, 0 = 10 */
99: #define AUX_SS_LINK 0x0004 /* link pass */
100: #define AUX_SS_ANEN 0x0002 /* auto-neg. enabled */
101: #define AUX_SS_JABBER 0x0001 /* jabber detected */
102:
103: #define MII_BMTPHY_INTR 0x1a /* interrupt register */
104: #define INTR_FDX_LED 0x8000 /* full-duplex led enable */
105: #define INTR_INTR_EN 0x4000 /* interrupt enable */
106: #define INTR_FDX_MASK 0x0800 /* full-dupled intr mask */
107: #define INTR_SPD_MASK 0x0400 /* speed intr mask */
108: #define INTR_LINK_MASK 0x0200 /* link intr mask */
109: #define INTR_INTR_MASK 0x0100 /* master interrupt mask */
110: #define INTR_FDX_CHANGE 0x0008 /* full-duplex change */
111: #define INTR_SPD_CHANGE 0x0004 /* speed change */
112: #define INTR_LINK_CHANGE 0x0002 /* link change */
113: #define INTR_INTR_STATUS 0x0001 /* interrupt status */
114:
115: #define MII_BMTPHY_AUX2 0x1b /* auliliary mode 2 */
116: #define AUX2_BLOCK_RXDV 0x0200 /* block RXDV mode enabled */
117: #define AUX2_ANPDQ 0x0100 /* auto-neg parallel detection Q mode */
118:
119: #endif /* _DEV_MII_BMTPHYREG_H_ */
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