Annotation of sys/dev/mii/acphyreg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: acphyreg.h,v 1.2 2004/10/01 04:08:45 jsg Exp $ */
! 2: /* $NetBSD: acphyreg.h,v 1.1 2001/08/24 17:54:33 thorpej Exp $ */
! 3:
! 4: /*
! 5: * Copyright 2001 Wasabi Systems, Inc.
! 6: * All rights reserved.
! 7: *
! 8: * Written by Jason R. Thorpe for Wasabi Systems, Inc.
! 9: *
! 10: * Redistribution and use in source and binary forms, with or without
! 11: * modification, are permitted provided that the following conditions
! 12: * are met:
! 13: * 1. Redistributions of source code must retain the above copyright
! 14: * notice, this list of conditions and the following disclaimer.
! 15: * 2. Redistributions in binary form must reproduce the above copyright
! 16: * notice, this list of conditions and the following disclaimer in the
! 17: * documentation and/or other materials provided with the distribution.
! 18: * 3. All advertising materials mentioning features or use of this software
! 19: * must display the following acknowledgement:
! 20: * This product includes software developed for the NetBSD Project by
! 21: * Wasabi Systems, Inc.
! 22: * 4. The name of Wasabi Systems, Inc. may not be used to endorse
! 23: * or promote products derived from this software without specific prior
! 24: * written permission.
! 25: *
! 26: * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
! 27: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
! 28: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
! 29: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
! 30: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
! 31: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
! 32: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
! 33: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
! 34: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
! 35: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 36: * POSSIBILITY OF SUCH DAMAGE.
! 37: */
! 38:
! 39: #ifndef _DEV_MII_ACPHYREG_H_
! 40: #define _DEV_MII_ACPHYREG_H_
! 41:
! 42: /*
! 43: * Altima AC101 PHY registers.
! 44: *
! 45: * Note the AC101 and the AMD Ac79c874 are the same PHY core. There
! 46: * are some registers documented in the AC101 manual that are not in
! 47: * the Am79c874 manual, and vice-versa. I have no idea how to tell
! 48: * the two apart, but we don't really use the registers that fall into
! 49: * this category, anyhow.
! 50: */
! 51:
! 52: #define MII_ACPHY_PILR 0x10 /* polarity and interrupt control */
! 53: #define PILR_REPEATER 0x8000 /* repeater mode */
! 54: #define PILR_INTR_LEVL 0x4000 /* 1 = active high, 0 = active low */
! 55: #define PILR_SQE_INHIBIT 0x0800 /* disable 10T SQE testing */
! 56: #define PILR_10T_LOOP 0x0400 /* enable loopback in 10T */
! 57: #define PILR_GPIO1_DATA 0x0200 /* GPIO1 pin */
! 58: #define PILR_GPIO1_DIR 0x0100 /* 1 = input */
! 59: #define PILR_GPIO0_DATA 0x0080 /* GPIO0 pin */
! 60: #define PILR_GPIO0_DIR 0x0040 /* 1 = input */
! 61: #define PILR_AUTO_POL_DIS 0x0020 /* disable auto-polarity */
! 62: #define PILR_REVERSE_POL 0x0010 /* 1 = reverse, 0 = normal */
! 63: #define PILR_RXCLK_CTRL 0x0001 /* disable RX_CLK when idle */
! 64:
! 65:
! 66: #define MII_ACPHY_ICSR 0x11 /* interrupt control/status */
! 67: #define ICSR_JABBER_IE 0x8000 /* jabber interrupt enable */
! 68: #define ICSR_RX_ER_IE 0x4000 /* Rx error interrupt enable */
! 69: #define ICSR_PAGE_RX_IE 0x2000 /* page received interrupt enable */
! 70: #define ICSR_PD_FAULT_IE 0x1000 /* parallel detection fault int en */
! 71: #define ICSR_LP_ACK_IE 0x0800 /* link partner ACK interrupt en */
! 72: #define ICSR_LNK_NOT_OK_IE 0x0400 /* link not okay interrupt enable */
! 73: #define ICSR_R_FAULT_IE 0x0200 /* remote fault interrupt enable */
! 74: #define ICSR_ANEG_COMP_IE 0x0100 /* autonegotiation complete int en */
! 75: #define ICSR_JABBER_INT 0x0080 /* jabber interrupt */
! 76: #define ICSR_RX_ER_INT 0x0040 /* Rx error interrupt */
! 77: #define ICSR_PAGE_RX_INT 0x0020 /* page received interrupt */
! 78: #define ICSR_PD_FAULT_INT 0x0010 /* parallel detection fault interrupt */
! 79: #define ICSR_LP_ACK_INT 0x0008 /* link partner ACK interrupt */
! 80: #define ICSR_LNK_NOT_OK_INT 0x0004 /* link not okay interrupt */
! 81: #define ICSR_R_FAULT_INT 0x0002 /* remote fault interrupt */
! 82: #define ICSR_ANEG_COMP_INT 0x0001 /* autonegotiation complete interrupt */
! 83:
! 84:
! 85: #define MII_ACPHY_DR 0x12 /* diagnostic register */
! 86: #define DR_DPLX 0x0800 /* full-duplex resolved */
! 87: #define DR_SPEED 0x0400 /* 100BASE-TX resolved */
! 88: #define DR_RX_PASS 0x0200 /* manchester/signal received */
! 89: #define DR_RX_LOCK 0x0100 /* PLL signal has been locked */
! 90:
! 91:
! 92: #define MII_ACPHY_PLR 0x13 /* power/loopback register */
! 93: #define PLR_TB125 0x0040 /* Tx transformer ratio 1.25:1 */
! 94: #define PLR_LOW_POWER_MODE 0x0020 /* enable advanced power saving mode */
! 95: #define PLR_TEST_LOOPBACK 0x0010 /* enable test loopback */
! 96: #define PLR_DIGITAL_LOOPBACK 0x0008 /* enable loopback */
! 97: #define PLR_LP_LPBK 0x0004 /* enable link pulse loopback */
! 98: #define PLR_NLP_LINK_INT_TEST 0x0002 /* send NLP instead of FLP */
! 99: #define PLR_REDUCE_TIMER 0x0001 /* reduce time constant for aneg */
! 100:
! 101:
! 102: /* AC101 only */
! 103: #define MII_ACPHY_CMR 0x14 /* cable measurement register */
! 104: #define CMR_MASK 0x00f0 /* cable measurement mask */
! 105:
! 106:
! 107: #define MII_ACPHY_MCR 0x15 /* mode control register */
! 108: #define MCR_NLP_DISABLE 0x4000 /* force good 10BASE-T link */
! 109: #define MCR_FORCE_LINK_UP 0x2000 /* force good 100BASE-TX link */
! 110: #define MCR_JABBER_DISABLE 0x1000 /* disable jabber function */
! 111: #define MCR_10BT_SEL 0x0800 /* enable 7-wire 10T operation */
! 112: #define MCR_CONF_ALED 0x0400 /* 1 = ALED only Rx, 0 = ALED Rx/Tx */
! 113: #define MCR_LED_SEL 0x0200 /* 1 = tqphy-compat LED config */
! 114: #define MCR_FEF_DIS 0x0100 /* disable far-end-fault insertion */
! 115: #define MCR_FORCE_FEF_TX 0x0080 /* force FEF transmission */
! 116: #define MCR_RX_ER_CNT_FULL 0x0040 /* Rx error counter full */
! 117: #define MCR_DIS_RX_ER_CNT 0x0020 /* disable Rx error counter */
! 118: #define MCR_DIS_WDT 0x0010 /* disable the watchdog timer */
! 119: #define MCR_EN_RPBK 0x0008 /* enable remote loopback */
! 120: #define MCR_DIS_SCRM 0x0004 /* enable 100M data scrambling */
! 121: #define MCR_PCSBP 0x0002 /* bypass PCS */
! 122: #define MCR_FX_SEL 0x0001 /* FX mode selected */
! 123:
! 124:
! 125: /* Am79c874 only */
! 126: #define MII_ACPHY_DCR 0x17 /* disconnect counter register */
! 127:
! 128:
! 129: #define MII_ACPHY_RECR 0x18 /* receive error counter register */
! 130:
! 131:
! 132: #endif /* _DEV_MII_ACPHYREG_H_ */
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