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1.1 nbrk 1: /* $OpenBSD: aic7xxx.reg,v 1.11 2007/05/26 00:36:03 krw Exp $ */
2: /*
3: * Aic7xxx register and scratch ram definitions.
4: *
5: * Copyright (c) 1994-2001 Justin T. Gibbs.
6: * Copyright (c) 2000-2001 Adaptec Inc.
7: * All rights reserved.
8: *
9: * Redistribution and use in source and binary forms, with or without
10: * modification, are permitted provided that the following conditions
11: * are met:
12: * 1. Redistributions of source code must retain the above copyright
13: * notice, this list of conditions, and the following disclaimer,
14: * without modification.
15: * 2. Redistributions in binary form must reproduce at minimum a disclaimer
16: * substantially similar to the "NO WARRANTY" disclaimer below
17: * ("Disclaimer") and any redistribution must be conditioned upon
18: * including a substantially similar Disclaimer requirement for further
19: * binary redistribution.
20: * 3. Neither the names of the above-listed copyright holders nor the names
21: * of any contributors may be used to endorse or promote products derived
22: * from this software without specific prior written permission.
23: *
24: * Alternatively, this software may be distributed under the terms of the
25: * GNU General Public License ("GPL") version 2 as published by the Free
26: * Software Foundation.
27: *
28: * NO WARRANTY
29: * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30: * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31: * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
32: * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33: * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
37: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
38: * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39: * POSSIBILITY OF SUCH DAMAGES.
40: *
41: * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.reg,v 1.46 2003/12/17 00:02:09 gibbs Exp $
42: */
43: VERSION = "$Id: aic7xxx.reg,v 1.11 2007/05/26 00:36:03 krw Exp $"
44:
45: /*
46: * This file is processed by the aic7xxx_asm utility for use in assembling
47: * firmware for the aic7xxx family of SCSI host adapters as well as to generate
48: * a C header file for use in the kernel portion of the Aic7xxx driver.
49: *
50: * All page numbers refer to the Adaptec AIC-7770 Data Book available from
51: * Adaptec's Technical Documents Department 1-800-934-2766
52: */
53:
54: /*
55: * SCSI Sequence Control (p. 3-11).
56: * Each bit, when set starts a specific SCSI sequence on the bus
57: */
58: register SCSISEQ {
59: address 0x000
60: access_mode RW
61: field TEMODE 0x80
62: field ENSELO 0x40
63: field ENSELI 0x20
64: field ENRSELI 0x10
65: field ENAUTOATNO 0x08
66: field ENAUTOATNI 0x04
67: field ENAUTOATNP 0x02
68: field SCSIRSTO 0x01
69: }
70:
71: /*
72: * SCSI Transfer Control 0 Register (pp. 3-13).
73: * Controls the SCSI module data path.
74: */
75: register SXFRCTL0 {
76: address 0x001
77: access_mode RW
78: field DFON 0x80
79: field DFPEXP 0x40
80: field FAST20 0x20
81: field CLRSTCNT 0x10
82: field SPIOEN 0x08
83: field SCAMEN 0x04
84: field CLRCHN 0x02
85: }
86:
87: /*
88: * SCSI Transfer Control 1 Register (pp. 3-14,15).
89: * Controls the SCSI module data path.
90: */
91: register SXFRCTL1 {
92: address 0x002
93: access_mode RW
94: field BITBUCKET 0x80
95: field SWRAPEN 0x40
96: field ENSPCHK 0x20
97: mask STIMESEL 0x18
98: field ENSTIMER 0x04
99: field ACTNEGEN 0x02
100: field STPWEN 0x01 /* Powered Termination */
101: }
102:
103: /*
104: * SCSI Control Signal Read Register (p. 3-15).
105: * Reads the actual state of the SCSI bus pins
106: */
107: register SCSISIGI {
108: address 0x003
109: access_mode RO
110: field CDI 0x80
111: field IOI 0x40
112: field MSGI 0x20
113: field ATNI 0x10
114: field SELI 0x08
115: field BSYI 0x04
116: field REQI 0x02
117: field ACKI 0x01
118: /*
119: * Possible phases in SCSISIGI
120: */
121: mask PHASE_MASK CDI|IOI|MSGI
122: mask P_DATAOUT 0x00
123: mask P_DATAIN IOI
124: mask P_DATAOUT_DT P_DATAOUT|MSGI
125: mask P_DATAIN_DT P_DATAIN|MSGI
126: mask P_COMMAND CDI
127: mask P_MESGOUT CDI|MSGI
128: mask P_STATUS CDI|IOI
129: mask P_MESGIN CDI|IOI|MSGI
130: }
131:
132: /*
133: * SCSI Control Signal Write Register (p. 3-16).
134: * Writing to this register modifies the control signals on the bus. Only
135: * those signals that are allowed in the current mode (Initiator/Target) are
136: * asserted.
137: */
138: register SCSISIGO {
139: address 0x003
140: access_mode WO
141: field CDO 0x80
142: field IOO 0x40
143: field MSGO 0x20
144: field ATNO 0x10
145: field SELO 0x08
146: field BSYO 0x04
147: field REQO 0x02
148: field ACKO 0x01
149: /*
150: * Possible phases to write into SCSISIG0
151: */
152: mask PHASE_MASK CDI|IOI|MSGI
153: mask P_DATAOUT 0x00
154: mask P_DATAIN IOI
155: mask P_COMMAND CDI
156: mask P_MESGOUT CDI|MSGI
157: mask P_STATUS CDI|IOI
158: mask P_MESGIN CDI|IOI|MSGI
159: }
160:
161: /*
162: * SCSI Rate Control (p. 3-17).
163: * Contents of this register determine the Synchronous SCSI data transfer
164: * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the
165: * SOFS (3:0) bits disables synchronous data transfers. Any offset value
166: * greater than 0 enables synchronous transfers.
167: */
168: register SCSIRATE {
169: address 0x004
170: access_mode RW
171: field WIDEXFER 0x80 /* Wide transfer control */
172: field ENABLE_CRC 0x40 /* CRC for D-Phases */
173: field SINGLE_EDGE 0x10 /* Disable DT Transfers */
174: mask SXFR 0x70 /* Sync transfer rate */
175: mask SXFR_ULTRA2 0x0f /* Sync transfer rate */
176: mask SOFS 0x0f /* Sync offset */
177: }
178:
179: /*
180: * SCSI ID (p. 3-18).
181: * Contains the ID of the board and the current target on the
182: * selected channel.
183: */
184: register SCSIID {
185: address 0x005
186: access_mode RW
187: mask TID 0xf0 /* Target ID mask */
188: mask TWIN_TID 0x70
189: field TWIN_CHNLB 0x80
190: mask OID 0x0f /* Our ID mask */
191: /*
192: * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book)
193: * The aic7890/91 allow an offset of up to 127 transfers in both wide
194: * and narrow mode.
195: */
196: alias SCSIOFFSET
197: mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */
198: }
199:
200: /*
201: * SCSI Latched Data (p. 3-19).
202: * Read/Write latches used to transfer data on the SCSI bus during
203: * Automatic or Manual PIO mode. SCSIDATH can be used for the
204: * upper byte of a 16bit wide asynchronouse data phase transfer.
205: */
206: register SCSIDATL {
207: address 0x006
208: access_mode RW
209: }
210:
211: register SCSIDATH {
212: address 0x007
213: access_mode RW
214: }
215:
216: /*
217: * SCSI Transfer Count (pp. 3-19,20)
218: * These registers count down the number of bytes transferred
219: * across the SCSI bus. The counter is decremented only once
220: * the data has been safely transferred. SDONE in SSTAT0 is
221: * set when STCNT goes to 0
222: */
223: register STCNT {
224: address 0x008
225: size 3
226: access_mode RW
227: }
228:
229: /* ALT_MODE registers (Ultra2 and Ultra160 chips) */
230: register SXFRCTL2 {
231: address 0x013
232: access_mode RW
233: field AUTORSTDIS 0x10
234: field CMDDMAEN 0x08
235: mask ASYNC_SETUP 0x07
236: }
237:
238: /* ALT_MODE register on Ultra160 chips */
239: register OPTIONMODE {
240: address 0x008
241: access_mode RW
242: field AUTORATEEN 0x80
243: field AUTOACKEN 0x40
244: field ATNMGMNTEN 0x20
245: field BUSFREEREV 0x10
246: field EXPPHASEDIS 0x08
247: field SCSIDATL_IMGEN 0x04
248: field AUTO_MSGOUT_DE 0x02
249: field DIS_MSGIN_DUALEDGE 0x01
250: mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE
251: }
252:
253: /* ALT_MODE register on Ultra160 chips */
254: register TARGCRCCNT {
255: address 0x00a
256: size 2
257: access_mode RW
258: }
259:
260: /*
261: * Clear SCSI Interrupt 0 (p. 3-20)
262: * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
263: */
264: register CLRSINT0 {
265: address 0x00b
266: access_mode WO
267: field CLRSELDO 0x40
268: field CLRSELDI 0x20
269: field CLRSELINGO 0x10
270: field CLRSWRAP 0x08
271: field CLRIOERR 0x08 /* Ultra2 Only */
272: field CLRSPIORDY 0x02
273: }
274:
275: /*
276: * SCSI Status 0 (p. 3-21)
277: * Contains one set of SCSI Interrupt codes
278: * These are most likely of interest to the sequencer
279: */
280: register SSTAT0 {
281: address 0x00b
282: access_mode RO
283: field TARGET 0x80 /* Board acting as target */
284: field SELDO 0x40 /* Selection Done */
285: field SELDI 0x20 /* Board has been selected */
286: field SELINGO 0x10 /* Selection In Progress */
287: field SWRAP 0x08 /* 24bit counter wrap */
288: field IOERR 0x08 /* LVD Tranceiver mode changed */
289: field SDONE 0x04 /* STCNT = 0x000000 */
290: field SPIORDY 0x02 /* SCSI PIO Ready */
291: field DMADONE 0x01 /* DMA transfer completed */
292: }
293:
294: /*
295: * Clear SCSI Interrupt 1 (p. 3-23)
296: * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
297: */
298: register CLRSINT1 {
299: address 0x00c
300: access_mode WO
301: field CLRSELTIMEO 0x80
302: field CLRATNO 0x40
303: field CLRSCSIRSTI 0x20
304: field CLRBUSFREE 0x08
305: field CLRSCSIPERR 0x04
306: field CLRPHASECHG 0x02
307: field CLRREQINIT 0x01
308: }
309:
310: /*
311: * SCSI Status 1 (p. 3-24)
312: */
313: register SSTAT1 {
314: address 0x00c
315: access_mode RO
316: field SELTO 0x80
317: field ATNTARG 0x40
318: field SCSIRSTI 0x20
319: field PHASEMIS 0x10
320: field BUSFREE 0x08
321: field SCSIPERR 0x04
322: field PHASECHG 0x02
323: field REQINIT 0x01
324: }
325:
326: /*
327: * SCSI Status 2 (pp. 3-25,26)
328: */
329: register SSTAT2 {
330: address 0x00d
331: access_mode RO
332: field OVERRUN 0x80
333: field SHVALID 0x40 /* Shadow Layer non-zero */
334: field EXP_ACTIVE 0x10 /* SCSI Expander Active */
335: field CRCVALERR 0x08 /* CRC doesn't match (U3 only) */
336: field CRCENDERR 0x04 /* No terminal CRC packet (U3 only) */
337: field CRCREQERR 0x02 /* Illegal CRC packet req (U3 only) */
338: field DUAL_EDGE_ERR 0x01 /* Incorrect data phase (U3 only) */
339: mask SFCNT 0x1f
340: }
341:
342: /*
343: * SCSI Status 3 (p. 3-26)
344: */
345: register SSTAT3 {
346: address 0x00e
347: access_mode RO
348: mask SCSICNT 0xf0
349: mask OFFCNT 0x0f
350: mask U2OFFCNT 0x7f
351: }
352:
353: /*
354: * SCSI ID for the aic7890/91 chips
355: */
356: register SCSIID_ULTRA2 {
357: address 0x00f
358: access_mode RW
359: mask TID 0xf0 /* Target ID mask */
360: mask OID 0x0f /* Our ID mask */
361: }
362:
363: /*
364: * SCSI Interrupt Mode 1 (p. 3-28)
365: * Setting any bit will enable the corresponding function
366: * in SIMODE0 to interrupt via the IRQ pin.
367: */
368: register SIMODE0 {
369: address 0x010
370: access_mode RW
371: field ENSELDO 0x40
372: field ENSELDI 0x20
373: field ENSELINGO 0x10
374: field ENSWRAP 0x08
375: field ENIOERR 0x08 /* LVD Tranceiver mode changes */
376: field ENSDONE 0x04
377: field ENSPIORDY 0x02
378: field ENDMADONE 0x01
379: }
380:
381: /*
382: * SCSI Interrupt Mode 1 (pp. 3-28,29)
383: * Setting any bit will enable the corresponding function
384: * in SIMODE1 to interrupt via the IRQ pin.
385: */
386: register SIMODE1 {
387: address 0x011
388: access_mode RW
389: field ENSELTIMO 0x80
390: field ENATNTARG 0x40
391: field ENSCSIRST 0x20
392: field ENPHASEMIS 0x10
393: field ENBUSFREE 0x08
394: field ENSCSIPERR 0x04
395: field ENPHASECHG 0x02
396: field ENREQINIT 0x01
397: }
398:
399: /*
400: * SCSI Data Bus (High) (p. 3-29)
401: * This register reads data on the SCSI Data bus directly.
402: */
403: register SCSIBUSL {
404: address 0x012
405: access_mode RW
406: }
407:
408: register SCSIBUSH {
409: address 0x013
410: access_mode RW
411: }
412:
413: /*
414: * SCSI/Host Address (p. 3-30)
415: * These registers hold the host address for the byte about to be
416: * transferred on the SCSI bus. They are counted up in the same
417: * manner as STCNT is counted down. SHADDR should always be used
418: * to determine the address of the last byte transferred since HADDR
419: * can be skewed by write ahead.
420: */
421: register SHADDR {
422: address 0x014
423: size 4
424: access_mode RO
425: }
426:
427: /*
428: * Selection Timeout Timer (p. 3-30)
429: */
430: register SELTIMER {
431: address 0x018
432: access_mode RW
433: field STAGE6 0x20
434: field STAGE5 0x10
435: field STAGE4 0x08
436: field STAGE3 0x04
437: field STAGE2 0x02
438: field STAGE1 0x01
439: alias TARGIDIN
440: }
441:
442: /*
443: * Selection/Reselection ID (p. 3-31)
444: * Upper four bits are the device id. The ONEBIT is set when the re/selecting
445: * device did not set its own ID.
446: */
447: register SELID {
448: address 0x019
449: access_mode RW
450: mask SELID_MASK 0xf0
451: field ONEBIT 0x08
452: }
453:
454: register SCAMCTL {
455: address 0x01a
456: access_mode RW
457: field ENSCAMSELO 0x80
458: field CLRSCAMSELID 0x40
459: field ALTSTIM 0x20
460: field DFLTTID 0x10
461: mask SCAMLVL 0x03
462: }
463:
464: /*
465: * Target Mode Selecting in ID bitmask (aic7890/91/96/97)
466: */
467: register TARGID {
468: address 0x01b
469: size 2
470: access_mode RW
471: }
472:
473: /*
474: * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book)
475: * Indicates if external logic has been attached to the chip to
476: * perform the tasks of accessing a serial eeprom, testing termination
477: * strength, and performing cable detection. On the aic7860, most of
478: * these features are handled on chip, but on the aic7855 an attached
479: * aic3800 does the grunt work.
480: */
481: register SPIOCAP {
482: address 0x01b
483: access_mode RW
484: field SOFT1 0x80
485: field SOFT0 0x40
486: field SOFTCMDEN 0x20
487: field EXT_BRDCTL 0x10 /* External Board control */
488: field SEEPROM 0x08 /* External serial eeprom logic */
489: field EEPROM 0x04 /* Writable external BIOS ROM */
490: field ROM 0x02 /* Logic for accessing external ROM */
491: field SSPIOCPS 0x01 /* Termination and cable detection */
492: }
493:
494: register BRDCTL {
495: address 0x01d
496: field BRDDAT7 0x80
497: field BRDDAT6 0x40
498: field BRDDAT5 0x20
499: field BRDSTB 0x10
500: field BRDCS 0x08
501: field BRDRW 0x04
502: field BRDCTL1 0x02
503: field BRDCTL0 0x01
504: /* 7890 Definitions */
505: field BRDDAT4 0x10
506: field BRDDAT3 0x08
507: field BRDDAT2 0x04
508: field BRDRW_ULTRA2 0x02
509: field BRDSTB_ULTRA2 0x01
510: }
511:
512: /*
513: * Serial EEPROM Control (p. 4-92 in 7870 Databook)
514: * Controls the reading and writing of an external serial 1-bit
515: * EEPROM Device. In order to access the serial EEPROM, you must
516: * first set the SEEMS bit that generates a request to the memory
517: * port for access to the serial EEPROM device. When the memory
518: * port is not busy servicing another request, it reconfigures
519: * to allow access to the serial EEPROM. When this happens, SEERDY
520: * gets set high to verify that the memory port access has been
521: * granted.
522: *
523: * After successful arbitration for the memory port, the SEECS bit of
524: * the SEECTL register is connected to the chip select. The SEECK,
525: * SEEDO, and SEEDI are connected to the clock, data out, and data in
526: * lines respectively. The SEERDY bit of SEECTL is useful in that it
527: * gives us an 800 nsec timer. After a write to the SEECTL register,
528: * the SEERDY goes high 800 nsec later. The one exception to this is
529: * when we first request access to the memory port. The SEERDY goes
530: * high to signify that access has been granted and, for this case, has
531: * no implied timing.
532: *
533: * See 93cx6.c for detailed information on the protocol necessary to
534: * read the serial EEPROM.
535: */
536: register SEECTL {
537: address 0x01e
538: field EXTARBACK 0x80
539: field EXTARBREQ 0x40
540: field SEEMS 0x20
541: field SEERDY 0x10
542: field SEECS 0x08
543: field SEECK 0x04
544: field SEEDO 0x02
545: field SEEDI 0x01
546: }
547: /*
548: * SCSI Block Control (p. 3-32)
549: * Controls Bus type and channel selection. In a twin channel configuration
550: * addresses 0x00-0x1e are gated to the appropriate channel based on this
551: * register. SELWIDE allows for the coexistence of 8bit and 16bit devices
552: * on a wide bus.
553: */
554: register SBLKCTL {
555: address 0x01f
556: access_mode RW
557: field DIAGLEDEN 0x80 /* Aic78X0 only */
558: field DIAGLEDON 0x40 /* Aic78X0 only */
559: field AUTOFLUSHDIS 0x20
560: field SELBUSB 0x08
561: field ENAB40 0x08 /* LVD transceiver active */
562: field ENAB20 0x04 /* SE/HVD transceiver active */
563: field SELWIDE 0x02
564: field XCVR 0x01 /* External transceiver active */
565: }
566:
567: /*
568: * Sequencer Control (p. 3-33)
569: * Error detection mode and speed configuration
570: */
571: register SEQCTL {
572: address 0x060
573: access_mode RW
574: field PERRORDIS 0x80
575: field PAUSEDIS 0x40
576: field FAILDIS 0x20
577: field FASTMODE 0x10
578: field BRKADRINTEN 0x08
579: field STEP 0x04
580: field SEQRESET 0x02
581: field LOADRAM 0x01
582: }
583:
584: /*
585: * Sequencer RAM Data (p. 3-34)
586: * Single byte window into the Scratch Ram area starting at the address
587: * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write
588: * four bytes in succession. The SEQADDRs will increment after the most
589: * significant byte is written
590: */
591: register SEQRAM {
592: address 0x061
593: access_mode RW
594: }
595:
596: /*
597: * Sequencer Address Registers (p. 3-35)
598: * Only the first bit of SEQADDR1 holds addressing information
599: */
600: register SEQADDR0 {
601: address 0x062
602: access_mode RW
603: }
604:
605: register SEQADDR1 {
606: address 0x063
607: access_mode RW
608: mask SEQADDR1_MASK 0x01
609: }
610:
611: /*
612: * Accumulator
613: * We cheat by passing arguments in the Accumulator up to the kernel driver
614: */
615: register ACCUM {
616: address 0x064
617: access_mode RW
618: accumulator
619: }
620:
621: register SINDEX {
622: address 0x065
623: access_mode RW
624: sindex
625: }
626:
627: register DINDEX {
628: address 0x066
629: access_mode RW
630: }
631:
632: register ALLONES {
633: address 0x069
634: access_mode RO
635: allones
636: }
637:
638: register ALLZEROS {
639: address 0x06a
640: access_mode RO
641: allzeros
642: }
643:
644: register NONE {
645: address 0x06a
646: access_mode WO
647: none
648: }
649:
650: register FLAGS {
651: address 0x06b
652: access_mode RO
653: field ZERO 0x02
654: field CARRY 0x01
655: }
656:
657: register SINDIR {
658: address 0x06c
659: access_mode RO
660: }
661:
662: register DINDIR {
663: address 0x06d
664: access_mode WO
665: }
666:
667: register FUNCTION1 {
668: address 0x06e
669: access_mode RW
670: }
671:
672: register STACK {
673: address 0x06f
674: access_mode RO
675: }
676:
677: const STACK_SIZE 4
678:
679: /*
680: * Board Control (p. 3-43)
681: */
682: register BCTL {
683: address 0x084
684: access_mode RW
685: field ACE 0x08
686: field ENABLE 0x01
687: }
688:
689: /*
690: * On the aic78X0 chips, Board Control is replaced by the DSCommand
691: * register (p. 4-64)
692: */
693: register DSCOMMAND0 {
694: address 0x084
695: access_mode RW
696: field CACHETHEN 0x80 /* Cache Threshold enable */
697: field DPARCKEN 0x40 /* Data Parity Check Enable */
698: field MPARCKEN 0x20 /* Memory Parity Check Enable */
699: field EXTREQLCK 0x10 /* External Request Lock */
700: /* aic7890/91/96/97 only */
701: field INTSCBRAMSEL 0x08 /* Internal SCB RAM Select */
702: field RAMPS 0x04 /* External SCB RAM Present */
703: field USCBSIZE32 0x02 /* Use 32byte SCB Page Size */
704: field CIOPARCKEN 0x01 /* Internal bus parity error enable */
705: }
706:
707: register DSCOMMAND1 {
708: address 0x085
709: access_mode RW
710: mask DSLATT 0xfc /* PCI latency timer (non-ultra2) */
711: field HADDLDSEL1 0x02 /* Host Address Load Select Bits */
712: field HADDLDSEL0 0x01
713: }
714:
715: /*
716: * Bus On/Off Time (p. 3-44) aic7770 only
717: */
718: register BUSTIME {
719: address 0x085
720: access_mode RW
721: mask BOFF 0xf0
722: mask BON 0x0f
723: }
724:
725: /*
726: * Bus Speed (p. 3-45) aic7770 only
727: */
728: register BUSSPD {
729: address 0x086
730: access_mode RW
731: mask DFTHRSH 0xc0
732: mask STBOFF 0x38
733: mask STBON 0x07
734: mask DFTHRSH_100 0xc0
735: mask DFTHRSH_75 0x80
736: }
737:
738: /* aic7850/55/60/70/80/95 only */
739: register DSPCISTATUS {
740: address 0x086
741: mask DFTHRSH_100 0xc0
742: }
743:
744: /* aic7890/91/96/97 only */
745: register HS_MAILBOX {
746: address 0x086
747: mask HOST_MAILBOX 0xF0
748: mask SEQ_MAILBOX 0x0F
749: mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */
750: }
751:
752: const HOST_MAILBOX_SHIFT 4
753: const SEQ_MAILBOX_SHIFT 0
754:
755: /*
756: * Host Control (p. 3-47) R/W
757: * Overall host control of the device.
758: */
759: register HCNTRL {
760: address 0x087
761: access_mode RW
762: field POWRDN 0x40
763: field SWINT 0x10
764: field IRQMS 0x08
765: field PAUSE 0x04
766: field INTEN 0x02
767: field CHIPRST 0x01
768: field CHIPRSTACK 0x01
769: }
770:
771: /*
772: * Host Address (p. 3-48)
773: * This register contains the address of the byte about
774: * to be transferred across the host bus.
775: */
776: register HADDR {
777: address 0x088
778: size 4
779: access_mode RW
780: }
781:
782: register HCNT {
783: address 0x08c
784: size 3
785: access_mode RW
786: }
787:
788: /*
789: * SCB Pointer (p. 3-49)
790: * Gate one of the SCBs into the SCBARRAY window.
791: */
792: register SCBPTR {
793: address 0x090
794: access_mode RW
795: }
796:
797: /*
798: * Interrupt Status (p. 3-50)
799: * Status for system interrupts
800: */
801: register INTSTAT {
802: address 0x091
803: access_mode RW
804: field BRKADRINT 0x08
805: field SCSIINT 0x04
806: field CMDCMPLT 0x02
807: field SEQINT 0x01
808: mask BAD_PHASE SEQINT /* unknown scsi bus phase */
809: mask SEND_REJECT 0x10|SEQINT /* sending a message reject */
810: mask PROTO_VIOLATION 0x20|SEQINT /* SCSI protocol violation */
811: mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */
812: mask IGN_WIDE_RES 0x40|SEQINT /* Complex IGN Wide Res Msg */
813: mask PDATA_REINIT 0x50|SEQINT /*
814: * Returned to data phase
815: * that requires data
816: * transfer pointers to be
817: * recalculated from the
818: * transfer residual.
819: */
820: mask HOST_MSG_LOOP 0x60|SEQINT /*
821: * The bus is ready for the
822: * host to perform another
823: * message transaction. This
824: * mechanism is used for things
825: * like sync/wide negotiation
826: * that require a kernel based
827: * message state engine.
828: */
829: mask BAD_STATUS 0x70|SEQINT /* Bad status from target */
830: mask PERR_DETECTED 0x80|SEQINT /*
831: * Either the phase_lock
832: * or inb_next routine has
833: * noticed a parity error.
834: */
835: mask DATA_OVERRUN 0x90|SEQINT /*
836: * Target attempted to write
837: * beyond the bounds of its
838: * command.
839: */
840: mask MKMSG_FAILED 0xa0|SEQINT /*
841: * Target completed command
842: * without honoring our ATN
843: * request to issue a message.
844: */
845: mask MISSED_BUSFREE 0xb0|SEQINT /*
846: * The sequencer never saw
847: * the bus go free after
848: * either a command complete
849: * or disconnect message.
850: */
851: mask SCB_MISMATCH 0xc0|SEQINT /*
852: * Downloaded SCB's tag does
853: * not match the entry we
854: * intended to download.
855: */
856: mask NO_FREE_SCB 0xd0|SEQINT /*
857: * get_free_or_disc_scb failed.
858: */
859: mask OUT_OF_RANGE 0xe0|SEQINT
860:
861: mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */
862: mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT)
863: }
864:
865: /*
866: * Hard Error (p. 3-53)
867: * Reporting of catastrophic errors. You usually cannot recover from
868: * these without a full board reset.
869: */
870: register ERROR {
871: address 0x092
872: access_mode RO
873: field CIOPARERR 0x80 /* Ultra2 only */
874: field PCIERRSTAT 0x40 /* PCI only */
875: field MPARERR 0x20 /* PCI only */
876: field DPARERR 0x10 /* PCI only */
877: field SQPARERR 0x08
878: field ILLOPCODE 0x04
879: field ILLSADDR 0x02
880: field ILLHADDR 0x01
881: }
882:
883: /*
884: * Clear Interrupt Status (p. 3-52)
885: */
886: register CLRINT {
887: address 0x092
888: access_mode WO
889: field CLRPARERR 0x10 /* PCI only */
890: field CLRBRKADRINT 0x08
891: field CLRSCSIINT 0x04
892: field CLRCMDINT 0x02
893: field CLRSEQINT 0x01
894: }
895:
896: register DFCNTRL {
897: address 0x093
898: access_mode RW
899: field PRELOADEN 0x80 /* aic7890 only */
900: field WIDEODD 0x40
901: field SCSIEN 0x20
902: field SDMAEN 0x10
903: field SDMAENACK 0x10
904: field HDMAEN 0x08
905: field HDMAENACK 0x08
906: field DIRECTION 0x04
907: field FIFOFLUSH 0x02
908: field FIFORESET 0x01
909: }
910:
911: register DFSTATUS {
912: address 0x094
913: access_mode RO
914: field PRELOAD_AVAIL 0x80
915: field DFCACHETH 0x40
916: field FIFOQWDEMP 0x20
917: field MREQPEND 0x10
918: field HDONE 0x08
919: field DFTHRESH 0x04
920: field FIFOFULL 0x02
921: field FIFOEMP 0x01
922: }
923:
924: register DFWADDR {
925: address 0x95
926: access_mode RW
927: }
928:
929: register DFRADDR {
930: address 0x97
931: access_mode RW
932: }
933:
934: register DFDAT {
935: address 0x099
936: access_mode RW
937: }
938:
939: /*
940: * SCB Auto Increment (p. 3-59)
941: * Byte offset into the SCB Array and an optional bit to allow auto
942: * incrementing of the address during download and upload operations
943: */
944: register SCBCNT {
945: address 0x09a
946: access_mode RW
947: field SCBAUTO 0x80
948: mask SCBCNT_MASK 0x1f
949: }
950:
951: /*
952: * Queue In FIFO (p. 3-60)
953: * Input queue for queued SCBs (commands that the sequencer has yet to start)
954: */
955: register QINFIFO {
956: address 0x09b
957: access_mode RW
958: }
959:
960: /*
961: * Queue In Count (p. 3-60)
962: * Number of queued SCBs
963: */
964: register QINCNT {
965: address 0x09c
966: access_mode RO
967: }
968:
969: /*
970: * Queue Out FIFO (p. 3-61)
971: * Queue of SCBs that have completed and await the host
972: */
973: register QOUTFIFO {
974: address 0x09d
975: access_mode WO
976: }
977:
978: register CRCCONTROL1 {
979: address 0x09d
980: access_mode RW
981: field CRCONSEEN 0x80
982: field CRCVALCHKEN 0x40
983: field CRCENDCHKEN 0x20
984: field CRCREQCHKEN 0x10
985: field TARGCRCENDEN 0x08
986: field TARGCRCCNTEN 0x04
987: }
988:
989:
990: /*
991: * Queue Out Count (p. 3-61)
992: * Number of queued SCBs in the Out FIFO
993: */
994: register QOUTCNT {
995: address 0x09e
996: access_mode RO
997: }
998:
999: register SCSIPHASE {
1000: address 0x09e
1001: access_mode RO
1002: field STATUS_PHASE 0x20
1003: field COMMAND_PHASE 0x10
1004: field MSG_IN_PHASE 0x08
1005: field MSG_OUT_PHASE 0x04
1006: field DATA_IN_PHASE 0x02
1007: field DATA_OUT_PHASE 0x01
1008: mask DATA_PHASE_MASK 0x03
1009: }
1010:
1011: /*
1012: * Special Function
1013: */
1014: register SFUNCT {
1015: address 0x09f
1016: access_mode RW
1017: field ALT_MODE 0x80
1018: }
1019:
1020: /*
1021: * SCB Definition (p. 5-4)
1022: */
1023: scb {
1024: address 0x0a0
1025: size 64
1026:
1027: SCB_CDB_PTR {
1028: size 4
1029: alias SCB_RESIDUAL_DATACNT
1030: alias SCB_CDB_STORE
1031: }
1032: SCB_RESIDUAL_SGPTR {
1033: size 4
1034: }
1035: SCB_SCSI_STATUS {
1036: size 1
1037: }
1038: SCB_TARGET_PHASES {
1039: size 1
1040: }
1041: SCB_TARGET_DATA_DIR {
1042: size 1
1043: }
1044: SCB_TARGET_ITAG {
1045: size 1
1046: }
1047: SCB_DATAPTR {
1048: size 4
1049: }
1050: SCB_DATACNT {
1051: /*
1052: * The last byte is really the high address bits for
1053: * the data address.
1054: */
1055: size 4
1056: field SG_LAST_SEG 0x80 /* In the fourth byte */
1057: mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */
1058: }
1059: SCB_SGPTR {
1060: size 4
1061: field SG_RESID_VALID 0x04 /* In the first byte */
1062: field SG_FULL_RESID 0x02 /* In the first byte */
1063: field SG_LIST_NULL 0x01 /* In the first byte */
1064: }
1065: SCB_CONTROL {
1066: size 1
1067: field TARGET_SCB 0x80
1068: field STATUS_RCVD 0x80
1069: field DISCENB 0x40
1070: field TAG_ENB 0x20
1071: field MK_MESSAGE 0x10
1072: field ULTRAENB 0x08
1073: field DISCONNECTED 0x04
1074: mask SCB_TAG_TYPE 0x03
1075: }
1076: SCB_SCSIID {
1077: size 1
1078: field TWIN_CHNLB 0x80
1079: mask TWIN_TID 0x70
1080: mask TID 0xf0
1081: mask OID 0x0f
1082: }
1083: SCB_LUN {
1084: field SCB_XFERLEN_ODD 0x80
1085: mask LID 0x3f
1086: size 1
1087: }
1088: SCB_TAG {
1089: size 1
1090: }
1091: SCB_CDB_LEN {
1092: size 1
1093: }
1094: SCB_SCSIRATE {
1095: size 1
1096: }
1097: SCB_SCSIOFFSET {
1098: size 1
1099: }
1100: SCB_NEXT {
1101: size 1
1102: }
1103: SCB_64_SPARE {
1104: size 16
1105: }
1106: SCB_64_BTT {
1107: size 16
1108: }
1109: }
1110:
1111: const SCB_UPLOAD_SIZE 32
1112: const SCB_DOWNLOAD_SIZE 32
1113: const SCB_DOWNLOAD_SIZE_64 48
1114:
1115: const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */
1116:
1117: /* --------------------- AHA-2840-only definitions -------------------- */
1118:
1119: register SEECTL_2840 {
1120: address 0x0c0
1121: access_mode RW
1122: field CS_2840 0x04
1123: field CK_2840 0x02
1124: field DO_2840 0x01
1125: }
1126:
1127: register STATUS_2840 {
1128: address 0x0c1
1129: access_mode RW
1130: field EEPROM_TF 0x80
1131: mask BIOS_SEL 0x60
1132: mask ADSEL 0x1e
1133: field DI_2840 0x01
1134: }
1135:
1136: /* --------------------- AIC-7870-only definitions -------------------- */
1137:
1138: register CCHADDR {
1139: address 0x0E0
1140: size 8
1141: }
1142:
1143: register CCHCNT {
1144: address 0x0E8
1145: }
1146:
1147: register CCSGRAM {
1148: address 0x0E9
1149: }
1150:
1151: register CCSGADDR {
1152: address 0x0EA
1153: }
1154:
1155: register CCSGCTL {
1156: address 0x0EB
1157: field CCSGDONE 0x80
1158: field CCSGEN 0x08
1159: field SG_FETCH_NEEDED 0x02 /* Bit used for software state */
1160: field CCSGRESET 0x01
1161: }
1162:
1163: register CCSCBCNT {
1164: address 0xEF
1165: }
1166:
1167: register CCSCBCTL {
1168: address 0x0EE
1169: field CCSCBDONE 0x80
1170: field ARRDONE 0x40 /* SCB Array prefetch done */
1171: field CCARREN 0x10
1172: field CCSCBEN 0x08
1173: field CCSCBDIR 0x04
1174: field CCSCBRESET 0x01
1175: }
1176:
1177: register CCSCBADDR {
1178: address 0x0ED
1179: }
1180:
1181: register CCSCBRAM {
1182: address 0xEC
1183: }
1184:
1185: /*
1186: * SCB bank address (7895/7896/97 only)
1187: */
1188: register SCBBADDR {
1189: address 0x0F0
1190: access_mode RW
1191: }
1192:
1193: register CCSCBPTR {
1194: address 0x0F1
1195: }
1196:
1197: register HNSCB_QOFF {
1198: address 0x0F4
1199: }
1200:
1201: register SNSCB_QOFF {
1202: address 0x0F6
1203: }
1204:
1205: register SDSCB_QOFF {
1206: address 0x0F8
1207: }
1208:
1209: register QOFF_CTLSTA {
1210: address 0x0FA
1211: field SCB_AVAIL 0x40
1212: field SNSCB_ROLLOVER 0x20
1213: field SDSCB_ROLLOVER 0x10
1214: mask SCB_QSIZE 0x07
1215: mask SCB_QSIZE_256 0x06
1216: }
1217:
1218: register DFF_THRSH {
1219: address 0x0FB
1220: mask WR_DFTHRSH 0x70
1221: mask RD_DFTHRSH 0x07
1222: mask RD_DFTHRSH_MIN 0x00
1223: mask RD_DFTHRSH_25 0x01
1224: mask RD_DFTHRSH_50 0x02
1225: mask RD_DFTHRSH_63 0x03
1226: mask RD_DFTHRSH_75 0x04
1227: mask RD_DFTHRSH_85 0x05
1228: mask RD_DFTHRSH_90 0x06
1229: mask RD_DFTHRSH_MAX 0x07
1230: mask WR_DFTHRSH_MIN 0x00
1231: mask WR_DFTHRSH_25 0x10
1232: mask WR_DFTHRSH_50 0x20
1233: mask WR_DFTHRSH_63 0x30
1234: mask WR_DFTHRSH_75 0x40
1235: mask WR_DFTHRSH_85 0x50
1236: mask WR_DFTHRSH_90 0x60
1237: mask WR_DFTHRSH_MAX 0x70
1238: }
1239:
1240: register SG_CACHE_PRE {
1241: access_mode WO
1242: address 0x0fc
1243: mask SG_ADDR_MASK 0xf8
1244: field LAST_SEG 0x02
1245: field LAST_SEG_DONE 0x01
1246: }
1247:
1248: register SG_CACHE_SHADOW {
1249: access_mode RO
1250: address 0x0fc
1251: mask SG_ADDR_MASK 0xf8
1252: field LAST_SEG 0x02
1253: field LAST_SEG_DONE 0x01
1254: }
1255: /* ---------------------- Scratch RAM Offsets ------------------------- */
1256: /* These offsets are either to values that are initialized by the board's
1257: * BIOS or are specified by the sequencer code.
1258: *
1259: * The host adapter card (at least the BIOS) uses 20-2f for SCSI
1260: * device information, 32-33 and 5a-5f as well. As it turns out, the
1261: * BIOS trashes 20-2f, writing the synchronous negotiation results
1262: * on top of the BIOS values, so we re-use those for our per-target
1263: * scratchspace (actually a value that can be copied directly into
1264: * SCSIRATE). The kernel driver will enable synchronous negotiation
1265: * for all targets that have a value other than 0 in the lower four
1266: * bits of the target scratch space. This should work regardless of
1267: * whether the bios has been installed.
1268: */
1269:
1270: scratch_ram {
1271: address 0x020
1272: size 58
1273:
1274: /*
1275: * 1 byte per target starting at this address for configuration values
1276: */
1277: BUSY_TARGETS {
1278: alias TARG_SCSIRATE
1279: size 16
1280: }
1281: /*
1282: * Bit vector of targets that have ULTRA enabled as set by
1283: * the BIOS. The Sequencer relies on a per-SCB field to
1284: * control whether to enable Ultra transfers or not. During
1285: * initialization, we read this field and reuse it for 2
1286: * entries in the busy target table.
1287: */
1288: ULTRA_ENB {
1289: alias CMDSIZE_TABLE
1290: size 2
1291: }
1292: /*
1293: * Bit vector of targets that have disconnection disabled as set by
1294: * the BIOS. The Sequencer relies in a per-SCB field to control the
1295: * disconnect priveldge. During initialization, we read this field
1296: * and reuse it for 2 entries in the busy target table.
1297: */
1298: DISC_DSB {
1299: size 2
1300: }
1301: CMDSIZE_TABLE_TAIL {
1302: size 4
1303: }
1304: /*
1305: * Partial transfer past cacheline end to be
1306: * transferred using an extra S/G.
1307: */
1308: MWI_RESIDUAL {
1309: size 1
1310: }
1311: /*
1312: * SCBID of the next SCB to be started by the controller.
1313: */
1314: NEXT_QUEUED_SCB {
1315: size 1
1316: }
1317: /*
1318: * Single byte buffer used to designate the type or message
1319: * to send to a target.
1320: */
1321: MSG_OUT {
1322: size 1
1323: }
1324: /* Parameters for DMA Logic */
1325: DMAPARAMS {
1326: size 1
1327: field PRELOADEN 0x80
1328: field WIDEODD 0x40
1329: field SCSIEN 0x20
1330: field SDMAEN 0x10
1331: field SDMAENACK 0x10
1332: field HDMAEN 0x08
1333: field HDMAENACK 0x08
1334: field DIRECTION 0x04 /* Set indicates PCI->SCSI */
1335: field FIFOFLUSH 0x02
1336: field FIFORESET 0x01
1337: }
1338: SEQ_FLAGS {
1339: size 1
1340: field NOT_IDENTIFIED 0x80
1341: field NO_CDB_SENT 0x40
1342: field TARGET_CMD_IS_TAGGED 0x40
1343: field DPHASE 0x20
1344: /* Target flags */
1345: field TARG_CMD_PENDING 0x10
1346: field CMDPHASE_PENDING 0x08
1347: field DPHASE_PENDING 0x04
1348: field SPHASE_PENDING 0x02
1349: field NO_DISCONNECT 0x01
1350: }
1351: /*
1352: * Temporary storage for the
1353: * target/channel/lun of a
1354: * reconnecting target
1355: */
1356: SAVED_SCSIID {
1357: size 1
1358: }
1359: SAVED_LUN {
1360: size 1
1361: }
1362: /*
1363: * The last bus phase as seen by the sequencer.
1364: */
1365: LASTPHASE {
1366: size 1
1367: field CDI 0x80
1368: field IOI 0x40
1369: field MSGI 0x20
1370: mask PHASE_MASK CDI|IOI|MSGI
1371: mask P_DATAOUT 0x00
1372: mask P_DATAIN IOI
1373: mask P_COMMAND CDI
1374: mask P_MESGOUT CDI|MSGI
1375: mask P_STATUS CDI|IOI
1376: mask P_MESGIN CDI|IOI|MSGI
1377: mask P_BUSFREE 0x01
1378: }
1379: /*
1380: * head of list of SCBs awaiting
1381: * selection
1382: */
1383: WAITING_SCBH {
1384: size 1
1385: }
1386: /*
1387: * head of list of SCBs that are
1388: * disconnected. Used for SCB
1389: * paging.
1390: */
1391: DISCONNECTED_SCBH {
1392: size 1
1393: }
1394: /*
1395: * head of list of SCBs that are
1396: * not in use. Used for SCB paging.
1397: */
1398: FREE_SCBH {
1399: size 1
1400: }
1401: /*
1402: * head of list of SCBs that have
1403: * completed but have not been
1404: * put into the qoutfifo.
1405: */
1406: COMPLETE_SCBH {
1407: size 1
1408: }
1409: /*
1410: * Address of the hardware scb array in the host.
1411: */
1412: HSCB_ADDR {
1413: size 4
1414: }
1415: /*
1416: * Base address of our shared data with the kernel driver in host
1417: * memory. This includes the qoutfifo and target mode
1418: * incoming command queue.
1419: */
1420: SHARED_DATA_ADDR {
1421: size 4
1422: }
1423: KERNEL_QINPOS {
1424: size 1
1425: }
1426: QINPOS {
1427: size 1
1428: }
1429: QOUTPOS {
1430: size 1
1431: }
1432: /*
1433: * Kernel and sequencer offsets into the queue of
1434: * incoming target mode command descriptors. The
1435: * queue is full when the KERNEL_TQINPOS == TQINPOS.
1436: */
1437: KERNEL_TQINPOS {
1438: size 1
1439: }
1440: TQINPOS {
1441: size 1
1442: }
1443: ARG_1 {
1444: size 1
1445: mask SEND_MSG 0x80
1446: mask SEND_SENSE 0x40
1447: mask SEND_REJ 0x20
1448: mask MSGOUT_PHASEMIS 0x10
1449: mask EXIT_MSG_LOOP 0x08
1450: mask CONT_MSG_LOOP 0x04
1451: mask CONT_TARG_SESSION 0x02
1452: alias RETURN_1
1453: }
1454: ARG_2 {
1455: size 1
1456: alias RETURN_2
1457: }
1458:
1459: /*
1460: * Snapshot of MSG_OUT taken after each message is sent.
1461: */
1462: LAST_MSG {
1463: size 1
1464: alias TARG_IMMEDIATE_SCB
1465: }
1466:
1467: /*
1468: * Sequences the kernel driver has okayed for us. This allows
1469: * the driver to do things like prevent initiator or target
1470: * operations.
1471: */
1472: SCSISEQ_TEMPLATE {
1473: size 1
1474: field ENSELO 0x40
1475: field ENSELI 0x20
1476: field ENRSELI 0x10
1477: field ENAUTOATNO 0x08
1478: field ENAUTOATNI 0x04
1479: field ENAUTOATNP 0x02
1480: }
1481: }
1482:
1483: scratch_ram {
1484: address 0x056
1485: size 4
1486: /*
1487: * These scratch ram locations are initialized by the 274X BIOS.
1488: * We reuse them after capturing the BIOS settings during
1489: * initialization.
1490: */
1491:
1492: /*
1493: * The initiator specified tag for this target mode transaction.
1494: */
1495: HA_274_BIOSGLOBAL {
1496: size 1
1497: field HA_274_EXTENDED_TRANS 0x01
1498: alias INITIATOR_TAG
1499: }
1500:
1501: SEQ_FLAGS2 {
1502: size 1
1503: field SCB_DMA 0x01
1504: field TARGET_MSG_PENDING 0x02
1505: }
1506: }
1507:
1508: scratch_ram {
1509: address 0x05a
1510: size 6
1511: /*
1512: * These are reserved registers in the card's scratch ram on the 2742.
1513: * The EISA configuraiton chip is mapped here. On Rev E. of the
1514: * aic7770, the sequencer can use this area for scratch, but the
1515: * host cannot directly access these registers. On later chips, this
1516: * area can be read and written by both the host and the sequencer.
1517: * Even on later chips, many of these locations are initialized by
1518: * the BIOS.
1519: */
1520: SCSICONF {
1521: size 1
1522: field TERM_ENB 0x80
1523: field RESET_SCSI 0x40
1524: field ENSPCHK 0x20
1525: mask HSCSIID 0x07 /* our SCSI ID */
1526: mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */
1527: }
1528: INTDEF {
1529: address 0x05c
1530: size 1
1531: field EDGE_TRIG 0x80
1532: mask VECTOR 0x0f
1533: }
1534: HOSTCONF {
1535: address 0x05d
1536: size 1
1537: }
1538: HA_274_BIOSCTRL {
1539: address 0x05f
1540: size 1
1541: mask BIOSMODE 0x30
1542: mask BIOSDISABLED 0x30
1543: field CHANNEL_B_PRIMARY 0x08
1544: }
1545: }
1546:
1547: scratch_ram {
1548: address 0x070
1549: size 16
1550:
1551: /*
1552: * Per target SCSI offset values for Ultra2 controllers.
1553: */
1554: TARG_OFFSET {
1555: size 16
1556: }
1557: }
1558:
1559: const TID_SHIFT 4
1560: const SCB_LIST_NULL 0xff
1561: const TARGET_CMD_CMPLT 0xfe
1562:
1563: const CCSGADDR_MAX 0x80
1564: const CCSGRAM_MAXSEGS 16
1565:
1566: /* WDTR Message values */
1567: const BUS_8_BIT 0x00
1568: const BUS_16_BIT 0x01
1569: const BUS_32_BIT 0x02
1570:
1571: /* Offset maximums */
1572: const MAX_OFFSET_8BIT 0x0f
1573: const MAX_OFFSET_16BIT 0x08
1574: const MAX_OFFSET_ULTRA2 0x7f
1575: const MAX_OFFSET 0x7f
1576: const HOST_MSG 0xff
1577:
1578: /* Target mode command processing constants */
1579: const CMD_GROUP_CODE_SHIFT 0x05
1580:
1581: const STATUS_BUSY 0x08
1582: const STATUS_QUEUE_FULL 0x28
1583: const TARGET_DATA_IN 1
1584:
1585: /*
1586: * Downloaded (kernel inserted) constants
1587: */
1588: /* Offsets into the SCBID array where different data is stored */
1589: const QOUTFIFO_OFFSET download
1590: const QINFIFO_OFFSET download
1591: const CACHESIZE_MASK download
1592: const INVERTED_CACHESIZE_MASK download
1593: const SG_PREFETCH_CNT download
1594: const SG_PREFETCH_ALIGN_MASK download
1595: const SG_PREFETCH_ADDR_MASK download