Annotation of sys/dev/microcode/aic7xxx/aic79xx.seq, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: aic79xx.seq,v 1.8 2007/05/26 00:36:03 krw Exp $ */
2: /*
3: * Adaptec U320 device driver firmware for Linux and FreeBSD.
4: *
5: * Copyright (c) 1994-2001, 2004 Justin T. Gibbs.
6: * Copyright (c) 2000-2002 Adaptec Inc.
7: * All rights reserved.
8: *
9: * Redistribution and use in source and binary forms, with or without
10: * modification, are permitted provided that the following conditions
11: * are met:
12: * 1. Redistributions of source code must retain the above copyright
13: * notice, this list of conditions, and the following disclaimer,
14: * without modification.
15: * 2. Redistributions in binary form must reproduce at minimum a disclaimer
16: * substantially similar to the "NO WARRANTY" disclaimer below
17: * ("Disclaimer") and any redistribution must be conditioned upon
18: * including a substantially similar Disclaimer requirement for further
19: * binary redistribution.
20: * 3. Neither the names of the above-listed copyright holders nor the names
21: * of any contributors may be used to endorse or promote products derived
22: * from this software without specific prior written permission.
23: *
24: * Alternatively, this software may be distributed under the terms of the
25: * GNU General Public License ("GPL") version 2 as published by the Free
26: * Software Foundation.
27: *
28: * NO WARRANTY
29: * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30: * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31: * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
32: * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33: * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
37: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
38: * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39: * POSSIBILITY OF SUCH DAMAGES.
40: *
41: * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.seq,v 1.17 2004/08/04 17:55:34 gibbs Exp $
42: */
43:
44: VERSION = "$Id: aic79xx.seq,v 1.8 2007/05/26 00:36:03 krw Exp $"
45: PATCH_ARG_LIST = "struct ahd_softc *ahd"
46: PREFIX = "ahd_"
47:
48: #include <dev/microcode/aic7xxx/aic79xx.reg>
49: #include <scsi/scsi_message.h>
50:
51: restart:
52: if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
53: test SEQINTCODE, 0xFF jz idle_loop;
54: SET_SEQINTCODE(NO_SEQINT)
55: }
56:
57: idle_loop:
58:
59: if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
60: /*
61: * Convert ERROR status into a sequencer
62: * interrupt to handle the case of an
63: * interrupt collision on the hardware
64: * setting of HWERR.
65: */
66: test ERROR, 0xFF jz no_error_set;
67: SET_SEQINTCODE(SAW_HWERR)
68: no_error_set:
69: }
70: SET_MODE(M_SCSI, M_SCSI)
71: test SCSISEQ0, ENSELO|ENARBO jnz idle_loop_checkbus;
72: test SEQ_FLAGS2, SELECTOUT_QFROZEN jz check_waiting_list;
73: /*
74: * If the kernel has caught up with us, thaw the queue.
75: */
76: mov A, KERNEL_QFREEZE_COUNT;
77: cmp QFREEZE_COUNT, A jne check_frozen_completions;
78: mov A, KERNEL_QFREEZE_COUNT[1];
79: cmp QFREEZE_COUNT[1], A jne check_frozen_completions;
80: and SEQ_FLAGS2, ~SELECTOUT_QFROZEN;
81: jmp check_waiting_list;
82: check_frozen_completions:
83: test SSTAT0, SELDO|SELINGO jnz idle_loop_checkbus;
84: BEGIN_CRITICAL;
85: /*
86: * If we have completions stalled waiting for the qfreeze
87: * to take effect, move them over to the complete_scb list
88: * now that no selections are pending.
89: */
90: cmp COMPLETE_ON_QFREEZE_HEAD[1],SCB_LIST_NULL je idle_loop_checkbus;
91: /*
92: * Find the end of the qfreeze list. The first element has
93: * to be treated specially.
94: */
95: bmov SCBPTR, COMPLETE_ON_QFREEZE_HEAD, 2;
96: cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL je join_lists;
97: /*
98: * Now the normal loop.
99: */
100: bmov SCBPTR, SCB_NEXT_COMPLETE, 2;
101: cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL jne . - 1;
102: join_lists:
103: bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
104: bmov COMPLETE_SCB_HEAD, COMPLETE_ON_QFREEZE_HEAD, 2;
105: mvi COMPLETE_ON_QFREEZE_HEAD[1], SCB_LIST_NULL;
106: jmp idle_loop_checkbus;
107: check_waiting_list:
108: cmp WAITING_TID_HEAD[1], SCB_LIST_NULL je idle_loop_checkbus;
109: /*
110: * ENSELO is cleared by a SELDO, so we must test for SELDO
111: * one last time.
112: */
113: test SSTAT0, SELDO jnz select_out;
114: call start_selection;
115: idle_loop_checkbus:
116: test SSTAT0, SELDO jnz select_out;
117: END_CRITICAL;
118: test SSTAT0, SELDI jnz select_in;
119: test SCSIPHASE, ~DATA_PHASE_MASK jz idle_loop_check_nonpackreq;
120: test SCSISIGO, ATNO jz idle_loop_check_nonpackreq;
121: call unexpected_nonpkt_phase_find_ctxt;
122: idle_loop_check_nonpackreq:
123: test SSTAT2, NONPACKREQ jz . + 2;
124: call unexpected_nonpkt_phase_find_ctxt;
125: if ((ahd->bugs & AHD_FAINT_LED_BUG) != 0) {
126: /*
127: * On Rev A. hardware, the busy LED is only
128: * turned on automatically during selections
129: * and re-selections. Make the LED status
130: * more useful by forcing it to be on so
131: * long as one of our data FIFOs is active.
132: */
133: and A, FIFO0FREE|FIFO1FREE, DFFSTAT;
134: cmp A, FIFO0FREE|FIFO1FREE jne . + 3;
135: and SBLKCTL, ~DIAGLEDEN|DIAGLEDON;
136: jmp . + 2;
137: or SBLKCTL, DIAGLEDEN|DIAGLEDON;
138: }
139: call idle_loop_gsfifo_in_scsi_mode;
140: call idle_loop_service_fifos;
141: call idle_loop_cchan;
142: jmp idle_loop;
143:
144: idle_loop_gsfifo:
145: SET_MODE(M_SCSI, M_SCSI)
146: BEGIN_CRITICAL;
147: idle_loop_gsfifo_in_scsi_mode:
148: test LQISTAT2, LQIGSAVAIL jz return;
149: /*
150: * We have received good status for this transaction. There may
151: * still be data in our FIFOs draining to the host. Complete
152: * the SCB only if all data has transferred to the host.
153: */
154: good_status_IU_done:
155: bmov SCBPTR, GSFIFO, 2;
156: clr SCB_SCSI_STATUS;
157: /*
158: * If a command completed before an attempted task management
159: * function completed, notify the host after disabling any
160: * pending select-outs.
161: */
162: test SCB_TASK_MANAGEMENT, 0xFF jz gsfifo_complete_normally;
163: test SSTAT0, SELDO|SELINGO jnz . + 2;
164: and SCSISEQ0, ~ENSELO;
165: SET_SEQINTCODE(TASKMGMT_CMD_CMPLT_OKAY)
166: gsfifo_complete_normally:
167: or SCB_CONTROL, STATUS_RCVD;
168:
169: /*
170: * Since this status did not consume a FIFO, we have to
171: * be a bit more diligent in how we check for FIFOs pertaining
172: * to this transaction. There are two states that a FIFO still
173: * transferring data may be in.
174: *
175: * 1) Configured and draining to the host, with a FIFO handler.
176: * 2) Pending cfg4data, fifo not empty.
177: *
178: * Case 1 can be detected by noticing a non-zero FIFO active
179: * count in the SCB. In this case, we allow the routine servicing
180: * the FIFO to complete the SCB.
181: *
182: * Case 2 implies either a pending or yet to occur save data
183: * pointers for this same context in the other FIFO. So, if
184: * we detect case 1, we will properly defer the post of the SCB
185: * and achieve the desired result. The pending cfg4data will
186: * notice that status has been received and complete the SCB.
187: */
188: test SCB_FIFO_USE_COUNT, 0xFF jnz idle_loop_gsfifo_in_scsi_mode;
189: call complete;
190: END_CRITICAL;
191: jmp idle_loop_gsfifo_in_scsi_mode;
192:
193: idle_loop_service_fifos:
194: SET_MODE(M_DFF0, M_DFF0)
195: BEGIN_CRITICAL;
196: test LONGJMP_ADDR[1], INVALID_ADDR jnz idle_loop_next_fifo;
197: call longjmp;
198: END_CRITICAL;
199: idle_loop_next_fifo:
200: SET_MODE(M_DFF1, M_DFF1)
201: BEGIN_CRITICAL;
202: test LONGJMP_ADDR[1], INVALID_ADDR jz longjmp;
203: END_CRITICAL;
204: return:
205: ret;
206:
207: idle_loop_cchan:
208: SET_MODE(M_CCHAN, M_CCHAN)
209: test QOFF_CTLSTA, HS_MAILBOX_ACT jz hs_mailbox_empty;
210: or QOFF_CTLSTA, HS_MAILBOX_ACT;
211: mov LOCAL_HS_MAILBOX, HS_MAILBOX;
212: hs_mailbox_empty:
213: BEGIN_CRITICAL;
214: test CCSCBCTL, CCARREN|CCSCBEN jz scbdma_idle;
215: test CCSCBCTL, CCSCBDIR jnz fetch_new_scb_inprog;
216: test CCSCBCTL, CCSCBDONE jz return;
217: /* FALLTHROUGH */
218: scbdma_tohost_done:
219: test CCSCBCTL, CCARREN jz fill_qoutfifo_dmadone;
220: /*
221: * An SCB has been successfully uploaded to the host.
222: * If the SCB was uploaded for some reason other than
223: * bad SCSI status (currently only for underruns), we
224: * queue the SCB for normal completion. Otherwise, we
225: * wait until any select-out activity has halted, and
226: * then queue the completion.
227: */
228: and CCSCBCTL, ~(CCARREN|CCSCBEN);
229: bmov COMPLETE_DMA_SCB_HEAD, SCB_NEXT_COMPLETE, 2;
230: cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL jne . + 2;
231: mvi COMPLETE_DMA_SCB_TAIL[1], SCB_LIST_NULL;
232: test SCB_SCSI_STATUS, 0xff jz scbdma_queue_completion;
233: bmov SCB_NEXT_COMPLETE, COMPLETE_ON_QFREEZE_HEAD, 2;
234: bmov COMPLETE_ON_QFREEZE_HEAD, SCBPTR, 2 ret;
235: scbdma_queue_completion:
236: bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
237: bmov COMPLETE_SCB_HEAD, SCBPTR, 2 ret;
238: fill_qoutfifo_dmadone:
239: and CCSCBCTL, ~(CCARREN|CCSCBEN);
240: call qoutfifo_updated;
241: mvi COMPLETE_SCB_DMAINPROG_HEAD[1], SCB_LIST_NULL;
242: bmov QOUTFIFO_NEXT_ADDR, SCBHADDR, 4;
243: test QOFF_CTLSTA, SDSCB_ROLLOVR jz return;
244: bmov QOUTFIFO_NEXT_ADDR, SHARED_DATA_ADDR, 4;
245: xor QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID_TOGGLE ret;
246: END_CRITICAL;
247:
248: qoutfifo_updated:
249: /*
250: * If there are more commands waiting to be dma'ed
251: * to the host, always coalesce. Otherwise honor the
252: * host's wishes.
253: */
254: cmp COMPLETE_DMA_SCB_HEAD[1], SCB_LIST_NULL jne coalesce_by_count;
255: cmp COMPLETE_SCB_HEAD[1], SCB_LIST_NULL jne coalesce_by_count;
256: test LOCAL_HS_MAILBOX, ENINT_COALESCE jz issue_cmdcmplt;
257:
258: /*
259: * If we have relatively few commands outstanding, don't
260: * bother waiting for another command to complete.
261: */
262: test CMDS_PENDING[1], 0xFF jnz coalesce_by_count;
263: /* Add -1 so that jnc means <= not just < */
264: add A, -1, INT_COALESCING_MINCMDS;
265: add NONE, A, CMDS_PENDING;
266: jnc issue_cmdcmplt;
267:
268: /*
269: * If coalescing, only coalesce up to the limit
270: * provided by the host driver.
271: */
272: coalesce_by_count:
273: mov A, INT_COALESCING_MAXCMDS;
274: add NONE, A, INT_COALESCING_CMDCOUNT;
275: jc issue_cmdcmplt;
276: /*
277: * If the timer is not currently active,
278: * fire it up.
279: */
280: test INTCTL, SWTMINTMASK jz return;
281: bmov SWTIMER, INT_COALESCING_TIMER, 2;
282: mvi CLRSEQINTSTAT, CLRSEQ_SWTMRTO;
283: or INTCTL, SWTMINTEN|SWTIMER_START;
284: and INTCTL, ~SWTMINTMASK ret;
285:
286: issue_cmdcmplt:
287: mvi INTSTAT, CMDCMPLT;
288: clr INT_COALESCING_CMDCOUNT;
289: or INTCTL, SWTMINTMASK ret;
290:
291: BEGIN_CRITICAL;
292: fetch_new_scb_inprog:
293: test CCSCBCTL, ARRDONE jz return;
294: fetch_new_scb_done:
295: and CCSCBCTL, ~(CCARREN|CCSCBEN);
296: clr A;
297: add CMDS_PENDING, 1;
298: adc CMDS_PENDING[1], A;
299: if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
300: /*
301: * "Short Luns" are not placed into outgoing LQ
302: * packets in the correct byte order. Use a full
303: * sized lun field instead and fill it with the
304: * one byte of lun information we support.
305: */
306: mov SCB_PKT_LUN[6], SCB_LUN;
307: }
308: /*
309: * The FIFO use count field is shared with the
310: * tag set by the host so that our SCB dma engine
311: * knows the correct location to store the SCB.
312: * Set it to zero before processing the SCB.
313: */
314: clr SCB_FIFO_USE_COUNT;
315: /* Update the next SCB address to download. */
316: bmov NEXT_QUEUED_SCB_ADDR, SCB_NEXT_SCB_BUSADDR, 4;
317: /*
318: * NULL out the SCB links since these fields
319: * occupy the same location as SCB_NEXT_SCB_BUSADDR.
320: */
321: mvi SCB_NEXT[1], SCB_LIST_NULL;
322: mvi SCB_NEXT2[1], SCB_LIST_NULL;
323: /* Increment our position in the QINFIFO. */
324: mov NONE, SNSCB_QOFF;
325:
326: /*
327: * Save SCBID of this SCB in REG0 since
328: * SCBPTR will be clobbered during target
329: * list updates. We also record the SCB's
330: * flags so that we can refer to them even
331: * after SCBPTR has been changed.
332: */
333: bmov REG0, SCBPTR, 2;
334: mov A, SCB_CONTROL;
335:
336: /*
337: * Find the tail SCB of the execution queue
338: * for this target.
339: */
340: shr SINDEX, 3, SCB_SCSIID;
341: and SINDEX, ~0x1;
342: mvi SINDEX[1], (WAITING_SCB_TAILS >> 8);
343: bmov DINDEX, SINDEX, 2;
344: bmov SCBPTR, SINDIR, 2;
345:
346: /*
347: * Update the tail to point to the new SCB.
348: */
349: bmov DINDIR, REG0, 2;
350:
351: /*
352: * If the queue was empty, queue this SCB as
353: * the first for this target.
354: */
355: cmp SCBPTR[1], SCB_LIST_NULL je first_new_target_scb;
356:
357: /*
358: * SCBs that want to send messages must always be
359: * at the head of their per-target queue so that
360: * ATN can be asserted even if the current
361: * negotiation agreement is packetized. If the
362: * target queue is empty, the SCB can be queued
363: * immediately. If the queue is not empty, we must
364: * wait for it to empty before entering this SCB
365: * into the waiting for selection queue. Otherwise
366: * our batching and round-robin selection scheme
367: * could allow commands to be queued out of order.
368: * To simplify the implementation, we stop pulling
369: * new commands from the host until the MK_MESSAGE
370: * SCB can be queued to the waiting for selection
371: * list.
372: */
373: test A, MK_MESSAGE jz batch_scb;
374:
375: /*
376: * If the last SCB is also a MK_MESSAGE SCB, then
377: * order is preserved even if we batch.
378: */
379: test SCB_CONTROL, MK_MESSAGE jz batch_scb;
380:
381: /*
382: * Defer this SCB and stop fetching new SCBs until
383: * it can be queued. Since the SCB_SCSIID of the
384: * tail SCB must be the same as that of the newly
385: * queued SCB, there is no need to restore the SCBID
386: * here.
387: */
388: or SEQ_FLAGS2, PENDING_MK_MESSAGE;
389: bmov MK_MESSAGE_SCB, REG0, 2;
390: mov MK_MESSAGE_SCSIID, SCB_SCSIID ret;
391:
392: batch_scb:
393: /*
394: * Otherwise just update the previous tail SCB to
395: * point to the new tail.
396: */
397: bmov SCB_NEXT, REG0, 2 ret;
398:
399: first_new_target_scb:
400: /*
401: * Append SCB to the tail of the waiting for
402: * selection list.
403: */
404: cmp WAITING_TID_HEAD[1], SCB_LIST_NULL je first_new_scb;
405: bmov SCBPTR, WAITING_TID_TAIL, 2;
406: bmov SCB_NEXT2, REG0, 2;
407: bmov WAITING_TID_TAIL, REG0, 2 ret;
408: first_new_scb:
409: /*
410: * Whole list is empty, so the head of
411: * the list must be initialized too.
412: */
413: bmov WAITING_TID_HEAD, REG0, 2;
414: bmov WAITING_TID_TAIL, REG0, 2 ret;
415: END_CRITICAL;
416:
417: scbdma_idle:
418: /*
419: * Don't bother downloading new SCBs to execute
420: * if select-outs are currently frozen or we have
421: * a MK_MESSAGE SCB waiting to enter the queue.
422: */
423: test SEQ_FLAGS2, SELECTOUT_QFROZEN|PENDING_MK_MESSAGE
424: jnz scbdma_no_new_scbs;
425: BEGIN_CRITICAL;
426: test QOFF_CTLSTA, NEW_SCB_AVAIL jnz fetch_new_scb;
427: scbdma_no_new_scbs:
428: cmp COMPLETE_DMA_SCB_HEAD[1], SCB_LIST_NULL jne dma_complete_scb;
429: cmp COMPLETE_SCB_HEAD[1], SCB_LIST_NULL je return;
430: /* FALLTHROUGH */
431: fill_qoutfifo:
432: /*
433: * Keep track of the SCBs we are dmaing just
434: * in case the DMA fails or is aborted.
435: */
436: bmov COMPLETE_SCB_DMAINPROG_HEAD, COMPLETE_SCB_HEAD, 2;
437: mvi CCSCBCTL, CCSCBRESET;
438: bmov SCBHADDR, QOUTFIFO_NEXT_ADDR, 4;
439: mov A, QOUTFIFO_NEXT_ADDR;
440: bmov SCBPTR, COMPLETE_SCB_HEAD, 2;
441: fill_qoutfifo_loop:
442: bmov CCSCBRAM, SCBPTR, 2;
443: mov CCSCBRAM, SCB_SGPTR[0];
444: mov CCSCBRAM, QOUTFIFO_ENTRY_VALID_TAG;
445: mov NONE, SDSCB_QOFF;
446: inc INT_COALESCING_CMDCOUNT;
447: add CMDS_PENDING, -1;
448: adc CMDS_PENDING[1], -1;
449: cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL je fill_qoutfifo_done;
450: cmp CCSCBADDR, CCSCBADDR_MAX je fill_qoutfifo_done;
451: test QOFF_CTLSTA, SDSCB_ROLLOVR jnz fill_qoutfifo_done;
452: /*
453: * Don't cross an ADB or Cachline boundary when DMA'ing
454: * completion entries. In PCI mode, at least in 32/33
455: * configurations, the SCB DMA engine may lose its place
456: * in the data-stream should the target force a retry on
457: * something other than an 8byte aligned boundary. In
458: * PCI-X mode, we do this to avoid split transactions since
459: * many chipsets seem to be unable to format proper split
460: * completions to continue the data transfer.
461: */
462: add SINDEX, A, CCSCBADDR;
463: test SINDEX, CACHELINE_MASK jz fill_qoutfifo_done;
464: bmov SCBPTR, SCB_NEXT_COMPLETE, 2;
465: jmp fill_qoutfifo_loop;
466: fill_qoutfifo_done:
467: mov SCBHCNT, CCSCBADDR;
468: mvi CCSCBCTL, CCSCBEN|CCSCBRESET;
469: bmov COMPLETE_SCB_HEAD, SCB_NEXT_COMPLETE, 2;
470: mvi SCB_NEXT_COMPLETE[1], SCB_LIST_NULL ret;
471:
472: fetch_new_scb:
473: bmov SCBHADDR, NEXT_QUEUED_SCB_ADDR, 4;
474: mvi CCARREN|CCSCBEN|CCSCBDIR|CCSCBRESET jmp dma_scb;
475: dma_complete_scb:
476: bmov SCBPTR, COMPLETE_DMA_SCB_HEAD, 2;
477: bmov SCBHADDR, SCB_BUSADDR, 4;
478: mvi CCARREN|CCSCBEN|CCSCBRESET jmp dma_scb;
479:
480: /*
481: * Either post or fetch an SCB from host memory. The caller
482: * is responsible for polling for transfer completion.
483: *
484: * Prerequisites: Mode == M_CCHAN
485: * SINDEX contains CCSCBCTL flags
486: * SCBHADDR set to Host SCB address
487: * SCBPTR set to SCB src location on "push" operations
488: */
489: SET_SRC_MODE M_CCHAN;
490: SET_DST_MODE M_CCHAN;
491: dma_scb:
492: mvi SCBHCNT, SCB_TRANSFER_SIZE;
493: mov CCSCBCTL, SINDEX ret;
494:
495: setjmp:
496: /*
497: * At least on the A, a return in the same
498: * instruction as the bmov results in a return
499: * to the caller, not to the new address at the
500: * top of the stack. Since we want the latter
501: * (we use setjmp to register a handler from an
502: * interrupt context but not invoke that handler
503: * until we return to our idle loop), use a
504: * separate ret instruction.
505: */
506: bmov LONGJMP_ADDR, STACK, 2;
507: ret;
508: setjmp_inline:
509: bmov LONGJMP_ADDR, STACK, 2;
510: longjmp:
511: bmov STACK, LONGJMP_ADDR, 2 ret;
512: END_CRITICAL;
513:
514: /*************************** Chip Bug Work Arounds ****************************/
515: /*
516: * Must disable interrupts when setting the mode pointer
517: * register as an interrupt occurring mid update will
518: * fail to store the new mode value for restoration on
519: * an iret.
520: */
521: if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) {
522: set_mode_work_around:
523: mvi SEQINTCTL, INTVEC1DSL;
524: mov MODE_PTR, SINDEX;
525: clr SEQINTCTL ret;
526: }
527:
528:
529: if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
530: set_seqint_work_around:
531: mov SEQINTCODE, SINDEX;
532: mvi SEQINTCODE, NO_SEQINT ret;
533: }
534:
535: /************************ Packetized LongJmp Routines *************************/
536: SET_SRC_MODE M_SCSI;
537: SET_DST_MODE M_SCSI;
538: start_selection:
539: BEGIN_CRITICAL;
540: if ((ahd->bugs & AHD_SENT_SCB_UPDATE_BUG) != 0) {
541: /*
542: * Razor #494
543: * Rev A hardware fails to update LAST/CURR/NEXTSCB
544: * correctly after a packetized selection in several
545: * situations:
546: *
547: * 1) If only one command existed in the queue, the
548: * LAST/CURR/NEXTSCB are unchanged.
549: *
550: * 2) In a non QAS, protocol allowed phase change,
551: * the queue is shifted 1 too far. LASTSCB is
552: * the last SCB that was correctly processed.
553: *
554: * 3) In the QAS case, if the full list of commands
555: * was successfully sent, NEXTSCB is NULL and neither
556: * CURRSCB nor LASTSCB can be trusted. We must
557: * manually walk the list counting MAXCMDCNT elements
558: * to find the last SCB that was sent correctly.
559: *
560: * To simplify the workaround for this bug in SELDO
561: * handling, we initialize LASTSCB prior to enabling
562: * selection so we can rely on it even for case #1 above.
563: */
564: bmov LASTSCB, WAITING_TID_HEAD, 2;
565: }
566: bmov CURRSCB, WAITING_TID_HEAD, 2;
567: bmov SCBPTR, WAITING_TID_HEAD, 2;
568: shr SELOID, 4, SCB_SCSIID;
569: /*
570: * If we want to send a message to the device, ensure
571: * we are selecting with atn irregardless of our packetized
572: * agreement. Since SPI4 only allows target reset or PPR
573: * messages if this is a packetized connection, the change
574: * to our negotiation table entry for this selection will
575: * be cleared when the message is acted on.
576: */
577: test SCB_CONTROL, MK_MESSAGE jz . + 3;
578: mov NEGOADDR, SELOID;
579: or NEGCONOPTS, ENAUTOATNO;
580: or SCSISEQ0, ENSELO ret;
581: END_CRITICAL;
582:
583: /*
584: * Allocate a FIFO for a non-packetized transaction.
585: * In RevA hardware, both FIFOs must be free before we
586: * can allocate a FIFO for a non-packetized transaction.
587: */
588: allocate_fifo_loop:
589: /*
590: * Do whatever work is required to free a FIFO.
591: */
592: call idle_loop_service_fifos;
593: SET_MODE(M_SCSI, M_SCSI)
594: allocate_fifo:
595: if ((ahd->bugs & AHD_NONPACKFIFO_BUG) != 0) {
596: and A, FIFO0FREE|FIFO1FREE, DFFSTAT;
597: cmp A, FIFO0FREE|FIFO1FREE jne allocate_fifo_loop;
598: } else {
599: test DFFSTAT, FIFO1FREE jnz allocate_fifo1;
600: test DFFSTAT, FIFO0FREE jz allocate_fifo_loop;
601: mvi DFFSTAT, B_CURRFIFO_0;
602: SET_MODE(M_DFF0, M_DFF0)
603: bmov SCBPTR, ALLOCFIFO_SCBPTR, 2 ret;
604: }
605: SET_SRC_MODE M_SCSI;
606: SET_DST_MODE M_SCSI;
607: allocate_fifo1:
608: mvi DFFSTAT, CURRFIFO_1;
609: SET_MODE(M_DFF1, M_DFF1)
610: bmov SCBPTR, ALLOCFIFO_SCBPTR, 2 ret;
611:
612: /*
613: * We have been reselected as an initiator
614: * or selected as a target.
615: */
616: SET_SRC_MODE M_SCSI;
617: SET_DST_MODE M_SCSI;
618: select_in:
619: if ((ahd->bugs & AHD_FAINT_LED_BUG) != 0) {
620: /*
621: * On Rev A. hardware, the busy LED is only
622: * turned on automatically during selections
623: * and re-selections. Make the LED status
624: * more useful by forcing it to be on from
625: * the point of selection until our idle
626: * loop determines that neither of our FIFOs
627: * are busy. This handles the non-packetized
628: * case nicely as we will not return to the
629: * idle loop until the busfree at the end of
630: * each transaction.
631: */
632: or SBLKCTL, DIAGLEDEN|DIAGLEDON;
633: }
634: if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
635: /*
636: * Test to ensure that the bus has not
637: * already gone free prior to clearing
638: * any stale busfree status. This avoids
639: * a window whereby a busfree just after
640: * a selection could be missed.
641: */
642: test SCSISIGI, BSYI jz . + 2;
643: mvi CLRSINT1,CLRBUSFREE;
644: or SIMODE1, ENBUSFREE;
645: }
646: or SXFRCTL0, SPIOEN;
647: and SAVED_SCSIID, SELID_MASK, SELID;
648: and A, OID, IOWNID;
649: or SAVED_SCSIID, A;
650: mvi CLRSINT0, CLRSELDI;
651: jmp ITloop;
652:
653: /*
654: * We have successfully selected out.
655: *
656: * Clear SELDO.
657: * Dequeue all SCBs sent from the waiting queue
658: * Requeue all SCBs *not* sent to the tail of the waiting queue
659: * Take Razor #494 into account for above.
660: *
661: * In Packetized Mode:
662: * Return to the idle loop. Our interrupt handler will take
663: * care of any incoming L_Qs.
664: *
665: * In Non-Packetize Mode:
666: * Continue to our normal state machine.
667: */
668: SET_SRC_MODE M_SCSI;
669: SET_DST_MODE M_SCSI;
670: select_out:
671: BEGIN_CRITICAL;
672: if ((ahd->bugs & AHD_FAINT_LED_BUG) != 0) {
673: /*
674: * On Rev A. hardware, the busy LED is only
675: * turned on automatically during selections
676: * and re-selections. Make the LED status
677: * more useful by forcing it to be on from
678: * the point of re-selection until our idle
679: * loop determines that neither of our FIFOs
680: * are busy. This handles the non-packetized
681: * case nicely as we will not return to the
682: * idle loop until the busfree at the end of
683: * each transaction.
684: */
685: or SBLKCTL, DIAGLEDEN|DIAGLEDON;
686: }
687: /* Clear out all SCBs that have been successfully sent. */
688: if ((ahd->bugs & AHD_SENT_SCB_UPDATE_BUG) != 0) {
689: /*
690: * For packetized, the LQO manager clears ENSELO on
691: * the assertion of SELDO. If we are non-packetized,
692: * LASTSCB and CURRSCB are accurate.
693: */
694: test SCSISEQ0, ENSELO jnz use_lastscb;
695:
696: /*
697: * The update is correct for LQOSTAT1 errors. All
698: * but LQOBUSFREE are handled by kernel interrupts.
699: * If we see LQOBUSFREE, return to the idle loop.
700: * Once we are out of the select_out critical section,
701: * the kernel will cleanup the LQOBUSFREE and we will
702: * eventually restart the selection if appropriate.
703: */
704: test LQOSTAT1, LQOBUSFREE jnz idle_loop;
705:
706: /*
707: * On a phase change outside of packet boundaries,
708: * LASTSCB points to the currently active SCB context
709: * on the bus.
710: */
711: test LQOSTAT2, LQOPHACHGOUTPKT jnz use_lastscb;
712:
713: /*
714: * If the hardware has traversed the whole list, NEXTSCB
715: * will be NULL, CURRSCB and LASTSCB cannot be trusted,
716: * but MAXCMDCNT is accurate. If we stop part way through
717: * the list or only had one command to issue, NEXTSCB[1] is
718: * not NULL and LASTSCB is the last command to go out.
719: */
720: cmp NEXTSCB[1], SCB_LIST_NULL jne use_lastscb;
721:
722: /*
723: * Brute force walk.
724: */
725: bmov SCBPTR, WAITING_TID_HEAD, 2;
726: mvi SEQINTCTL, INTVEC1DSL;
727: mvi MODE_PTR, MK_MODE(M_CFG, M_CFG);
728: mov A, MAXCMDCNT;
729: mvi MODE_PTR, MK_MODE(M_SCSI, M_SCSI);
730: clr SEQINTCTL;
731: find_lastscb_loop:
732: dec A;
733: test A, 0xFF jz found_last_sent_scb;
734: bmov SCBPTR, SCB_NEXT, 2;
735: jmp find_lastscb_loop;
736: use_lastscb:
737: bmov SCBPTR, LASTSCB, 2;
738: found_last_sent_scb:
739: bmov CURRSCB, SCBPTR, 2;
740: curscb_ww_done:
741: } else {
742: bmov SCBPTR, CURRSCB, 2;
743: }
744:
745: /*
746: * The whole list made it. Clear our tail pointer to indicate
747: * that the per-target selection queue is now empty.
748: */
749: cmp SCB_NEXT[1], SCB_LIST_NULL je select_out_clear_tail;
750:
751: /*
752: * Requeue any SCBs not sent, to the tail of the waiting Q.
753: * We know that neither the per-TID list nor the list of
754: * TIDs is empty. Use this knowledge to our advantage and
755: * queue the remainder to the tail of the global execution
756: * queue.
757: */
758: bmov REG0, SCB_NEXT, 2;
759: select_out_queue_remainder:
760: bmov SCBPTR, WAITING_TID_TAIL, 2;
761: bmov SCB_NEXT2, REG0, 2;
762: bmov WAITING_TID_TAIL, REG0, 2;
763: jmp select_out_inc_tid_q;
764:
765: select_out_clear_tail:
766: /*
767: * Queue any pending MK_MESSAGE SCB for this target now
768: * that the queue is empty.
769: */
770: test SEQ_FLAGS2, PENDING_MK_MESSAGE jz select_out_no_mk_message_scb;
771: mov A, MK_MESSAGE_SCSIID;
772: cmp SCB_SCSIID, A jne select_out_no_mk_message_scb;
773: and SEQ_FLAGS2, ~PENDING_MK_MESSAGE;
774: bmov REG0, MK_MESSAGE_SCB, 2;
775: jmp select_out_queue_remainder;
776:
777: select_out_no_mk_message_scb:
778: /*
779: * Clear this target's execution tail and increment the queue.
780: */
781: shr DINDEX, 3, SCB_SCSIID;
782: or DINDEX, 1; /* Want only the second byte */
783: mvi DINDEX[1], ((WAITING_SCB_TAILS) >> 8);
784: mvi DINDIR, SCB_LIST_NULL;
785: select_out_inc_tid_q:
786: bmov SCBPTR, WAITING_TID_HEAD, 2;
787: bmov WAITING_TID_HEAD, SCB_NEXT2, 2;
788: cmp WAITING_TID_HEAD[1], SCB_LIST_NULL jne . + 2;
789: mvi WAITING_TID_TAIL[1], SCB_LIST_NULL;
790: bmov SCBPTR, CURRSCB, 2;
791: mvi CLRSINT0, CLRSELDO;
792: test LQOSTAT2, LQOPHACHGOUTPKT jnz unexpected_nonpkt_mode_cleared;
793: test LQOSTAT1, LQOPHACHGINPKT jnz unexpected_nonpkt_mode_cleared;
794:
795: /*
796: * If this is a packetized connection, return to our
797: * idle_loop and let our interrupt handler deal with
798: * any connection setup/teardown issues. The only
799: * exceptions are the case of MK_MESSAGE and task management
800: * SCBs.
801: */
802: if ((ahd->bugs & AHD_LQO_ATNO_BUG) != 0) {
803: /*
804: * In the A, the LQO manager transitions to LQOSTOP0 even if
805: * we have selected out with ATN asserted and the target
806: * REQs in a non-packet phase.
807: */
808: test SCB_CONTROL, MK_MESSAGE jz select_out_no_message;
809: test SCSISIGO, ATNO jnz select_out_non_packetized;
810: select_out_no_message:
811: }
812: test LQOSTAT2, LQOSTOP0 jz select_out_non_packetized;
813: test SCB_TASK_MANAGEMENT, 0xFF jz idle_loop;
814: SET_SEQINTCODE(TASKMGMT_FUNC_COMPLETE)
815: jmp idle_loop;
816:
817: select_out_non_packetized:
818: /* Non packetized request. */
819: and SCSISEQ0, ~ENSELO;
820: if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
821: /*
822: * Test to ensure that the bus has not
823: * already gone free prior to clearing
824: * any stale busfree status. This avoids
825: * a window whereby a busfree just after
826: * a selection could be missed.
827: */
828: test SCSISIGI, BSYI jz . + 2;
829: mvi CLRSINT1,CLRBUSFREE;
830: or SIMODE1, ENBUSFREE;
831: }
832: mov SAVED_SCSIID, SCB_SCSIID;
833: mov SAVED_LUN, SCB_LUN;
834: mvi SEQ_FLAGS, NO_CDB_SENT;
835: END_CRITICAL;
836: or SXFRCTL0, SPIOEN;
837:
838: /*
839: * As soon as we get a successful selection, the target
840: * should go into the message out phase since we have ATN
841: * asserted.
842: */
843: mvi MSG_OUT, MSG_IDENTIFYFLAG;
844:
845: /*
846: * Main loop for information transfer phases. Wait for the
847: * target to assert REQ before checking MSG, C/D and I/O for
848: * the bus phase.
849: */
850: mesgin_phasemis:
851: ITloop:
852: call phase_lock;
853:
854: mov A, LASTPHASE;
855:
856: test A, ~P_DATAIN_DT jz p_data;
857: cmp A,P_COMMAND je p_command;
858: cmp A,P_MESGOUT je p_mesgout;
859: cmp A,P_STATUS je p_status;
860: cmp A,P_MESGIN je p_mesgin;
861:
862: SET_SEQINTCODE(BAD_PHASE)
863: jmp ITloop; /* Try reading the bus again. */
864:
865: /*
866: * Command phase. Set up the DMA registers and let 'er rip.
867: */
868: p_command:
869: test SEQ_FLAGS, NOT_IDENTIFIED jz p_command_okay;
870: SET_SEQINTCODE(PROTO_VIOLATION)
871: p_command_okay:
872: test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
873: jnz p_command_allocate_fifo;
874: /*
875: * Command retry. Free our current FIFO and
876: * re-allocate a FIFO so transfer state is
877: * reset.
878: */
879: SET_SRC_MODE M_DFF1;
880: SET_DST_MODE M_DFF1;
881: mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
882: SET_MODE(M_SCSI, M_SCSI)
883: p_command_allocate_fifo:
884: bmov ALLOCFIFO_SCBPTR, SCBPTR, 2;
885: call allocate_fifo;
886: SET_SRC_MODE M_DFF1;
887: SET_DST_MODE M_DFF1;
888: add NONE, -17, SCB_CDB_LEN;
889: jnc p_command_embedded;
890: p_command_from_host:
891: bmov HADDR[0], SCB_HOST_CDB_PTR, 9;
892: mvi SG_CACHE_PRE, LAST_SEG;
893: mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
894: jmp p_command_xfer;
895: p_command_embedded:
896: bmov SHCNT[0], SCB_CDB_LEN, 1;
897: bmov DFDAT, SCB_CDB_STORE, 16;
898: mvi DFCNTRL, SCSIEN;
899: p_command_xfer:
900: and SEQ_FLAGS, ~NO_CDB_SENT;
901: if ((ahd->features & AHD_FAST_CDB_DELIVERY) != 0) {
902: /*
903: * To speed up CDB delivery in Rev B, all CDB acks
904: * are "released" to the output sync as soon as the
905: * command phase starts. There is only one problem
906: * with this approach. If the target changes phase
907: * before all data are sent, we have left over acks
908: * that can go out on the bus in a data phase. Due
909: * to other chip contraints, this only happens if
910: * the target goes to data-in, but if the acks go
911: * out before we can test SDONE, we'll think that
912: * the transfer has completed successfully. Work
913: * around this by taking advantage of the 400ns or
914: * 800ns dead time between command phase and the REQ
915: * of the new phase. If the transfer has completed
916: * successfully, SCSIEN should fall *long* before we
917: * see a phase change. We thus treat any phasemiss
918: * that occurs before SCSIEN falls as an incomplete
919: * transfer.
920: */
921: test SSTAT1, PHASEMIS jnz p_command_xfer_failed;
922: test DFCNTRL, SCSIEN jnz . - 1;
923: } else {
924: test DFCNTRL, SCSIEN jnz .;
925: }
926: /*
927: * DMA Channel automatically disabled.
928: * Don't allow a data phase if the command
929: * was not fully transferred.
930: */
931: test SSTAT2, SDONE jnz ITloop;
932: p_command_xfer_failed:
933: or SEQ_FLAGS, NO_CDB_SENT;
934: jmp ITloop;
935:
936:
937: /*
938: * Status phase. Wait for the data byte to appear, then read it
939: * and store it into the SCB.
940: */
941: SET_SRC_MODE M_SCSI;
942: SET_DST_MODE M_SCSI;
943: p_status:
944: test SEQ_FLAGS,NOT_IDENTIFIED jnz mesgin_proto_violation;
945: p_status_okay:
946: mov SCB_SCSI_STATUS, SCSIDAT;
947: or SCB_CONTROL, STATUS_RCVD;
948: jmp ITloop;
949:
950: /*
951: * Message out phase. If MSG_OUT is MSG_IDENTIFYFLAG, build a full
952: * identify message sequence and send it to the target. The host may
953: * override this behavior by setting the MK_MESSAGE bit in the SCB
954: * control byte. This will cause us to interrupt the host and allow
955: * it to handle the message phase completely on its own. If the bit
956: * associated with this target is set, we will also interrupt the host,
957: * thereby allowing it to send a message on the next selection regardless
958: * of the transaction being sent.
959: *
960: * If MSG_OUT is == HOST_MSG, also interrupt the host and take a message.
961: * This is done to allow the host to send messages outside of an identify
962: * sequence while protecting the sequencer from testing the MK_MESSAGE bit
963: * on an SCB that might not be for the current nexus. (For example, a
964: * BDR message in response to a bad reselection would leave us pointed to
965: * an SCB that doesn't have anything to do with the current target).
966: *
967: * Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag,
968: * bus device reset).
969: *
970: * When there are no messages to send, MSG_OUT should be set to MSG_NOOP,
971: * in case the target decides to put us in this phase for some strange
972: * reason.
973: */
974: p_mesgout_retry:
975: /* Turn on ATN for the retry */
976: mvi SCSISIGO, ATNO;
977: p_mesgout:
978: mov SINDEX, MSG_OUT;
979: cmp SINDEX, MSG_IDENTIFYFLAG jne p_mesgout_from_host;
980: test SCB_CONTROL,MK_MESSAGE jnz host_message_loop;
981: p_mesgout_identify:
982: or SINDEX, MSG_IDENTIFYFLAG|DISCENB, SCB_LUN;
983: test SCB_CONTROL, DISCENB jnz . + 2;
984: and SINDEX, ~DISCENB;
985: /*
986: * Send a tag message if TAG_ENB is set in the SCB control block.
987: * Use SCB_NONPACKET_TAG as the tag value.
988: */
989: p_mesgout_tag:
990: test SCB_CONTROL,TAG_ENB jz p_mesgout_onebyte;
991: mov SCSIDAT, SINDEX; /* Send the identify message */
992: call phase_lock;
993: cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
994: and SCSIDAT,TAG_ENB|SCB_TAG_TYPE,SCB_CONTROL;
995: call phase_lock;
996: cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
997: mov SCBPTR jmp p_mesgout_onebyte;
998: /*
999: * Interrupt the driver, and allow it to handle this message
1000: * phase and any required retries.
1001: */
1002: p_mesgout_from_host:
1003: cmp SINDEX, HOST_MSG jne p_mesgout_onebyte;
1004: jmp host_message_loop;
1005:
1006: p_mesgout_onebyte:
1007: mvi CLRSINT1, CLRATNO;
1008: mov SCSIDAT, SINDEX;
1009:
1010: /*
1011: * If the next bus phase after ATN drops is message out, it means
1012: * that the target is requesting that the last message(s) be resent.
1013: */
1014: call phase_lock;
1015: cmp LASTPHASE, P_MESGOUT je p_mesgout_retry;
1016:
1017: p_mesgout_done:
1018: mvi CLRSINT1,CLRATNO; /* Be sure to turn ATNO off */
1019: mov LAST_MSG, MSG_OUT;
1020: mvi MSG_OUT, MSG_NOOP; /* No message left */
1021: jmp ITloop;
1022:
1023: /*
1024: * Message in phase. Bytes are read using Automatic PIO mode.
1025: */
1026: p_mesgin:
1027: /* read the 1st message byte */
1028: mvi ACCUM call inb_first;
1029:
1030: test A,MSG_IDENTIFYFLAG jnz mesgin_identify;
1031: cmp A,MSG_DISCONNECT je mesgin_disconnect;
1032: cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs;
1033: cmp ALLZEROS,A je mesgin_complete;
1034: cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs;
1035: cmp A,MSG_IGN_WIDE_RESIDUE je mesgin_ign_wide_residue;
1036: cmp A,MSG_NOOP je mesgin_done;
1037:
1038: /*
1039: * Pushed message loop to allow the kernel to
1040: * run its own message state engine. To avoid an
1041: * extra nop instruction after signaling the kernel,
1042: * we perform the phase_lock before checking to see
1043: * if we should exit the loop and skip the phase_lock
1044: * in the ITloop. Performing back to back phase_locks
1045: * shouldn't hurt, but why do it twice...
1046: */
1047: host_message_loop:
1048: call phase_lock; /* Benign the first time through. */
1049: SET_SEQINTCODE(HOST_MSG_LOOP)
1050: cmp RETURN_1, EXIT_MSG_LOOP je ITloop;
1051: cmp RETURN_1, CONT_MSG_LOOP_WRITE jne . + 3;
1052: mov SCSIDAT, RETURN_2;
1053: jmp host_message_loop;
1054: /* Must be CONT_MSG_LOOP_READ */
1055: mov NONE, SCSIDAT; /* ACK Byte */
1056: jmp host_message_loop;
1057:
1058: mesgin_ign_wide_residue:
1059: mov SAVED_MODE, MODE_PTR;
1060: SET_MODE(M_SCSI, M_SCSI)
1061: shr NEGOADDR, 4, SAVED_SCSIID;
1062: mov A, NEGCONOPTS;
1063: RESTORE_MODE(SAVED_MODE)
1064: test A, WIDEXFER jz mesgin_reject;
1065: /* Pull the residue byte */
1066: mvi REG0 call inb_next;
1067: cmp REG0, 0x01 jne mesgin_reject;
1068: test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 2;
1069: test SCB_TASK_ATTRIBUTE, SCB_XFERLEN_ODD jnz mesgin_done;
1070: SET_SEQINTCODE(IGN_WIDE_RES)
1071: jmp mesgin_done;
1072:
1073: mesgin_proto_violation:
1074: SET_SEQINTCODE(PROTO_VIOLATION)
1075: jmp mesgin_done;
1076: mesgin_reject:
1077: mvi MSG_MESSAGE_REJECT call mk_mesg;
1078: mesgin_done:
1079: mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
1080: jmp ITloop;
1081:
1082: #define INDEX_DISC_LIST(scsiid, lun) \
1083: and A, 0xC0, scsiid; \
1084: or SCBPTR, A, lun; \
1085: clr SCBPTR[1]; \
1086: and SINDEX, 0x30, scsiid; \
1087: shr SINDEX, 3; /* Multiply by 2 */ \
1088: add SINDEX, (SCB_DISCONNECTED_LISTS & 0xFF); \
1089: mvi SINDEX[1], ((SCB_DISCONNECTED_LISTS >> 8) & 0xFF)
1090:
1091: mesgin_identify:
1092: /*
1093: * Determine whether a target is using tagged or non-tagged
1094: * transactions by first looking at the transaction stored in
1095: * the per-device, disconnected array. If there is no untagged
1096: * transaction for this target, this must be a tagged transaction.
1097: */
1098: and SAVED_LUN, MSG_IDENTIFY_LUNMASK, A;
1099: INDEX_DISC_LIST(SAVED_SCSIID, SAVED_LUN);
1100: bmov DINDEX, SINDEX, 2;
1101: bmov REG0, SINDIR, 2;
1102: cmp REG0[1], SCB_LIST_NULL je snoop_tag;
1103: /* Untagged. Clear the busy table entry and setup the SCB. */
1104: bmov DINDIR, ALLONES, 2;
1105: bmov SCBPTR, REG0, 2;
1106: jmp setup_SCB;
1107:
1108: /*
1109: * Here we "snoop" the bus looking for a SIMPLE QUEUE TAG message.
1110: * If we get one, we use the tag returned to find the proper
1111: * SCB. After receiving the tag, look for the SCB at SCB locations tag and
1112: * tag + 256.
1113: */
1114: snoop_tag:
1115: if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
1116: or SEQ_FLAGS, 0x80;
1117: }
1118: mov NONE, SCSIDAT; /* ACK Identify MSG */
1119: call phase_lock;
1120: if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
1121: or SEQ_FLAGS, 0x1;
1122: }
1123: cmp LASTPHASE, P_MESGIN jne not_found_ITloop;
1124: if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
1125: or SEQ_FLAGS, 0x2;
1126: }
1127: cmp SCSIBUS, MSG_SIMPLE_Q_TAG jne not_found;
1128: get_tag:
1129: clr SCBPTR[1];
1130: mvi SCBPTR call inb_next; /* tag value */
1131: verify_scb:
1132: test SCB_CONTROL,DISCONNECTED jz verify_other_scb;
1133: mov A, SAVED_SCSIID;
1134: cmp SCB_SCSIID, A jne verify_other_scb;
1135: mov A, SAVED_LUN;
1136: cmp SCB_LUN, A je setup_SCB_disconnected;
1137: verify_other_scb:
1138: xor SCBPTR[1], 1;
1139: test SCBPTR[1], 0xFF jnz verify_scb;
1140: jmp not_found;
1141:
1142: /*
1143: * Ensure that the SCB the tag points to is for
1144: * an SCB transaction to the reconnecting target.
1145: */
1146: setup_SCB:
1147: if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
1148: or SEQ_FLAGS, 0x10;
1149: }
1150: test SCB_CONTROL,DISCONNECTED jz not_found;
1151: setup_SCB_disconnected:
1152: and SCB_CONTROL,~DISCONNECTED;
1153: clr SEQ_FLAGS; /* make note of IDENTIFY */
1154: test SCB_SGPTR, SG_LIST_NULL jnz . + 3;
1155: bmov ALLOCFIFO_SCBPTR, SCBPTR, 2;
1156: call allocate_fifo;
1157: /* See if the host wants to send a message upon reconnection */
1158: test SCB_CONTROL, MK_MESSAGE jz mesgin_done;
1159: mvi HOST_MSG call mk_mesg;
1160: jmp mesgin_done;
1161:
1162: not_found:
1163: SET_SEQINTCODE(NO_MATCH)
1164: jmp mesgin_done;
1165:
1166: not_found_ITloop:
1167: SET_SEQINTCODE(NO_MATCH)
1168: jmp ITloop;
1169:
1170: /*
1171: * We received a "command complete" message. Put the SCB on the complete
1172: * queue and trigger a completion interrupt via the idle loop. Before doing
1173: * so, check to see if there is a residual or the status byte is something
1174: * other than STATUS_GOOD (0). In either of these conditions, we upload the
1175: * SCB back to the host so it can process this information.
1176: */
1177: mesgin_complete:
1178:
1179: /*
1180: * If ATN is raised, we still want to give the target a message.
1181: * Perhaps there was a parity error on this last message byte.
1182: * Either way, the target should take us to message out phase
1183: * and then attempt to complete the command again. We should use a
1184: * critical section here to guard against a timeout triggering
1185: * for this command and setting ATN while we are still processing
1186: * the completion.
1187: test SCSISIGI, ATNI jnz mesgin_done;
1188: */
1189:
1190: /*
1191: * If we are identified and have successfully sent the CDB,
1192: * any status will do. Optimize this fast path.
1193: */
1194: test SCB_CONTROL, STATUS_RCVD jz mesgin_proto_violation;
1195: test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz complete_accepted;
1196:
1197: /*
1198: * If the target never sent an identify message but instead went
1199: * to mesgin to give an invalid message, let the host abort us.
1200: */
1201: test SEQ_FLAGS, NOT_IDENTIFIED jnz mesgin_proto_violation;
1202:
1203: /*
1204: * If we received good status but never successfully sent the
1205: * cdb, abort the command.
1206: */
1207: test SCB_SCSI_STATUS,0xff jnz complete_accepted;
1208: test SEQ_FLAGS, NO_CDB_SENT jnz mesgin_proto_violation;
1209: complete_accepted:
1210:
1211: /*
1212: * See if we attempted to deliver a message but the target ingnored us.
1213: */
1214: test SCB_CONTROL, MK_MESSAGE jz complete_nomsg;
1215: SET_SEQINTCODE(MKMSG_FAILED)
1216: complete_nomsg:
1217: call queue_scb_completion;
1218: jmp await_busfree;
1219:
1220: BEGIN_CRITICAL;
1221: freeze_queue:
1222: /* Cancel any pending select-out. */
1223: test SSTAT0, SELDO|SELINGO jnz . + 2;
1224: and SCSISEQ0, ~ENSELO;
1225: mov ACCUM_SAVE, A;
1226: clr A;
1227: add QFREEZE_COUNT, 1;
1228: adc QFREEZE_COUNT[1], A;
1229: or SEQ_FLAGS2, SELECTOUT_QFROZEN;
1230: mov A, ACCUM_SAVE ret;
1231: END_CRITICAL;
1232:
1233: /*
1234: * Complete the current FIFO's SCB if data for this same
1235: * SCB is not transferring in the other FIFO.
1236: */
1237: SET_SRC_MODE M_DFF1;
1238: SET_DST_MODE M_DFF1;
1239: pkt_complete_scb_if_fifos_idle:
1240: bmov ARG_1, SCBPTR, 2;
1241: mvi DFFSXFRCTL, CLRCHN;
1242: SET_MODE(M_SCSI, M_SCSI)
1243: bmov SCBPTR, ARG_1, 2;
1244: test SCB_FIFO_USE_COUNT, 0xFF jnz return;
1245: queue_scb_completion:
1246: test SCB_SCSI_STATUS,0xff jnz bad_status;
1247: /*
1248: * Check for residuals
1249: */
1250: test SCB_SGPTR, SG_LIST_NULL jnz complete; /* No xfer */
1251: test SCB_SGPTR, SG_FULL_RESID jnz upload_scb;/* Never xfered */
1252: test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jz upload_scb;
1253: complete:
1254: BEGIN_CRITICAL;
1255: bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
1256: bmov COMPLETE_SCB_HEAD, SCBPTR, 2 ret;
1257: END_CRITICAL;
1258: bad_status:
1259: cmp SCB_SCSI_STATUS, STATUS_PKT_SENSE je upload_scb;
1260: call freeze_queue;
1261: upload_scb:
1262: /*
1263: * Restore SCB TAG since we reuse this field
1264: * in the sequencer. We don't want to corrupt
1265: * it on the host.
1266: */
1267: bmov SCB_TAG, SCBPTR, 2;
1268: BEGIN_CRITICAL;
1269: or SCB_SGPTR, SG_STATUS_VALID;
1270: mvi SCB_NEXT_COMPLETE[1], SCB_LIST_NULL;
1271: cmp COMPLETE_DMA_SCB_HEAD[1], SCB_LIST_NULL jne add_dma_scb_tail;
1272: bmov COMPLETE_DMA_SCB_HEAD, SCBPTR, 2;
1273: bmov COMPLETE_DMA_SCB_TAIL, SCBPTR, 2 ret;
1274: add_dma_scb_tail:
1275: bmov REG0, SCBPTR, 2;
1276: bmov SCBPTR, COMPLETE_DMA_SCB_TAIL, 2;
1277: bmov SCB_NEXT_COMPLETE, REG0, 2;
1278: bmov COMPLETE_DMA_SCB_TAIL, REG0, 2 ret;
1279: END_CRITICAL;
1280:
1281: /*
1282: * Is it a disconnect message? Set a flag in the SCB to remind us
1283: * and await the bus going free. If this is an untagged transaction
1284: * store the SCB id for it in our untagged target table for lookup on
1285: * a reselection.
1286: */
1287: mesgin_disconnect:
1288: /*
1289: * If ATN is raised, we still want to give the target a message.
1290: * Perhaps there was a parity error on this last message byte
1291: * or we want to abort this command. Either way, the target
1292: * should take us to message out phase and then attempt to
1293: * disconnect again.
1294: * XXX - Wait for more testing.
1295: test SCSISIGI, ATNI jnz mesgin_done;
1296: */
1297: test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT
1298: jnz mesgin_proto_violation;
1299: or SCB_CONTROL,DISCONNECTED;
1300: test SCB_CONTROL, TAG_ENB jnz await_busfree;
1301: queue_disc_scb:
1302: bmov REG0, SCBPTR, 2;
1303: INDEX_DISC_LIST(SAVED_SCSIID, SAVED_LUN);
1304: bmov DINDEX, SINDEX, 2;
1305: bmov DINDIR, REG0, 2;
1306: bmov SCBPTR, REG0, 2;
1307: /* FALLTHROUGH */
1308: await_busfree:
1309: and SIMODE1, ~ENBUSFREE;
1310: if ((ahd->bugs & AHD_BUSFREEREV_BUG) == 0) {
1311: /*
1312: * In the BUSFREEREV_BUG case, the
1313: * busfree status was cleared at the
1314: * beginning of the connection.
1315: */
1316: mvi CLRSINT1,CLRBUSFREE;
1317: }
1318: mov NONE, SCSIDAT; /* Ack the last byte */
1319: test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
1320: jnz await_busfree_not_m_dff;
1321: SET_SRC_MODE M_DFF1;
1322: SET_DST_MODE M_DFF1;
1323: await_busfree_clrchn:
1324: mvi DFFSXFRCTL, CLRCHN;
1325: await_busfree_not_m_dff:
1326: /* clear target specific flags */
1327: mvi SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT;
1328: test SSTAT1,REQINIT|BUSFREE jz .;
1329: /*
1330: * We only set BUSFREE status once either a new
1331: * phase has been detected or we are really
1332: * BUSFREE. This allows the driver to know
1333: * that we are active on the bus even though
1334: * no identified transaction exists should a
1335: * timeout occur while awaiting busfree.
1336: */
1337: mvi LASTPHASE, P_BUSFREE;
1338: test SSTAT1, BUSFREE jnz idle_loop;
1339: SET_SEQINTCODE(MISSED_BUSFREE)
1340:
1341:
1342: /*
1343: * Save data pointers message:
1344: * Copying RAM values back to SCB, for Save Data Pointers message, but
1345: * only if we've actually been into a data phase to change them. This
1346: * protects against bogus data in scratch ram and the residual counts
1347: * since they are only initialized when we go into data_in or data_out.
1348: * Ack the message as soon as possible.
1349: */
1350: SET_SRC_MODE M_DFF1;
1351: SET_DST_MODE M_DFF1;
1352: mesgin_sdptrs:
1353: mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
1354: test SEQ_FLAGS, DPHASE jz ITloop;
1355: call save_pointers;
1356: jmp ITloop;
1357:
1358: save_pointers:
1359: /*
1360: * If we are asked to save our position at the end of the
1361: * transfer, just mark us at the end rather than perform a
1362: * full save.
1363: */
1364: test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz save_pointers_full;
1365: or SCB_SGPTR, SG_LIST_NULL ret;
1366:
1367: save_pointers_full:
1368: /*
1369: * The SCB_DATAPTR becomes the current SHADDR.
1370: * All other information comes directly from our residual
1371: * state.
1372: */
1373: bmov SCB_DATAPTR, SHADDR, 8;
1374: bmov SCB_DATACNT, SCB_RESIDUAL_DATACNT, 8 ret;
1375:
1376: /*
1377: * Restore pointers message? Data pointers are recopied from the
1378: * SCB anytime we enter a data phase for the first time, so all
1379: * we need to do is clear the DPHASE flag and let the data phase
1380: * code do the rest. We also reset/reallocate the FIFO to make
1381: * sure we have a clean start for the next data or command phase.
1382: */
1383: mesgin_rdptrs:
1384: and SEQ_FLAGS, ~DPHASE;
1385: test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1)) jnz msgin_rdptrs_get_fifo;
1386: mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
1387: SET_MODE(M_SCSI, M_SCSI)
1388: msgin_rdptrs_get_fifo:
1389: call allocate_fifo;
1390: jmp mesgin_done;
1391:
1392: phase_lock:
1393: if ((ahd->bugs & AHD_EARLY_REQ_BUG) != 0) {
1394: /*
1395: * Don't ignore persistent REQ assertions just because
1396: * they were asserted within the bus settle delay window.
1397: * This allows us to tolerate devices like the GEM318
1398: * that violate the SCSI spec. We are careful not to
1399: * count REQ while we are waiting for it to fall during
1400: * an async phase due to our asserted ACK. Each
1401: * sequencer instruction takes ~25ns, so the REQ must
1402: * last at least 100ns in order to be counted as a true
1403: * REQ.
1404: */
1405: test SCSIPHASE, 0xFF jnz phase_locked;
1406: test SCSISIGI, ACKI jnz phase_lock;
1407: test SCSISIGI, REQI jz phase_lock;
1408: test SCSIPHASE, 0xFF jnz phase_locked;
1409: test SCSISIGI, ACKI jnz phase_lock;
1410: test SCSISIGI, REQI jz phase_lock;
1411: phase_locked:
1412: } else {
1413: test SCSIPHASE, 0xFF jz .;
1414: }
1415: test SSTAT1, SCSIPERR jnz phase_lock;
1416: phase_lock_latch_phase:
1417: and LASTPHASE, PHASE_MASK, SCSISIGI ret;
1418:
1419: /*
1420: * Functions to read data in Automatic PIO mode.
1421: *
1422: * An ACK is not sent on input from the target until SCSIDATL is read from.
1423: * So we wait until SCSIDATL is latched (the usual way), then read the data
1424: * byte directly off the bus using SCSIBUSL. When we have pulled the ATN
1425: * line, or we just want to acknowledge the byte, then we do a dummy read
1426: * from SCISDATL. The SCSI spec guarantees that the target will hold the
1427: * data byte on the bus until we send our ACK.
1428: *
1429: * The assumption here is that these are called in a particular sequence,
1430: * and that REQ is already set when inb_first is called. inb_{first,next}
1431: * use the same calling convention as inb.
1432: */
1433: inb_next:
1434: mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
1435: inb_next_wait:
1436: /*
1437: * If there is a parity error, wait for the kernel to
1438: * see the interrupt and prepare our message response
1439: * before continuing.
1440: */
1441: test SCSIPHASE, 0xFF jz .;
1442: test SSTAT1, SCSIPERR jnz inb_next_wait;
1443: inb_next_check_phase:
1444: and LASTPHASE, PHASE_MASK, SCSISIGI;
1445: cmp LASTPHASE, P_MESGIN jne mesgin_phasemis;
1446: inb_first:
1447: clr DINDEX[1];
1448: mov DINDEX,SINDEX;
1449: mov DINDIR,SCSIBUS ret; /*read byte directly from bus*/
1450: inb_last:
1451: mov NONE,SCSIDAT ret; /*dummy read from latch to ACK*/
1452:
1453: mk_mesg:
1454: mvi SCSISIGO, ATNO;
1455: mov MSG_OUT,SINDEX ret;
1456:
1457: SET_SRC_MODE M_DFF1;
1458: SET_DST_MODE M_DFF1;
1459: disable_ccsgen:
1460: test SG_STATE, FETCH_INPROG jz disable_ccsgen_fetch_done;
1461: clr CCSGCTL;
1462: disable_ccsgen_fetch_done:
1463: clr SG_STATE ret;
1464:
1465: service_fifo:
1466: /*
1467: * Do we have any prefetch left???
1468: */
1469: test SG_STATE, SEGS_AVAIL jnz idle_sg_avail;
1470:
1471: /*
1472: * Can this FIFO have access to the S/G cache yet?
1473: */
1474: test CCSGCTL, SG_CACHE_AVAIL jz return;
1475:
1476: /* Did we just finish fetching segs? */
1477: test CCSGCTL, CCSGDONE jnz idle_sgfetch_complete;
1478:
1479: /* Are we actively fetching segments? */
1480: test CCSGCTL, CCSGENACK jnz return;
1481:
1482: /*
1483: * Should the other FIFO get the S/G cache first? If
1484: * both FIFOs have been allocated since we last checked
1485: * any FIFO, it is important that we service a FIFO
1486: * that is not actively on the bus first. This guarantees
1487: * that a FIFO will be freed to handle snapshot requests for
1488: * any FIFO that is still on the bus. Chips with RTI do not
1489: * perform snapshots, so don't bother with this test there.
1490: */
1491: if ((ahd->features & AHD_RTI) == 0) {
1492: /*
1493: * If we're not still receiving SCSI data,
1494: * it is safe to allocate the S/G cache to
1495: * this FIFO.
1496: */
1497: test DFCNTRL, SCSIEN jz idle_sgfetch_start;
1498:
1499: /*
1500: * Switch to the other FIFO. Non-RTI chips
1501: * also have the "set mode" bug, so we must
1502: * disable interrupts during the switch.
1503: */
1504: mvi SEQINTCTL, INTVEC1DSL;
1505: xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
1506:
1507: /*
1508: * If the other FIFO needs loading, then it
1509: * must not have claimed the S/G cache yet
1510: * (SG_CACHE_AVAIL would have been cleared in
1511: * the original FIFO mode and we test this above).
1512: * Return to the idle loop so we can process the
1513: * FIFO not currently on the bus first.
1514: */
1515: test SG_STATE, LOADING_NEEDED jz idle_sgfetch_okay;
1516: clr SEQINTCTL ret;
1517: idle_sgfetch_okay:
1518: xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
1519: clr SEQINTCTL;
1520: }
1521:
1522: idle_sgfetch_start:
1523: /*
1524: * We fetch a "cacheline aligned" and sized amount of data
1525: * so we don't end up referencing a non-existant page.
1526: * Cacheline aligned is in quotes because the kernel will
1527: * set the prefetch amount to a reasonable level if the
1528: * cacheline size is unknown.
1529: */
1530: bmov SGHADDR, SCB_RESIDUAL_SGPTR, 4;
1531: mvi SGHCNT, SG_PREFETCH_CNT;
1532: if ((ahd->bugs & AHD_REG_SLOW_SETTLE_BUG) != 0) {
1533: /*
1534: * Need two instructions between "touches" of SGHADDR.
1535: */
1536: nop;
1537: }
1538: and SGHADDR[0], SG_PREFETCH_ALIGN_MASK, SCB_RESIDUAL_SGPTR;
1539: mvi CCSGCTL, CCSGEN|CCSGRESET;
1540: or SG_STATE, FETCH_INPROG ret;
1541: idle_sgfetch_complete:
1542: /*
1543: * Guard against SG_CACHE_AVAIL activating during sg fetch
1544: * request in the other FIFO.
1545: */
1546: test SG_STATE, FETCH_INPROG jz return;
1547: clr CCSGCTL;
1548: and CCSGADDR, SG_PREFETCH_ADDR_MASK, SCB_RESIDUAL_SGPTR;
1549: mvi SG_STATE, SEGS_AVAIL|LOADING_NEEDED;
1550: idle_sg_avail:
1551: /* Does the hardware have space for another SG entry? */
1552: test DFSTATUS, PRELOAD_AVAIL jz return;
1553: /*
1554: * On the A, preloading a segment before HDMAENACK
1555: * comes true can clobber the shadow address of the
1556: * first segment in the S/G FIFO. Wait until it is
1557: * safe to proceed.
1558: */
1559: if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) == 0) {
1560: test DFCNTRL, HDMAENACK jz return;
1561: }
1562: if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
1563: bmov HADDR, CCSGRAM, 8;
1564: } else {
1565: bmov HADDR, CCSGRAM, 4;
1566: }
1567: bmov HCNT, CCSGRAM, 3;
1568: bmov SCB_RESIDUAL_DATACNT[3], CCSGRAM, 1;
1569: if ((ahd->flags & AHD_39BIT_ADDRESSING) != 0) {
1570: and HADDR[4], SG_HIGH_ADDR_BITS, SCB_RESIDUAL_DATACNT[3];
1571: }
1572: if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
1573: /* Skip 4 bytes of pad. */
1574: add CCSGADDR, 4;
1575: }
1576: sg_advance:
1577: clr A; /* add sizeof(struct scatter) */
1578: add SCB_RESIDUAL_SGPTR[0],SG_SIZEOF;
1579: adc SCB_RESIDUAL_SGPTR[1],A;
1580: adc SCB_RESIDUAL_SGPTR[2],A;
1581: adc SCB_RESIDUAL_SGPTR[3],A;
1582: mov SINDEX, SCB_RESIDUAL_SGPTR[0];
1583: test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 3;
1584: or SINDEX, LAST_SEG;
1585: clr SG_STATE;
1586: mov SG_CACHE_PRE, SINDEX;
1587: if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) != 0) {
1588: /*
1589: * Use SCSIENWRDIS so that SCSIEN is never
1590: * modified by this operation.
1591: */
1592: or DFCNTRL, PRELOADEN|HDMAEN|SCSIENWRDIS;
1593: } else {
1594: or DFCNTRL, PRELOADEN|HDMAEN;
1595: }
1596: /*
1597: * Do we have another segment in the cache?
1598: */
1599: add NONE, SG_PREFETCH_CNT_LIMIT, CCSGADDR;
1600: jnc return;
1601: and SG_STATE, ~SEGS_AVAIL ret;
1602:
1603: /*
1604: * Initialize the DMA address and counter from the SCB.
1605: */
1606: load_first_seg:
1607: bmov HADDR, SCB_DATAPTR, 11;
1608: and REG_ISR, ~SG_FULL_RESID, SCB_SGPTR[0];
1609: test SCB_DATACNT[3], SG_LAST_SEG jz . + 2;
1610: or REG_ISR, LAST_SEG;
1611: mov SG_CACHE_PRE, REG_ISR;
1612: mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
1613: /*
1614: * Since we've are entering a data phase, we will
1615: * rely on the SCB_RESID* fields. Initialize the
1616: * residual and clear the full residual flag.
1617: */
1618: and SCB_SGPTR[0], ~SG_FULL_RESID;
1619: bmov SCB_RESIDUAL_DATACNT[3], SCB_DATACNT[3], 5;
1620: /* If we need more S/G elements, tell the idle loop */
1621: test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jnz . + 2;
1622: mvi SG_STATE, LOADING_NEEDED ret;
1623: clr SG_STATE ret;
1624:
1625: p_data_handle_xfer:
1626: call setjmp;
1627: test SG_STATE, LOADING_NEEDED jnz service_fifo;
1628: p_data_clear_handler:
1629: or LONGJMP_ADDR[1], INVALID_ADDR ret;
1630:
1631: p_data:
1632: test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz p_data_allowed;
1633: SET_SEQINTCODE(PROTO_VIOLATION)
1634: p_data_allowed:
1635:
1636: test SEQ_FLAGS, DPHASE jz data_phase_initialize;
1637:
1638: /*
1639: * If we re-enter the data phase after going through another
1640: * phase, our transfer location has almost certainly been
1641: * corrupted by the interveining, non-data, transfers. Ask
1642: * the host driver to fix us up based on the transfer residual
1643: * unless we already know that we should be bitbucketing.
1644: */
1645: test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jnz p_data_bitbucket;
1646: SET_SEQINTCODE(PDATA_REINIT)
1647: jmp data_phase_inbounds;
1648:
1649: p_data_bitbucket:
1650: /*
1651: * Turn on `Bit Bucket' mode, wait until the target takes
1652: * us to another phase, and then notify the host.
1653: */
1654: mov SAVED_MODE, MODE_PTR;
1655: test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
1656: jnz bitbucket_not_m_dff;
1657: /*
1658: * Ensure that any FIFO contents are cleared out and the
1659: * FIFO free'd prior to starting the BITBUCKET. BITBUCKET
1660: * doesn't discard data already in the FIFO.
1661: */
1662: mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
1663: SET_MODE(M_SCSI, M_SCSI)
1664: bitbucket_not_m_dff:
1665: or SXFRCTL1,BITBUCKET;
1666: /* Wait for non-data phase. */
1667: test SCSIPHASE, ~DATA_PHASE_MASK jz .;
1668: and SXFRCTL1, ~BITBUCKET;
1669: RESTORE_MODE(SAVED_MODE)
1670: SET_SRC_MODE M_DFF1;
1671: SET_DST_MODE M_DFF1;
1672: SET_SEQINTCODE(DATA_OVERRUN)
1673: jmp ITloop;
1674:
1675: data_phase_initialize:
1676: test SCB_SGPTR[0], SG_LIST_NULL jnz p_data_bitbucket;
1677: call load_first_seg;
1678: data_phase_inbounds:
1679: /* We have seen a data phase at least once. */
1680: or SEQ_FLAGS, DPHASE;
1681: mov SAVED_MODE, MODE_PTR;
1682: test SG_STATE, LOADING_NEEDED jz data_group_dma_loop;
1683: call p_data_handle_xfer;
1684: data_group_dma_loop:
1685: /*
1686: * The transfer is complete if either the last segment
1687: * completes or the target changes phase. Both conditions
1688: * will clear SCSIEN.
1689: */
1690: call idle_loop_service_fifos;
1691: call idle_loop_cchan;
1692: call idle_loop_gsfifo;
1693: RESTORE_MODE(SAVED_MODE)
1694: test DFCNTRL, SCSIEN jnz data_group_dma_loop;
1695:
1696: data_group_dmafinish:
1697: /*
1698: * The transfer has terminated either due to a phase
1699: * change, and/or the completion of the last segment.
1700: * We have two goals here. Do as much other work
1701: * as possible while the data fifo drains on a read
1702: * and respond as quickly as possible to the standard
1703: * messages (save data pointers/disconnect and command
1704: * complete) that usually follow a data phase.
1705: */
1706: call calc_residual;
1707:
1708: /*
1709: * Go ahead and shut down the DMA engine now.
1710: */
1711: test DFCNTRL, DIRECTION jnz data_phase_finish;
1712: data_group_fifoflush:
1713: if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
1714: or DFCNTRL, FIFOFLUSH;
1715: }
1716: /*
1717: * We have enabled the auto-ack feature. This means
1718: * that the controller may have already transferred
1719: * some overrun bytes into the data FIFO and acked them
1720: * on the bus. The only way to detect this situation is
1721: * to wait for LAST_SEG_DONE to come true on a completed
1722: * transfer and then test to see if the data FIFO is
1723: * non-empty. We know there is more data yet to transfer
1724: * if SG_LIST_NULL is not yet set, thus there cannot be
1725: * an overrun.
1726: */
1727: test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz data_phase_finish;
1728: test SG_CACHE_SHADOW, LAST_SEG_DONE jz .;
1729: test DFSTATUS, FIFOEMP jnz data_phase_finish;
1730: /* Overrun */
1731: jmp p_data;
1732: data_phase_finish:
1733: /*
1734: * If the target has left us in data phase, loop through
1735: * the dma code again. We will only loop if there is a
1736: * data overrun.
1737: */
1738: if ((ahd->flags & AHD_TARGETROLE) != 0) {
1739: test SSTAT0, TARGET jnz data_phase_done;
1740: }
1741: if ((ahd->flags & AHD_INITIATORROLE) != 0) {
1742: test SSTAT1, REQINIT jz .;
1743: test SCSIPHASE, DATA_PHASE_MASK jnz p_data;
1744: }
1745:
1746: data_phase_done:
1747: /* Kill off any pending prefetch */
1748: call disable_ccsgen;
1749: or LONGJMP_ADDR[1], INVALID_ADDR;
1750:
1751: if ((ahd->flags & AHD_TARGETROLE) != 0) {
1752: test SEQ_FLAGS, DPHASE_PENDING jz ITloop;
1753: /*
1754: and SEQ_FLAGS, ~DPHASE_PENDING;
1755: * For data-in phases, wait for any pending acks from the
1756: * initiator before changing phase. We only need to
1757: * send Ignore Wide Residue messages for data-in phases.
1758: test DFCNTRL, DIRECTION jz target_ITloop;
1759: test SSTAT1, REQINIT jnz .;
1760: test SCB_TASK_ATTRIBUTE, SCB_XFERLEN_ODD jz target_ITloop;
1761: SET_MODE(M_SCSI, M_SCSI)
1762: test NEGCONOPTS, WIDEXFER jz target_ITloop;
1763: */
1764: /*
1765: * Issue an Ignore Wide Residue Message.
1766: mvi P_MESGIN|BSYO call change_phase;
1767: mvi MSG_IGN_WIDE_RESIDUE call target_outb;
1768: mvi 1 call target_outb;
1769: jmp target_ITloop;
1770: */
1771: } else {
1772: jmp ITloop;
1773: }
1774:
1775: /*
1776: * We assume that, even though data may still be
1777: * transferring to the host, that the SCSI side of
1778: * the DMA engine is now in a static state. This
1779: * allows us to update our notion of where we are
1780: * in this transfer.
1781: *
1782: * If, by chance, we stopped before being able
1783: * to fetch additional segments for this transfer,
1784: * yet the last S/G was completely exhausted,
1785: * call our idle loop until it is able to load
1786: * another segment. This will allow us to immediately
1787: * pickup on the next segment on the next data phase.
1788: *
1789: * If we happened to stop on the last segment, then
1790: * our residual information is still correct from
1791: * the idle loop and there is no need to perform
1792: * any fixups.
1793: */
1794: residual_before_last_seg:
1795: test MDFFSTAT, SHVALID jnz sgptr_fixup;
1796: /*
1797: * Can never happen from an interrupt as the packetized
1798: * hardware will only interrupt us once SHVALID or
1799: * LAST_SEG_DONE.
1800: */
1801: call idle_loop_service_fifos;
1802: RESTORE_MODE(SAVED_MODE)
1803: /* FALLTHROUGH */
1804: calc_residual:
1805: test SG_CACHE_SHADOW, LAST_SEG jz residual_before_last_seg;
1806: /* Record if we've consumed all S/G entries */
1807: test MDFFSTAT, SHVALID jz . + 2;
1808: bmov SCB_RESIDUAL_DATACNT, SHCNT, 3 ret;
1809: or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL ret;
1810:
1811: sgptr_fixup:
1812: /*
1813: * Fixup the residual next S/G pointer. The S/G preload
1814: * feature of the chip allows us to load two elements
1815: * in addition to the currently active element. We
1816: * store the bottom byte of the next S/G pointer in
1817: * the SG_CACHE_PTR register so we can restore the
1818: * correct value when the DMA completes. If the next
1819: * sg ptr value has advanced to the point where higher
1820: * bytes in the address have been affected, fix them
1821: * too.
1822: */
1823: test SG_CACHE_SHADOW, 0x80 jz sgptr_fixup_done;
1824: test SCB_RESIDUAL_SGPTR[0], 0x80 jnz sgptr_fixup_done;
1825: add SCB_RESIDUAL_SGPTR[1], -1;
1826: adc SCB_RESIDUAL_SGPTR[2], -1;
1827: adc SCB_RESIDUAL_SGPTR[3], -1;
1828: sgptr_fixup_done:
1829: and SCB_RESIDUAL_SGPTR[0], SG_ADDR_MASK, SG_CACHE_SHADOW;
1830: clr SCB_RESIDUAL_DATACNT[3]; /* We are not the last seg */
1831: bmov SCB_RESIDUAL_DATACNT, SHCNT, 3 ret;
1832:
1833: export timer_isr:
1834: call issue_cmdcmplt;
1835: mvi CLRSEQINTSTAT, CLRSEQ_SWTMRTO;
1836: if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) {
1837: /*
1838: * In H2A4, the mode pointer is not saved
1839: * for intvec2, but is restored on iret.
1840: * This can lead to the restoration of a
1841: * bogus mode ptr. Manually clear the
1842: * intmask bits and do a normal return
1843: * to compensate.
1844: */
1845: and SEQINTCTL, ~(INTMASK2|INTMASK1) ret;
1846: } else {
1847: or SEQINTCTL, IRET ret;
1848: }
1849:
1850: export seq_isr:
1851: if ((ahd->features & AHD_RTI) == 0) {
1852: /*
1853: * On RevA Silicon, if the target returns us to data-out
1854: * after we have already trained for data-out, it is
1855: * possible for us to transition the free running clock to
1856: * data-valid before the required 100ns P1 setup time (8 P1
1857: * assertions in fast-160 mode). This will only happen if
1858: * this L-Q is a continuation of a data transfer for which
1859: * we have already prefetched data into our FIFO (LQ/Data
1860: * followed by LQ/Data for the same write transaction).
1861: * This can cause some target implementations to miss the
1862: * first few data transfers on the bus. We detect this
1863: * situation by noticing that this is the first data transfer
1864: * after an LQ (LQIWORKONLQ true), that the data transfer is
1865: * a continuation of a transfer already setup in our FIFO
1866: * (SAVEPTRS interrupt), and that the transaction is a write
1867: * (DIRECTION set in DFCNTRL). The delay is performed by
1868: * disabling SCSIEN until we see the first REQ from the
1869: * target.
1870: *
1871: * First instruction in an ISR cannot be a branch on
1872: * Rev A. Snapshot LQISTAT2 so the status is not missed
1873: * and deffer the test by one instruction.
1874: */
1875: mov REG_ISR, LQISTAT2;
1876: test REG_ISR, LQIWORKONLQ jz main_isr;
1877: test SEQINTSRC, SAVEPTRS jz main_isr;
1878: test LONGJMP_ADDR[1], INVALID_ADDR jz saveptr_active_fifo;
1879: /*
1880: * Switch to the active FIFO after clearing the snapshot
1881: * savepointer in the current FIFO. We do this so that
1882: * a pending CTXTDONE or SAVEPTR is visible in the active
1883: * FIFO. This status is the only way we can detect if we
1884: * have lost the race (e.g. host paused us) and our attempts
1885: * to disable the channel occurred after all REQs were
1886: * already seen and acked (REQINIT never comes true).
1887: */
1888: mvi DFFSXFRCTL, CLRCHN;
1889: xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
1890: test DFCNTRL, DIRECTION jz interrupt_return;
1891: and DFCNTRL, ~SCSIEN;
1892: snapshot_wait_data_valid:
1893: test SEQINTSRC, (CTXTDONE|SAVEPTRS) jnz interrupt_return;
1894: test SSTAT1, REQINIT jz snapshot_wait_data_valid;
1895: snapshot_data_valid:
1896: or DFCNTRL, SCSIEN;
1897: or SEQINTCTL, IRET ret;
1898: snapshot_saveptr:
1899: mvi DFFSXFRCTL, CLRCHN;
1900: or SEQINTCTL, IRET ret;
1901: main_isr:
1902: }
1903: test SEQINTSRC, CFG4DATA jnz cfg4data_intr;
1904: test SEQINTSRC, CFG4ISTAT jnz cfg4istat_intr;
1905: test SEQINTSRC, SAVEPTRS jnz saveptr_intr;
1906: test SEQINTSRC, CFG4ICMD jnz cfg4icmd_intr;
1907: SET_SEQINTCODE(INVALID_SEQINT)
1908:
1909: /*
1910: * There are two types of save pointers interrupts:
1911: * The first is a snapshot save pointers where the current FIFO is not
1912: * active and contains a snapshot of the current pointer information.
1913: * This happens between packets in a stream for a single L_Q. Since we
1914: * are not performing a pointer save, we can safely clear the channel
1915: * so it can be used for other transactions. On RTI capable controllers,
1916: * where snapshots can be, and are, disabled, the code to handle this type
1917: * of snapshot is not active.
1918: *
1919: * The second case is a save pointers on an active FIFO which occurs
1920: * if the target changes to a new L_Q or busfrees/QASes and the transfer
1921: * has a residual. This should occur coincident with a ctxtdone. We
1922: * disable the interrupt and allow our active routine to handle the
1923: * save.
1924: */
1925: saveptr_intr:
1926: if ((ahd->features & AHD_RTI) == 0) {
1927: test LONGJMP_ADDR[1], INVALID_ADDR jnz snapshot_saveptr;
1928: }
1929: saveptr_active_fifo:
1930: and SEQIMODE, ~ENSAVEPTRS;
1931: or SEQINTCTL, IRET ret;
1932:
1933: cfg4data_intr:
1934: test SCB_SGPTR[0], SG_LIST_NULL jnz pkt_handle_overrun_inc_use_count;
1935: call load_first_seg;
1936: call pkt_handle_xfer;
1937: inc SCB_FIFO_USE_COUNT;
1938: interrupt_return:
1939: or SEQINTCTL, IRET ret;
1940:
1941: cfg4istat_intr:
1942: call freeze_queue;
1943: add NONE, -13, SCB_CDB_LEN;
1944: jnc cfg4istat_have_sense_addr;
1945: test SCB_CDB_LEN, SCB_CDB_LEN_PTR jnz cfg4istat_have_sense_addr;
1946: /*
1947: * Host sets up address/count and enables transfer.
1948: */
1949: SET_SEQINTCODE(CFG4ISTAT_INTR)
1950: jmp cfg4istat_setup_handler;
1951: cfg4istat_have_sense_addr:
1952: bmov HADDR, SCB_SENSE_BUSADDR, 4;
1953: mvi HCNT[1], (AHD_SENSE_BUFSIZE >> 8);
1954: mvi SG_CACHE_PRE, LAST_SEG;
1955: mvi DFCNTRL, PRELOADEN|SCSIEN|HDMAEN;
1956: cfg4istat_setup_handler:
1957: /*
1958: * Status pkt is transferring to host.
1959: * Wait in idle loop for transfer to complete.
1960: * If a command completed before an attempted
1961: * task management function completed, notify the host.
1962: */
1963: test SCB_TASK_MANAGEMENT, 0xFF jz cfg4istat_no_taskmgmt_func;
1964: SET_SEQINTCODE(TASKMGMT_CMD_CMPLT_OKAY)
1965: cfg4istat_no_taskmgmt_func:
1966: call pkt_handle_status;
1967: or SEQINTCTL, IRET ret;
1968:
1969: cfg4icmd_intr:
1970: /*
1971: * In the case of DMAing a CDB from the host, the normal
1972: * CDB buffer is formatted with an 8 byte address followed
1973: * by a 1 byte count.
1974: */
1975: bmov HADDR[0], SCB_HOST_CDB_PTR, 9;
1976: mvi SG_CACHE_PRE, LAST_SEG;
1977: mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
1978: call pkt_handle_cdb;
1979: or SEQINTCTL, IRET ret;
1980:
1981: /*
1982: * See if the target has gone on in this context creating an
1983: * overrun condition. For the write case, the hardware cannot
1984: * ack bytes until data are provided. So, if the target begins
1985: * another packet without changing contexts, implying we are
1986: * not sitting on a packet boundary, we are in an overrun
1987: * situation. For the read case, the hardware will continue to
1988: * ack bytes into the FIFO, and may even ack the last overrun packet
1989: * into the FIFO. If the FIFO should become non-empty, we are in
1990: * a read overrun case.
1991: */
1992: #define check_overrun \
1993: /* Not on a packet boundary. */ \
1994: test MDFFSTAT, DLZERO jz pkt_handle_overrun; \
1995: test DFSTATUS, FIFOEMP jz pkt_handle_overrun
1996:
1997: pkt_handle_xfer:
1998: test SG_STATE, LOADING_NEEDED jz pkt_last_seg;
1999: call setjmp;
2000: test SEQINTSRC, SAVEPTRS jnz pkt_saveptrs;
2001: test SCSIPHASE, ~DATA_PHASE_MASK jz . + 2;
2002: test SCSISIGO, ATNO jnz . + 2;
2003: test SSTAT2, NONPACKREQ jz pkt_service_fifo;
2004: /*
2005: * Defer handling of this NONPACKREQ until we
2006: * can be sure it pertains to this FIFO. SAVEPTRS
2007: * will not be asserted if the NONPACKREQ is for us,
2008: * so we must simulate it if shadow is valid. If
2009: * shadow is not valid, keep running this FIFO until we
2010: * have satisfied the transfer by loading segments and
2011: * waiting for either shadow valid or last_seg_done.
2012: */
2013: test MDFFSTAT, SHVALID jnz pkt_saveptrs;
2014: pkt_service_fifo:
2015: test SG_STATE, LOADING_NEEDED jnz service_fifo;
2016: pkt_last_seg:
2017: call setjmp;
2018: test SEQINTSRC, SAVEPTRS jnz pkt_saveptrs;
2019: test SG_CACHE_SHADOW, LAST_SEG_DONE jnz pkt_last_seg_done;
2020: test SCSIPHASE, ~DATA_PHASE_MASK jz . + 2;
2021: test SCSISIGO, ATNO jnz . + 2;
2022: test SSTAT2, NONPACKREQ jz return;
2023: test MDFFSTAT, SHVALID jz return;
2024: /* FALLTHROUGH */
2025:
2026: /*
2027: * Either a SAVEPTRS interrupt condition is pending for this FIFO
2028: * or we have a pending NONPACKREQ for this FIFO. We differentiate
2029: * between the two by capturing the state of the SAVEPTRS interrupt
2030: * prior to clearing this status and executing the common code for
2031: * these two cases.
2032: */
2033: pkt_saveptrs:
2034: BEGIN_CRITICAL;
2035: if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
2036: or DFCNTRL, FIFOFLUSH;
2037: }
2038: mov REG0, SEQINTSRC;
2039: call calc_residual;
2040: call save_pointers;
2041: mvi CLRSEQINTSRC, CLRSAVEPTRS;
2042: call disable_ccsgen;
2043: or SEQIMODE, ENSAVEPTRS;
2044: test DFCNTRL, DIRECTION jnz pkt_saveptrs_check_status;
2045: test DFSTATUS, FIFOEMP jnz pkt_saveptrs_check_status;
2046: /*
2047: * Keep a handler around for this FIFO until it drains
2048: * to the host to guarantee that we don't complete the
2049: * command to the host before the data arrives.
2050: */
2051: pkt_saveptrs_wait_fifoemp:
2052: call setjmp;
2053: test DFSTATUS, FIFOEMP jz return;
2054: pkt_saveptrs_check_status:
2055: or LONGJMP_ADDR[1], INVALID_ADDR;
2056: test REG0, SAVEPTRS jz unexpected_nonpkt_phase;
2057: dec SCB_FIFO_USE_COUNT;
2058: test SCB_CONTROL, STATUS_RCVD jnz pkt_complete_scb_if_fifos_idle;
2059: mvi DFFSXFRCTL, CLRCHN ret;
2060:
2061: /*
2062: * LAST_SEG_DONE status has been seen in the current FIFO.
2063: * This indicates that all of the allowed data for this
2064: * command has transferred across the SCSI and host buses.
2065: * Check for overrun and see if we can complete this command.
2066: */
2067: pkt_last_seg_done:
2068: /*
2069: * Mark transfer as completed.
2070: */
2071: or SCB_SGPTR, SG_LIST_NULL;
2072:
2073: /*
2074: * Wait for the current context to finish to verify that
2075: * no overrun condition has occurred.
2076: */
2077: test SEQINTSRC, CTXTDONE jnz pkt_ctxt_done;
2078: call setjmp;
2079: pkt_wait_ctxt_done_loop:
2080: test SEQINTSRC, CTXTDONE jnz pkt_ctxt_done;
2081: /*
2082: * A sufficiently large overrun or a NONPACKREQ may
2083: * prevent CTXTDONE from ever asserting, so we must
2084: * poll for these statuses too.
2085: */
2086: check_overrun;
2087: test SSTAT2, NONPACKREQ jz return;
2088: test SEQINTSRC, CTXTDONE jz unexpected_nonpkt_phase;
2089: /* FALLTHROUGH */
2090:
2091: pkt_ctxt_done:
2092: check_overrun;
2093: or LONGJMP_ADDR[1], INVALID_ADDR;
2094: /*
2095: * If status has been received, it is safe to skip
2096: * the check to see if another FIFO is active because
2097: * LAST_SEG_DONE has been observed. However, we check
2098: * the FIFO anyway since it costs us only one extra
2099: * instruction to leverage common code to perform the
2100: * SCB completion.
2101: */
2102: dec SCB_FIFO_USE_COUNT;
2103: test SCB_CONTROL, STATUS_RCVD jnz pkt_complete_scb_if_fifos_idle;
2104: mvi DFFSXFRCTL, CLRCHN ret;
2105: END_CRITICAL;
2106:
2107: /*
2108: * Must wait until CDB xfer is over before issuing the
2109: * clear channel.
2110: */
2111: pkt_handle_cdb:
2112: call setjmp;
2113: test SG_CACHE_SHADOW, LAST_SEG_DONE jz return;
2114: or LONGJMP_ADDR[1], INVALID_ADDR;
2115: mvi DFFSXFRCTL, CLRCHN ret;
2116:
2117: /*
2118: * Watch over the status transfer. Our host sense buffer is
2119: * large enough to take the maximum allowed status packet.
2120: * None-the-less, we must still catch and report overruns to
2121: * the host. Additionally, properly catch unexpected non-packet
2122: * phases that are typically caused by CRC errors in status packet
2123: * transmission.
2124: */
2125: pkt_handle_status:
2126: call setjmp;
2127: test SG_CACHE_SHADOW, LAST_SEG_DONE jnz pkt_status_check_overrun;
2128: test SEQINTSRC, CTXTDONE jz pkt_status_check_nonpackreq;
2129: test SG_CACHE_SHADOW, LAST_SEG_DONE jnz pkt_status_check_overrun;
2130: pkt_status_IU_done:
2131: if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
2132: or DFCNTRL, FIFOFLUSH;
2133: }
2134: test DFSTATUS, FIFOEMP jz return;
2135: BEGIN_CRITICAL;
2136: or LONGJMP_ADDR[1], INVALID_ADDR;
2137: mvi SCB_SCSI_STATUS, STATUS_PKT_SENSE;
2138: or SCB_CONTROL, STATUS_RCVD;
2139: jmp pkt_complete_scb_if_fifos_idle;
2140: END_CRITICAL;
2141: pkt_status_check_overrun:
2142: /*
2143: * Status PKT overruns are unceremoniously recovered with a
2144: * bus reset. If we've overrun, let the host know so that
2145: * recovery can be performed.
2146: *
2147: * LAST_SEG_DONE has been observed. If either CTXTDONE or
2148: * a NONPACKREQ phase change have occurred and the FIFO is
2149: * empty, there is no overrun.
2150: */
2151: test DFSTATUS, FIFOEMP jz pkt_status_report_overrun;
2152: test SEQINTSRC, CTXTDONE jz . + 2;
2153: test DFSTATUS, FIFOEMP jnz pkt_status_IU_done;
2154: test SCSIPHASE, ~DATA_PHASE_MASK jz return;
2155: test DFSTATUS, FIFOEMP jnz pkt_status_check_nonpackreq;
2156: pkt_status_report_overrun:
2157: SET_SEQINTCODE(STATUS_OVERRUN)
2158: /* SEQUENCER RESTARTED */
2159: pkt_status_check_nonpackreq:
2160: /*
2161: * CTXTDONE may be held off if a NONPACKREQ is associated with
2162: * the current context. If a NONPACKREQ is observed, decide
2163: * if it is for the current context. If it is for the current
2164: * context, we must defer NONPACKREQ processing until all data
2165: * has transferred to the host.
2166: */
2167: test SCSIPHASE, ~DATA_PHASE_MASK jz return;
2168: test SCSISIGO, ATNO jnz . + 2;
2169: test SSTAT2, NONPACKREQ jz return;
2170: test SEQINTSRC, CTXTDONE jnz pkt_status_IU_done;
2171: test DFSTATUS, FIFOEMP jz return;
2172: /*
2173: * The unexpected nonpkt phase handler assumes that any
2174: * data channel use will have a FIFO reference count. It
2175: * turns out that the status handler doesn't need a reference
2176: * count since the status received flag, and thus completion
2177: * processing, cannot be set until the handler is finished.
2178: * We increment the count here to make the nonpkt handler
2179: * happy.
2180: */
2181: inc SCB_FIFO_USE_COUNT;
2182: /* FALLTHROUGH */
2183:
2184: /*
2185: * Nonpackreq is a polled status. It can come true in three situations:
2186: * we have received an L_Q, we have sent one or more L_Qs, or there is no
2187: * L_Q context associated with this REQ (REQ occurs immediately after a
2188: * (re)selection). Routines that know that the context responsible for this
2189: * nonpackreq call directly into unexpected_nonpkt_phase. In the case of the
2190: * top level idle loop, we exhaust all active contexts prior to determining that
2191: * we simply do not have the full I_T_L_Q for this phase.
2192: */
2193: unexpected_nonpkt_phase_find_ctxt:
2194: /*
2195: * This nonpackreq is most likely associated with one of the tags
2196: * in a FIFO or an outgoing LQ. Only treat it as an I_T only
2197: * nonpackreq if we've cleared out the FIFOs and handled any
2198: * pending SELDO.
2199: */
2200: SET_SRC_MODE M_SCSI;
2201: SET_DST_MODE M_SCSI;
2202: and A, FIFO1FREE|FIFO0FREE, DFFSTAT;
2203: cmp A, FIFO1FREE|FIFO0FREE jne return;
2204: test SSTAT0, SELDO jnz return;
2205: mvi SCBPTR[1], SCB_LIST_NULL;
2206: unexpected_nonpkt_phase:
2207: test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
2208: jnz unexpected_nonpkt_mode_cleared;
2209: SET_SRC_MODE M_DFF0;
2210: SET_DST_MODE M_DFF0;
2211: or LONGJMP_ADDR[1], INVALID_ADDR;
2212: dec SCB_FIFO_USE_COUNT;
2213: mvi DFFSXFRCTL, CLRCHN;
2214: unexpected_nonpkt_mode_cleared:
2215: mvi CLRSINT2, CLRNONPACKREQ;
2216: if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
2217: /*
2218: * Test to ensure that the bus has not
2219: * already gone free prior to clearing
2220: * any stale busfree status. This avoids
2221: * a window whereby a busfree just after
2222: * a selection could be missed.
2223: */
2224: test SCSISIGI, BSYI jz . + 2;
2225: mvi CLRSINT1,CLRBUSFREE;
2226: or SIMODE1, ENBUSFREE;
2227: }
2228: test SCSIPHASE, ~(MSG_IN_PHASE|MSG_OUT_PHASE) jnz illegal_phase;
2229: SET_SEQINTCODE(ENTERING_NONPACK)
2230: jmp ITloop;
2231:
2232: illegal_phase:
2233: SET_SEQINTCODE(ILLEGAL_PHASE)
2234: jmp ITloop;
2235:
2236: /*
2237: * We have entered an overrun situation. If we have working
2238: * BITBUCKET, flip that on and let the hardware eat any overrun
2239: * data. Otherwise use an overrun buffer in the host to simulate
2240: * BITBUCKET.
2241: */
2242: pkt_handle_overrun_inc_use_count:
2243: inc SCB_FIFO_USE_COUNT;
2244: pkt_handle_overrun:
2245: SET_SEQINTCODE(CFG4OVERRUN)
2246: call freeze_queue;
2247: if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) == 0) {
2248: or DFFSXFRCTL, DFFBITBUCKET;
2249: SET_SRC_MODE M_DFF1;
2250: SET_DST_MODE M_DFF1;
2251: } else {
2252: call load_overrun_buf;
2253: mvi DFCNTRL, (HDMAEN|SCSIEN|PRELOADEN);
2254: }
2255: call setjmp;
2256: if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
2257: test DFSTATUS, PRELOAD_AVAIL jz overrun_load_done;
2258: call load_overrun_buf;
2259: or DFCNTRL, PRELOADEN;
2260: overrun_load_done:
2261: test SEQINTSRC, CTXTDONE jnz pkt_overrun_end;
2262: } else {
2263: test DFFSXFRCTL, DFFBITBUCKET jz pkt_overrun_end;
2264: }
2265: test SSTAT2, NONPACKREQ jz return;
2266: pkt_overrun_end:
2267: or SCB_RESIDUAL_SGPTR, SG_OVERRUN_RESID;
2268: test SEQINTSRC, CTXTDONE jz unexpected_nonpkt_phase;
2269: dec SCB_FIFO_USE_COUNT;
2270: or LONGJMP_ADDR[1], INVALID_ADDR;
2271: test SCB_CONTROL, STATUS_RCVD jnz pkt_complete_scb_if_fifos_idle;
2272: mvi DFFSXFRCTL, CLRCHN ret;
2273:
2274: if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
2275: load_overrun_buf:
2276: /*
2277: * Load a dummy segment if preload space is available.
2278: */
2279: mov HADDR[0], SHARED_DATA_ADDR;
2280: add HADDR[1], PKT_OVERRUN_BUFOFFSET, SHARED_DATA_ADDR[1];
2281: mov ACCUM_SAVE, A;
2282: clr A;
2283: adc HADDR[2], A, SHARED_DATA_ADDR[2];
2284: adc HADDR[3], A, SHARED_DATA_ADDR[3];
2285: mov A, ACCUM_SAVE;
2286: bmov HADDR[4], ALLZEROS, 4;
2287: /* PKT_OVERRUN_BUFSIZE is a multiple of 256 */
2288: clr HCNT[0];
2289: mvi HCNT[1], ((PKT_OVERRUN_BUFSIZE >> 8) & 0xFF);
2290: clr HCNT[2] ret;
2291: }
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