Annotation of sys/dev/isa/isareg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: isareg.h,v 1.3 2003/06/02 23:28:03 millert Exp $ */
2: /* $NetBSD: isareg.h,v 1.5 1995/04/17 12:09:13 cgd Exp $ */
3:
4: /*-
5: * Copyright (c) 1990 The Regents of the University of California.
6: * All rights reserved.
7: *
8: * This code is derived from software contributed to Berkeley by
9: * William Jolitz.
10: *
11: * Redistribution and use in source and binary forms, with or without
12: * modification, are permitted provided that the following conditions
13: * are met:
14: * 1. Redistributions of source code must retain the above copyright
15: * notice, this list of conditions and the following disclaimer.
16: * 2. Redistributions in binary form must reproduce the above copyright
17: * notice, this list of conditions and the following disclaimer in the
18: * documentation and/or other materials provided with the distribution.
19: * 3. Neither the name of the University nor the names of its contributors
20: * may be used to endorse or promote products derived from this software
21: * without specific prior written permission.
22: *
23: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33: * SUCH DAMAGE.
34: *
35: * @(#)isa.h 5.7 (Berkeley) 5/9/91
36: */
37:
38: /*
39: * ISA Bus conventions
40: */
41:
42: /*
43: * Input / Output Port Assignments
44: */
45:
46: #ifndef IO_ISABEGIN
47: #define IO_ISABEGIN 0x000 /* 0x000 - Beginning of I/O Registers */
48:
49: /* CPU Board */
50: #define IO_DMA1 0x000 /* 8237A DMA Controller #1 */
51: #define IO_ICU1 0x020 /* 8259A Interrupt Controller #1 */
52: #define IO_PMP1 0x026 /* 82347 Power Management Peripheral */
53: #define IO_TIMER1 0x040 /* 8253 Timer #1 */
54: #define IO_TIMER2 0x048 /* 8253 Timer #2 (EISA only) */
55: #define IO_KBD 0x060 /* 8042 Keyboard */
56: #define IO_PPI 0x061 /* Programmable Peripheral Interface */
57: #define IO_RTC 0x070 /* RTC */
58: #define IO_NMI IO_RTC /* NMI Control */
59: #define IO_DMAPG 0x080 /* DMA Page Registers */
60: #define IO_ICU2 0x0A0 /* 8259A Interrupt Controller #2 */
61: #define IO_DMA2 0x0C0 /* 8237A DMA Controller #2 */
62: #define IO_NPX 0x0F0 /* Numeric Coprocessor */
63:
64: /* Cards */
65: /* 0x100 - 0x16F Open */
66:
67: #define IO_WD2 0x170 /* Secondary Fixed Disk Controller */
68: #define IO_PMP2 0x178 /* 82347 Power Management Peripheral */
69:
70: /* 0x17A - 0x1EF Open */
71:
72: #define IO_WD1 0x1f0 /* Primary Fixed Disk Controller */
73: #define IO_GAME 0x200 /* Game Controller */
74:
75: /* 0x208 - 0x237 Open */
76:
77: #define IO_BMS2 0x238 /* secondary InPort Bus Mouse */
78: #define IO_BMS1 0x23c /* primary InPort Bus Mouse */
79:
80: /* 0x240 - 0x277 Open */
81:
82: #define IO_LPT2 0x278 /* Parallel Port #2 */
83:
84: /* 0x280 - 0x2E7 Open */
85:
86: #define IO_COM4 0x2e8 /* COM4 i/o address */
87:
88: /* 0x2F0 - 0x2F7 Open */
89:
90: #define IO_COM2 0x2f8 /* COM2 i/o address */
91:
92: /* 0x300 - 0x32F Open */
93:
94: #define IO_BT0 0x330 /* bustek 742a default addr. */
95: #define IO_AHA0 0x330 /* adaptec 1542 default addr. */
96: #define IO_UHA0 0x330 /* ultrastore 14f default addr. */
97: #define IO_BT1 0x334 /* bustek 742a default addr. */
98: #define IO_AHA1 0x334 /* adaptec 1542 default addr. */
99:
100: /* 0x338 - 0x34F Open */
101:
102: #define IO_WDS 0x350 /* WD7000 scsi */
103:
104: /* 0x354 - 0x36F Open */
105:
106: #define IO_FD2 0x370 /* secondary base i/o address */
107: #define IO_LPT1 0x378 /* Parallel Port #1 */
108:
109: /* 0x380 - 0x3AF Open */
110:
111: #define IO_MDA 0x3B0 /* Monochome Adapter */
112: #define IO_LPT3 0x3BC /* Monochome Adapter Printer Port */
113: #define IO_VGA 0x3C0 /* E/VGA Ports */
114: #define IO_CGA 0x3D0 /* CGA Ports */
115:
116: /* 0x3E0 - 0x3E7 Open */
117:
118: #define IO_COM3 0x3e8 /* COM3 i/o address */
119: #define IO_FD1 0x3f0 /* primary base i/o address */
120: #define IO_COM1 0x3f8 /* COM1 i/o address */
121:
122: #define IO_ISAEND 0x3FF /* - 0x3FF End of I/O Registers */
123: #endif /* !IO_ISABEGIN */
124:
125: /*
126: * Input / Output Port Sizes - these are from several sources, and tend
127: * to be the larger of what was found, ie COM ports can be 4, but some
128: * boards do not fully decode the address, thus 8 ports are used.
129: */
130:
131: #ifndef IO_ISASIZES
132: #define IO_ISASIZES
133:
134: #define IO_COMSIZE 8 /* 8250, 16X50 com controllers */
135: #define IO_CGASIZE 16 /* CGA controllers */
136: #define IO_DMASIZE 16 /* 8237 DMA controllers */
137: #define IO_DPGSIZE 32 /* 74LS612 DMA page reisters */
138: #define IO_FDCSIZE 8 /* Nec765 floppy controllers */
139: #define IO_WDCSIZE 8 /* WD compatible disk controller */
140: #define IO_GAMSIZE 16 /* AT compatible game controller */
141: #define IO_ICUSIZE 16 /* 8259A interrupt controllers */
142: #define IO_KBDSIZE 16 /* 8042 Keyboard controllers */
143: #define IO_LPTSIZE 8 /* LPT controllers, some use onl */
144: #define IO_MDASIZE 16 /* Monochrome display controller */
145: #define IO_RTCSIZE 16 /* CMOS real time clock, NMI con */
146: #define IO_TMRSIZE 16 /* 8253 programmable timers */
147: #define IO_NPXSIZE 16 /* 80387/80487 NPX registers */
148: #define IO_VGASIZE 16 /* VGA controllers */
149: #define IO_PMPSIZE 2 /* 82347 Power Management Peripheral */
150: #endif /* !IO_ISASIZES */
151:
152: /*
153: * Input / Output Memory Physical Addresses
154: */
155:
156: #ifndef IOM_BEGIN
157: #define IOM_BEGIN 0x0a0000 /* Start of I/O Memory "hole" */
158: #define IOM_END 0x100000 /* End of I/O Memory "hole" */
159: #define IOM_SIZE (IOM_END - IOM_BEGIN)
160: #endif /* !IOM_BEGIN */
CVSweb
![[BACK]](/icons/back.gif){kind=icon}
Return to isareg.h CVS log ![[TXT]](/icons/text.gif){kind=icon}
![[DIR]](/icons/dir.gif){kind=icon}
Up to [local] / sys / dev / isa